RMPA2450 2.4–2.5 GHz GaAs MMIC Power Amplifier General Description Features The Fairchild RMPA2450 is a fully monolithic power amplifier in a surface mount package for use in wireless applications in the 2.4 to 2.5GHz ISM frequency band. The amplifier may be biased for linear, class AB or class F for high efficiency applications. On-chip matching components allow operation in a 50Ω system with no external matching components. The MMIC chip design utilizes our 0.25µm power PHEMT process. • • • • • • 35% Power Added Efficiency 31dBm Output Power (P1dB) at Vd = +7V 28dBm Output Power (P1dB) at Vd = +5V No external RF matching components Small Package Outline: 0.28" x 0.28" x 0.07" Thermal Resistance (Channel to Case): 33°C/W Device Absolute Ratings Symbol Vd1, Vd2 Vg1, Vg2 Vd–Vg PIN Ids Ig Tch TCASE TSTG Parameter Positive Drain DC Voltage Negative Gate DC Voltage Simultaneous Drain to Gate Voltage RF Input Power (from 50Ω source) Drain to Source Current Gate Current Channel Temperature Operating Case Temperature Storage Temperature Range ©2004 Fairchild Semiconductor Corporation Rating +8 -5 +10 +10 575 5 150 -40 to 100 -40 to 125 Units V V V dBm mA mA °C °C °C RMPA2450 Rev. C RMPA2450 May 2004 Parameter Frequency Range Gain1, 2, 4 Output Power, P1dB1,4 Assoc. Power Added Efficiency Output Power, P1dB3 Assoc. Power Added Efficiency Drain Current (Idd1 + Idd2) Gate Current (Igg1 + Igg2) Input Return Loss (50Ω) Min 2400 Typ 2450 30 28 35 31 33 Max 2500 550 5 7.5 Units MHz dB dBm % dBm % mA mA dB Notes: 1: Idq = 360mA, Vd1 = Vd2 = 5.0V 2: Pin = -3dBm, 3: Vd1 = Vd2 = +7V 4: Production Testing includes Gain, Output Power (P1dB) and Input Return Loss at Vd1 = Vd2 = 5.0V, Vg1 = Vg2 = -0.5V (nominal) , adjusted for Idq = 360mA, Pin = -3 dBm and at F = 2.45 GHz. Other Parameters are guaranteed by Design Validation Testing. Vd2 Pin# 4 Vd1 Pin# 5 Ground Pin# 1, 3, 6, 7, 9, 12, 13 RF OUT Pins# 2 RF IN Pin# 8 Vg2 Pin# 11 Vg1 Pin# 10 Figure 1. Functional Block Diagram (RMPA2450) TOP VIEW 0.200 SQ. BOTTOM VIEW 654 A 45 6 3 7 8 RMPA 2450 0.030 2 9 2 8 9 1 1 12 10 7 3 0.015 0.041 12 11 11 10 0.069 MAX. PLASTIC LID Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 Description GND RF Out GND Vd2 Vd1 GND GND RF GND Vg1 Vg2 GND GND (PACKAGE BASE) 0.010 0.230 0.246 0.282 Dimensions in inches SIDE SECTION Figure 2. Outline Dimensions (RMPA2450) ©2004 Fairchild Semiconductor Corporation RMPA2450 Rev. C RMPA2450 Electrical Characteristics (Note 4, At 25°C, ZO = 50Ω, Unless Otherwise Noted) The following briefly describes a procedure for evaluating the high efficiency PHEMT amplifier packaged in a surface mount package. It may be noted that the chip is a fully monolithic amplifier for ISM band applications. Figure 1 shows the functional block diagram of the packaged product. Test Fixture Figure 2 shows the outline and pin-out descriptions for the packaged device. A typical test fixture schematic showing external bias components is shown in Figure 3. Figure 4 shows typical layout of an evaluation board corresponding to the schematic diagram. The following should be noted: (1) Package pin designations are as shown in Figure 2. Test Procedure for the Evaluation Board (RMPA2450-TB) The following sequence of procedure must be followed to properly test the power amplifier: CAUTION: LOSS OF GATE VOLTAGES (VG1, VG2) WHILE DRAIN VOLTAGES (VD1,VD2) ARE PRESENT MAY DAMAGE THE AMPLIFIER. Step 1: Turn off RF input power. Step 2: Use GND terminal of the evaluation board for DC supplies. Apply gate supply voltages of typical -0.5V to evaluation board terminals Vgg. (3) Vgg1 = Vgg2 = Vgg is the negative supply voltage at the evaluation board terminal Step 3: Apply drain supply voltages of +5.0V to evaluation board terminals Vdd. Adjust gate supply voltage, if needed, to set the desired quiescent bias currents Idq (or to the values as shown on the data summary accompanying the product samples). (4) Vd1, Vd2 are the Drain Voltages (positive) applied at the pins of the package Step 4: After the bias condition is established, RF input signal may now be applied. (5) Vdd1 = Vdd2 = Vdd is the positive supply voltage at the evaluation board terminal Step 5: Follow turn-off sequence of: (i) Turn off RF Input Power (ii) Turn down and off Vdd (iii) Turn down and off Vgg (2) Vg1, Vg2 are the Gate Voltages (negative) applied at the pins of the package ©2004 Fairchild Semiconductor Corporation RMPA2450 Rev. C RMPA2450 Application Information CAUTION: THIS IS AN ESD SENSITIVE DEVICE. 6 C6 4 3 7 RF IN J1 C4 (Opt) Vdd P2 RF OUT J2 RMPA 2450 9 1 U1 12 GND P3 Vgg P1 C5 + C3 (Opt) C1 Figure 3. Schematic for a Typical Test Evaluation Board (RMPA2450-TB) Parts List for Test Evaluation Board (RMPA2450-TB), G654220 Part C1, C2 C3, C4 C5, C6 U1 P1, P2, P3 J1, J2 Board Rating 330pF 1000pF 4.75µF RMPA2550 Terminals SMA Connectors FR4 ©2004 Fairchild Semiconductor Corporation Size (L" X W") .04" X .02" .04" X .02" .14" X .11" .28" X .28" X .07 Vendors AVX, Murata, Novacap AVX, Murata, Novacap Sprague, ATC, AVX, Murata Sametec E.F. Johnson RMPA2450 Rev. C RMPA2450 C2 + RMPA2450 C4 4 C2 C6 Vdd1=Vdd2 (+Vdd ) P2 U1 P1 C4 C2 RF In J1 RF Out J2 U1 C1 C1 C3 C3 P2 P3 C5 Vgg1=Vgg2 (-Vgg ) P1 Ground (GND) P3 Figure 4. Layout and Assembly of Test Evaluation Board (RMPA2450-TB) ©2004 Fairchild Semiconductor Corporation RMPA2450 Rev. C TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FAST ActiveArray™ FASTr™ Bottomless™ FPS™ CoolFET™ FRFET™ CROSSVOLT™ GlobalOptoisolator™ DOME™ GTO™ EcoSPARK™ HiSeC™ E2CMOS™ I2C™ EnSigna™ i-Lo™ FACT™ ImpliedDisconnect™ FACT Quiet Series™ ISOPLANAR™ LittleFET™ MICROCOUPLER™ MicroFET™ MicroPak™ MICROWIRE™ MSX™ MSXPro™ OCX™ OCXPro™ OPTOLOGIC Across the board. Around the world.™ OPTOPLANAR™ PACMAN™ The Power Franchise POP™ Programmable Active Droop™ Power247™ PowerSaver™ PowerTrench QFET QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ µSerDes™ SILENT SWITCHER SMART START™ SPM™ Stealth™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic TINYOPTO™ TruTranslation™ UHC™ UltraFET VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I11