FUJITSU MB15E06

FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-21336-2E
ASSP
Single Serial Input
PLL Frequency Synthesizer
On-Chip 2.5 GHz Prescaler
MB15E06
■ DESCRIPTION
The Fujitsu MB15E06 is serial input Phase Locked Loop (PLL) frequency synthesizers with a 2.5 GHz prescaler. A
64/65 or a 128/129 can be selected for the prescaler that enables pulse swallow operation.
The latest BiCMOS process technology is used, resuItantly a supply current is limited as low as 8 mA typ. This operates with a supply voltage of 3.0 V (typ.) .
Furthermore, a super charger circuit is included to get a fast tuning as well as low noise performance. As a result of
this, MB15E06 is ideally suitable for digital mobile communications, such as GPS (Global Positioning System) ,
Wireless LAN, CATV (CAble TeleVision) etc.
■ FEATURES
•
•
•
•
•
•
•
High frequency operation : 2.5 GHz max
Low power supply voltage : VCC = 2.7 to 3.6 V
Very Low power supply current : ICC = 8.0 mA typ. (VCC = 3 V)
Power saving function : IPS = 10 µA max.
Pulse swallow function : 64/65 or 128/129
Serial input 14-bit programmable reference divider : R = 5 to 16, 383
Serial input 18-bit programmable divider consisting of:
- Binary 7-bit swallow counter : 0 to 127
- Binary 11-bit programmable counter : 5 to 2, 047
• Wide operating temperature : Ta = −40 to 85 °C
• Plastic 16-pin SSOP package (FPT-16P-M05)
■ PACKAGE
16-pin plastic SSOP
16-pad plastic BCC
(FPT-16P-M05)
(LCC-16P-M06)
MB15E06
■ PIN ASSIGNMENT
(TOP VIEW)
OSCIN
1
16
φR
OSCOUT
2
15
φP
VP
3
14
LD/fout
VCC
4
DO
5
TOP 13
VIEW
12
ZC
PS
GND
6
11
LE
Xfin
7
10
Data
fin
8
9
Clock
(FPT-16P-M05)
2
(TOP VIEW)
OSCIN φR
OSCOUT
1
VP
2
VCC
DO
3
4
GND
5
Xfin
6
16 15
14
13
12
11
10
7
8
9
fin Clock
(LCC-16P-M06)
φP
LD/fout
ZC
PS
LE
Data
MB15E06
■ PIN DESCRIPTIONS
Pin No.
Pin Name
I/O
Descriptions
1 (16)
OSCIN
I
Programmable reference divider input.
Oscillator input connection to a TCXO.
2 (1)
OSCOUT
O
Oscillator output.
3 (2)
VP

Power supply voltage input for the charge pump.
4 (3)
VCC

Power supply voltage input.
5 (4)
DO
O
Charge pump output.
Phase of the charge pump can be reversed by FC input.
6 (5)
GND

Ground.
7 (6)
Xfin
I
Prescaler complementary input, and should be grounded via a capacitor.
8 (7)
fin
I
Prescaler input.
Connection with an external VCO should be done with AC coupling.
9 (8)
Clock
I
Clock input for the 19-bit shift register.
Data is shifted into the shift register on the rising edge of the clock. (Open is
prohibited.)
10 (9)
Data
I
Serial data input using binary code.
The last bit of the data is a control bit. (Open is prohibited.)
Control bit = “H” ; Data is transmitted to the programmable reference
counter.
Control bit = “L” ; Data is transmitted to the programmable counter.
11 (10)
LE
I
Load enable signal input (Open is prohibited.)
When LE is high, the data in the shift register is transferred to a latch,
according to the control bit in the serial data.
I
Power saving mode control. This pin must be set at “L” at Power-ON.
(Open is prohibited.)
PS = “H” ; Normal mode
PS = “L” ; Power saving mode
I
Forced high-impedance control for the charge pump (with internal pull up
resistor.)
ZC = “H” ; Normal Do output.
ZC = “L” ; Do becomes high impedance.
12 (11)
13 (12)
PS
ZC
14 (13)
LD/fout
O
Lock detect signal output (LD) /phase comparator monitoring
output (fout) .
The output signal is selected by LDS bit in the serial data.
LDS = “H” ; outputs fout (fr/fp monitoring output)
LDS = “L” ; outputs LD (“H” at locking, “L” at unlocking.)
15 (14)
φP
O
Phase comparator output for an external charge pump.
16 (15)
φR
O
Phase comparator output for an external charge pump.
( ) : for Bcc Package.
3
MB15E06
■ BLOCK DIAGRAM
fr
(16)
OSCIN 1
Crystal
Oscillator
circuit
(15)
Phase
comparator
(14)
(1)
OSCOUT 2
15 φP
(2)
VP 3
Binary 14-bit
reference counter
SW FC LDS
14-bit latch
3-bit latch
Lock
detector
fp
C
N
T
(3)
4
(4)
DO 5
Super charger
VCC
16 φR
LD/fr/fp
selector
(13) LD/
14 fout
(12)
19-bit shift register
13 ZC
7-bit latch
Binary 7-bit
swallow counter
11-bit latch
Binary 11-bit
programmable
counter
Intermittent
mode control
(power save)
(11)
12 PS
(10)
(5)
GND 6
11 LE
Control
1-bit
(9)
(6)
X fin 7
MD
10 Data
Prescaler
64/65,
128/129
(7)
fin 8
for SSOP Package
( ) for BCC Package
4
(8)
9
Clock
MB15E06
■ ABSOLUTE MAXIMUM RAGINGS
Parameter
Symbol
Rating
Unit
Min.
Max.
VCC
−0.5
+4.0
V
VP
VCC
+6.0
V
Output voltage
VO
−0.5
VCC +0.5
V
Input voltage
VI
−0.5
VCC +0.5
V
Output current
IO
−10
+10
mA
VOOP
−0.5
+7.0
V
Tstg
−55
+125
°C
Power supply voltage
Open drain withstand voltage
Storage temperature
Remark
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Unit
Min.
Typ.
Max.
VCC
2.7
3.0
3.6
V
VP
VCC

6.0
V
Input voltage
VI
GND

VCC
V
Operating temperature
Ta
−40

+85
°C
Power supply voltage
Remark
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
5
MB15E06
■ ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Condition
Power supply current*1
ICC
Power saving current*2
Ips
Operating frequency
fin
Crystal oscillator operating frequency
fOSC
fin
OSCin
Input sensitivity
Input voltage
Input current
Typ.
Max.
finIF = 2500 MHz,
fosc = 12 MHz

8.0

mA
Vcc current at
PS = “L” and
ZC = “H”


10
µA
100

2500
MHz
min. 500 mVp−p
3

40
MHz
VfinIF
50 Ω termination
(Refer to the test
circuit.)
–10

+2
dBm
VOSC

500

VCC
mVp−p
Data, Clock,
LE, PS, ZC
VIH

VCC × 0.7


VIL



VCC × 0.3
Data, Clock,
LE, PS
IIH

−1.0

+1.0
IIL

−1.0

+1.0
IIH

−1.0

+1.0
−100

0
ZC
IIL

Pull up input
µA
µA

0

+100
IIL

−100

0
φP
VOL
Open drain output


0.4
φR,
LD/fout
VOH

VCC − 0.4

–
VOL



0.4
VDOH

VP − 0.4

–
VDOL



0.4
Do
IOFF



1.1
µA
φP
IOL
Open drain output
1.0


mA
φR,
LD/fou
IOH



−1.0
IOL

1.0


−10.0*2

Output current
IDOH
VCC = 3.0 V,
Vp = 5 V,
VDOH = 4.0 V

IDOL
VCC = 3.0 V,
Vp = 5 V,
VDOL = 1.0 V

Do
*1 : Conditions ; VCC = 3.0 V, Ta = 25 °C, in locking state.
*2 : Conditions ; Ta = 25 °C
6
V
IIH
Do
High impedance
cutoff current
Unit
Min.
OSCin
Output voltage
Value
µA
V
V
V
mA
mA
10.0*2

MB15E06
■ FUNCTION DESCRIPTIONS
Pulse Swallow Function
The divide ratio can be calculated using the following equation :
fVCO = [ (M × N) + A] × fOSC ÷ R (A < N)
fVCO : Output frequency of external voltage controlled oscillator (VCO)
N
: Preset divide ratio of binary 11-bit programmable counter (5 to 2,047)
A
: Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)
fOSC : Output frequency of the reference frequency oscillator
R
: Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383)
M
: Preset divide ratio of modules prescaler (64 or 128)
Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference
divider and the programmable divider separately.
Binary serial data is entered through the Data pin.
One bit of data is shifted into the shift register on the rising edge of the clock. When the load enable pin is high,
stored data is latched according to the control bit data as follows:
Table.1 Control Bit
Control bit (CNT)
Destination of serial data
H
17 bit latch (for the programmable reference divider)
L
18 bit latch (for the programmable divider)
Shift Register Configuration
Programmable Reference Counter
LSB
Data Flow
MSB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
C
N
T
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
10
R
11
R
12
R
13
R
14 SW FC LDS
CNT
R1 to R14
SW
FC
LDS
16
17
: Control bit
: Divide ratio setting bit for the programmable reference counter (5 to 16,383)
: Divide ratio setting bit for the prescaler (64/65 or 128/129)
: Phase control bit for the phase comparator
: LD/fout signal select bit
18
[Table. 1]
[Table. 2]
[Table. 5]
[Table. 7]
[Table. 6]
Note : Start data input with MSB first
7
MB15E06
Programmable Reference Counter
LSB
Data Flow
MSB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C
N
T
A
1
A
2
A
3
A
4
A
5
A
6
A
7
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
10
N
11
CNT
: Control bit
[Table. 1]
[Table. 3]
[Table. 4]
N1 to N11 : Divide ratio setting bits for the programmable counter (5 to 2,047)
A1 to A7
: Divide ratio setting bits for the swallow counter (0 to 127)
Note : Start data input with MSB first
Table2. Binary 14-bit Programmable Reference Counter Data Setting
Divide
ratio
(R)
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
5
0
0
0
0
0
0
0
0
0
0
0
1
0
1
6
0
0
0
0
0
0
0
0
0
0
0
1
1
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note : • Divide ratio less than 5 is prohibited.
Table.3 Binary 11-bit Programmable Counter Data Setting
Divide
ratio
(N)
N
11
N
10
N
9
N
8
N
7
N
6
N
5
N
4
N
3
N
2
N
1
5
0
0
0
0
0
0
0
0
1
0
1
6
0
0
0
0
0
0
0
0
1
1
0
•
•
•
•
•
•
•
•
•
•
•
•
2047
1
1
1
1
1
1
1
1
1
1
1
Note : • Divide ratio less than 5 is prohibited.
• Divide ratio (N) range = 5 to 2,047
8
MB15E06
Table.4 Binary 7-bit Swallow Counter Data Setting
Divide
ratio
(A)
A
7
A
6
A
5
A
4
A
3
A
2
A
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
•
•
•
•
•
•
•
•
127
1
1
1
1
1
1
1
Note : • Divide ratio (A) range = 0 to 127
Table. 5 Prescaler Data Setting
SW
Prescaler Divide ratio
H
64/65
L
128/129
Table. 6 LD/fout Output Select Data Setting
LDS
LD/fout output signal
H
fout signal
L
LD signal
Relation between the FC input and phase characteristics
The FC bit changes the phase characteristics of the phase comparator. Both the internal charge pump output level
(DO) and the phase comparator output (φR, φP) are reversed according to the FC bit. Also, the monitor pin (fOUT)
output is controlled by the FC bit. The relationship between the FC bit and each of DO, φR, and φP is shown below.
Table. 7 FC Bit Data Setting (LDS = “H”)
FC = High
FC = Low
Do
φR
φP
LD/fout
Do
φR
φP
LD/fout
fr > fp
H
L
L
(fr)
L
H
Z*
(fp)
fr < fp
L
H
Z*
(fr)
H
L
L
(fp)
fr = fp
Z*
L
Z*
(fr)
Z*
L
Z*
(fp)
* : High impedance
9
MB15E06
When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics.
* : When the LPF and VCO characteristics are
similar to (1) , set FC bit high.
High
(1)
* : When the VCO characteristics are similar to
(2) , set FC bit low.
VCO
Output
Frequency
( 2)
LPF Output Voltage
Large
3. Power Saving Mode (Intermittent Mode Control Circuit)
Setting a PS pin to Low, the IC enters into power saving mode resultatly current sonsumption can be limited to
10 µA (max.) . Setting PS pin to High, power saving mode is released so that the IC works normally.
In addition, the intermittent operation control circuit is included which helps smooth start up from the power
saving mode. In general, the power consumption can be saved by the intermittent operation that powering down
or waking up the synthesizer. Such case, if the PLL is powered up uncontrolled, the resulting phase comparator
output signal is unpredictable due to an undefined phase relation between reference frequency (fr) and comparison frequency (fp) and may in the worst case take longer time for lock up of the loop.
To prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector
during power up, thus keeping the loop locked.
During the power saving mode, the corresponding section except for indispensable circuit for the power saving
function stops working, then current consumption is reduced to 10 µA (max.) .
Note : • While the power saving mode is executed, ZC pin should be set at “H” or open. If ZC is set at “L”
during power saving mode, approximately 10 µA current flows.
• PS pin must be set “L” at Power-ON.
• The power saving mode can be released (PS : L → H) 1 µs later after power supply remains stable.
• During the power saving mode, it is possible to input the serial data.
OFF
VCC
ON
tV ≥ 1 µs
Clock
Data
LE
tPS ≥ 100 ns
PS
(1)
(2)
(3)
(1) PS = L (power saving mode) at Power ON
(2) Set serial data 1 µs later after power supply remains stable (VCC ≥ 2.2 V) .
(3) Release power saving mode (PS : L → H) 100 ns later after setting serial data.
10
MB15E06
Table.8 PS Pin Setting
PS pin
Status
H
Normal mode
L
Power saving mode
Table.9 ZC Pin Setting
ZC pin
Do output
H
Normal output
L
High impedance
11
MB15E06
■ SERIAL DATA INPUT TIMING
t 0 ≥ 100 ns , t 1 , t 2 , t 4 ≥ 20 ns , t 3 , t 5 ≥ 3 0 n s , t 6 ≥ 1 0 0 n s
C:Control bit
(LSB)
( M SB)
Clock
t0
LE
t1
t2
t5
t3
t6
t4
On rising edge of the clock, one bit of the data is transferred into the shift register.
12
MB15E06
■ PHASE COMPARATOR OUTPUT WAVEFORM
fr
fp
t WU
t WL
LD
[FC = " H"]
φP
φR
H
DO
Z
L
[FC = "L"]
φP
φR
H
DO
Z
L
Note : 1. Phase error detection range : −2π to +2π
2. Pulses on Do output signal during locked state are output to prevent dead zone.
3. LD output becomes low when phase is tWU or more. LD output becomes high when phase error is tWL
or less and continues to be so for three cysles or more.
4. tWU and tWL depend on OSCin input frequency.
tWU ≥ 8/fosc (e. g. tWU ≥ 625ns, foscin = 12.8 MHz)
tWL ≤ 16/fosc (e. g. tWL ≤ 1250ns, foscin = 12.8 MHz)
5. LD becomes high during the power saving mode (PS = “L”.)
13
MB15E06
■ TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCin)
VCC = VP = 3 V
1000 pF
0.1 µF
0.1 µF
1000 pF
1000 pF
S•G
S•G
50 Ω
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
VCC
Controller (setting divide ratio)
50 Ω
→
Oscilloscope
Note : SSOP
14
MB15E06
■ TYPICAL CHARACTERISTICS
1. fin Input Sensitivity
Vfin vs. fin
+10
Ta = +25 °C
,,,,,,,,,,,,,,
,,,,,,,,,,,,,,
,,,,,,,,,,,,,,
0
V fin (dBm)
SPEC
−10
−20
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
−30
−40
0
1000
2000
3000
4000
fin (MHz)
2. OSCin Input Sensitivity
,,,,,,,,
,,,,,,,,
Vfosc vs. fosc
+10
Ta = +25 °C
SPEC
Vfosc (dBm)
0
−10
−20
−30
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
−40
0
50
100
fosc (MHz)
15
MB15E06
3. Do Output Current
VOH vs. IOH
Ta = +25 °C
VCC = 3 V
VP = 5 V
5.0
VOH (V)
4.0
VP = 3 V
3.0
2.0
1.0
0
0
−5
−10
−15
−20
IOH (mA)
VOL vs. IOL
VP = 5 V
Ta = +25 °C
VCC = 3 V
5.0
VP = 3 V
VOL (V)
4.0
3.0
2.0
1.0
0
0
5
10
IOL (mA)
16
15
20
MB15E06
4. fin Input Impedance
1; 10.188 Ω
−36.666 Ω
1 GHz
4
2; 10.731 Ω
1.4438 Ω
1.5 GHz
3
3; 16.474 Ω
31.454 Ω
2 GHz
2
4; 29.314 Ω
50.516 Ω
2.5 GHz
1
5. OSCin Input Impedance
3
1
2
4
1;
3.516 kΩ
−43.99 kΩ
1 MHz
2;
150.5 Ω
−4.8388 kΩ
10 MHz
3;
30.13 Ω
−2.389 kΩ
20 MHz
4; 12.844 Ω
−948.37 Ω
50 MHz
17
MB15E06
■ REFERENCE INFORMATION
Typical plots measured with the
test circuit are shown below.
Each plot shows lock up time,
phase noise and reference
leakage.
•
•
•
•
•
Test Circuit
S.G
OSCin
Do
fvco = 1835 MHz
Kv = 87 MHz/v
fr = 200 kHz
fosc = 13 MHz
LPF :
LPF
fin
15 kΩ
910 Ω
Spectrum
Analyzer
VCO
3000 pF
PLL Lock Up Time = 500 µs
(1797.6 MHz → 1872.4 MHz, within ± 1kHz)
400 pF
PLL Phase Noise
@ within loop band = 69.4 dBc/H
REF
∆MKr x : 500.01844 µs
y : −74.8009 MHz
0.03 µF
0.0 dBm
ATT 10 dB
10 dB/
38.00500
MHz
RBW
300 Hz
2.000
kHz/div
VBW
300 Hz
29.99500
MHz
SPAN 50.0 kHz CENTER 1.8350000 GHz
10.1339 µs
1.9903829 ms
PLL Reference Leakage
@ 200 kHz offset = 74.6 dBc
∆MKr x : 500.01844 µs
y : −74.8009 MHz
REF
250.0000
MHz
0.0 dBm
ATT 10 dB
10 dB/
50.00000
MHz/div
RBW
10 kHz
0
Hz
10.1339 µs
1.9903829 ms
VBW
10 kHz
SPAN 1.00 MHz CENTER
18
1.83500 GHz
MB15E06
■ APPLICATION EXAMPLE
VP
10 kΩ
Output
VCO
LPF
12 kΩ
12 kΩ
10 kΩ
Lock detect.
From
a controller
φR
φP
16
15
LD/fout
ZC
PS
LE
Data
Clock
13
12
11
10
9
MB15E06
1
2
3
4
5
6
7
8
OSCIN
OSCOUT
VP
VCC
DO
GND
Xfin
fin
1000 pF
1000 pF
1000 pF
0.1 µF
0.1 µF
TCXO
Vp : 5.5 V Max
Note : 1. SSOP-16
2. In case of using a crystal resonator, it is necessary to optimize matching between the crystal
and this LSI, and perform detailed system evaluation. It is recommended to consult with a
supplier of the crystal resonator. (Reference oscillator circuit provides its own bias, feedback
resistor is 100 kΩ (typ) .)
19
MB15E06
■ ORDERING INFORMATION
Part number
20
Package
MB15E06PFV1
16-pin Plastic SSOP
(FPT-16P-M05)
MB15E06PV1
16-pad plastic BCC
(LCC-16P-M06)
Remarks
MB15E06
■ PACKAGE DIMENSION
16-pin Plastic SSOP
(FPT-16P-M05)
* : These dimensions do not include resin protrusion.
+0.20
* 5.00±0.10(.197±.004)
1.25 –0.10
+.008
.049 –.004
(Mounting height)
0.10(.004)
INDEX
* 4.40±0.10
(.173±.004)
0.65±0.12
(.0256±.0047)
4.55(.179)REF
C
+0.10
6.40±0.20
(.252±.008)
5.40(.213)
NOM
"A"
+0.05
0.22 –0.05
0.15 –0.02
+.004
–.002
.006 –.001
.009
Details of "A" part
+.002
0.10±0.10(.004±.004)
(STAND OFF)
0
10°
0.50±0.20
(.020±.008)
1994 FUJITSU LIMITED F16013S-2C-4
Dimensions in : mm (inches)
21
MB15E06
16-pad Plastic BCC
(LCC-16P-M06)
4.55±0.10
(.179±.004)
0.80(.031)MAX
Mounting height
14
3.40(.134)TYP
0.65(.026)
TYP
0.40±0.10
(.016±.004)
9
0.325±0.10
(.013±.004)
9
14
0.80(.031)
REF
INDEX AREA
3.40±0.10
(.134±.004)
2.45(.096)
TYP
"A"
1
6
0.075±0.025
(.003±.001)
(Stand off)
6
Details of "A" part
0.75±0.10
(.030±.004)
1.15(.045)
REF
"B"
1.725(.068)
REF
1
Details of "B" part
0.60±0.10
(.024±.004)
0.05(.002)
0.40±0.10
(.016±.004)
C
0.60±0.10
(.024±.004)
1999 FUJITSU LIMITED C16017S-1C-1
Dimensions in : mm (inches)
22
MB15E06
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
Fax: 81(44) 754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
http://www.fmap.com.sg/
F9907
 FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have an inherent chance of failure.
You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for
export of those products from Japan.