FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-21341-2E
ASSP
Dual Serial Input
PLL Frequency Synthesizer
MB15F02
■ DESCRIPTION
The Fujitsu MB15F02 is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2.0 GHz and a 500
MHz prescalers. A 64/65 or a 128/129 for the 1.2 GHz prescaler, and a 16/17 or a 32/33 for 500 MHz prescaler
can be selected that enables pulse swallow operation.
The latest BiCMOS process technology is used, resuItantly a supply current is limited as low as 6.0 mA typ. at a
supply voltage of 3.0 V.
Furthermore, a super charger circuit is included to provide a fast tuning as well as low noise performance. As a
result of this, MB15F02 is ideally suitable for digital mobile communications, such as GSM (Global System for
Mobile Communications).
■ FEATURES
• High frequency operation
•
•
•
•
•
•
•
•
RF synthesizer : 1.2 GHz max.
IF synthesizer
: 500 MHz max.
Low power supply voltage: VCC = 2.7 to 3.6V
Very Low power supply current : ICC = 6.0 mA typ. (VCC = 3 V)
Power saving function : IPS1 = IPS2 = 0.1 µA typ.
Serial input 14–bit programmable reference divider: R = 5 to 16,383
Serial input 18–bit programmable divider consisting of:
- Binary 7–bit swallow counter: 0 to 127
- Binary 11–bit programmable counter: 5 to 2,047
On–chip high performance charge pump circuit and phase comparator, achieving high–speed lock–up and
low phase noise
Wide operating temperature: Ta = −40 to 85°C
Plastic 16-pin SSOP package (FPT-16P-M05) and 16-pin BCC package (LCC-16P-M03)
■ PACKAGES
16-pin, Plastic SSOP
(FPT-16P-M05)
16-pin, Plastic BCC
(LCC-16P-M03)
MB15F02
■ PIN ASSIGNMENTS
SSOP-16 pin
GNDRF
1
16
Clock
OSCin
2
15
Data
GNDIF
3
14
LE
finIF
4
TOP 13
VIEW
5
12
finRF
LD/fout
6
11
XfinRF
PSIF
7
10
PSRF
DoIF
8
9
DoRF
VccIF
VccRF
(FPT-16P-M05)
BCC-16 pin
GNDRF
OSCin
1
GNDIF
2
finIF
3
VCCIF
4
LD/fout
5
PSIF
6
16
Clock
15
TOP
VIEW
7
DoIF
8
DoRF
(LCC-16P-M03)
2
14
Data
13
LE
12
finRF
11
VCCRF
10
XfinRF
9
PSRF
MB15F02
■ PIN DESCRIPTIONS
Pin No.
SSOP
BCC
Pin
name
1
16
GNDRF
–
Ground for RF–PLL section.
2
1
OSCin
I
The programmable reference divider input. TCXO should be connected
with a coupling capacitor.
3
2
GNDIF
–
Ground for the IF-PLL section.
4
3
finIF
I
Prescaler input pin for the IF-PLL.
The connection with VCO should be AC coupling.
5
4
VccIF
–
Power supply voltage input pin for the IF-PLL section.
O
Lock detect signal output (LD) / phase comparator monitoring output
(fout)
The output signal is selected by a LDS bit in a serial data.
LDS bit = ”H” ; outputs fout signal
LDS bit = ”L” ; outputs LD signal
6
5
LD/fout
I/O
Descriptions
7
6
PSIF
I
Power saving mode control for the IF-PLL section. This pin must be set
at ”L” Power-ON. (Open is prohibited.)
PSIF = ”H” ; Normal mode
PSIF = ”L” ; Power saving mode
8
7
DoIF
O
Charge pump output for the IF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
9
8
DoRF
O
Charge pump output for the RF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
10
9
PSRF
I
Power saving mode control for the RF-PLL section. This pin must be set
at ”L” Power-ON. (Open is prohibited.)
PSRF = ”H” ; Normal mode
PSRF = ”L” ; Power saving mode
11
10
XfinRF
I
Prescaler complimentary input for the RF-PLL section.
This pin should be grounded via a capacitor.
12
11
VccRF
–
Power supply voltage input pin for the RF-PLL section, the shift register
and the oscillator input buffer.
13
12
finRF
I
Prescaler input pin for the RF-PLL.
The connection with VCO should be AC coupling.
I
Load enable signal input (with the schmitt trigger circuit.)
When LE is ”H”, data in the shift register is transferred to the
corresponding
latch according to the control bit in a serial data.
14
13
LE
15
14
Data
I
Serial data input (with the schmitt trigger circuit.)
A data is transferred to the corresponding latch (IF-ref counter, IF-Prog.
counter, RF-ref. counter, RF-prog. counter) according to the control bit
in a serial data.
16
15
Clock
I
Clock input for the 23-bit shift register (with the schmitt trigger circuit.)
One bit data is shifted into the shift register on a riging edge of the
clock.
3
MB15F02
■ BLOCK DIAGRAM
VccIF
GNDIF
3
5
7
PSIF
3-bit latch
Intermittent
mode
control
LDS SWIF FCIF
(IF–PLL)
7-bit latch
11-bit latch
Binary 11-bit
Binary 7-bit
swallow counter programmable
(IF–PLL)
counter(IF–PLL)
fpIF
Phase
comp.
Charge Super
pump charger
(IF–PLL)
(IF–PLL)
8 DoIF
Prescaler
finIF 4
(IF–PLL)
16/17,32/33
2-bit latch
T1
T2
Lock
Det.
14-bit latch
Binary 14–bit programmable ref.
counter(IF–PLL)
(IF–PLL)
LDIF
frIF
2
OSCin
AND
OR
frRF
T1
T2
Binary 14-bit programmable ref.
counter(RF–PLL)
LDRF
2-bit latch
finRF 13
11
XfinRF
6 LD/fout
(RF–PLL)
(RF–PLL)
64/65,
128/129
Intermittent
mode
control
LE 14
Schmitt
circuit
Data 15
Schmitt
circuit
Clock 16
Schmitt
circuit
Binary 7-bit
swallow counter
(RF–PLL)
Binary 11-bit
programmable
counter(RF–PLL)
3-bit latch
7-bit latch
(RF–PLL)
11-bit latch
Latch selector
C
N
1
C
N
2
23-bit shift
register
12
VCCRF
Note: SSOP-16 pin
Phase
comp.
fpRF
(RF–PLL)
4
LD
frIF
frRF
fpIF
fpRF
Lock
Det.
Prescaler
LDS SWRF FCRF
PSRF 10
14-bit latch
Selector
1
GNDRF
Charge Super
pump
(RF–PLL) charger
9 DoRF
MB15F02
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
VCC
–0.5 to +4.0
V
Input voltage
VI
–0.5 to VCC +0.5
V
Output voltage
VO
–0.5 to VCC +0.5
V
TSTG
–55 to +125
°C
Power supply voltage
Storage temperature
Remark
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Unit
Min.
Typ.
Max.
VCC
2.7
3.0
3.6
V
Input voltage
Vi
GND
–
VCC
V
Operating temperature
Ta
–40
–
+85
°C
Power supply voltage
Note
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All
the device’s electrical characteristics are warranted when operated within these ranges.
Always yse semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with repect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
5
MB15F02
■ ELECTRICAL CHARACTERISTICS
Parameter
Symbol
ICCIF*1
Power supply current
ICCRF*2
Power saving current
finIF
Operating
frequency
Input sensitivity
Input voltage
Input current
finRF
2.5
–
–
3.5
–
mA
IpsIF
VccIF current at PSIF =”L”
–
0.1*3
10
IpsRF
VccRF current at PSIF/RF =”L”
–
*3
0.1
10
finIF*4
IF–PLL
50
–
500
RF–PLL
100
–
1200
3
–
40
–10
–
+2
dBm
–10
–
+2
dBm
–
–
VCC
Vp-p
RF*4
µA
MHz
finIF
VfinIF
finRF
VfinRF
OSCin
VOSC
Data,
Clock,
LE
VIH
Schmitt trigger input
0.5
VCC×0.7+0.4
VIL
Schmitt trigger input
–
–
VCC×0.3–0.4
V
PSIF,
PSRF
VIH
VIL
VCC×0.7
–
–
–
VCC×0.3
V
Data,
Clock,
LE,
PSIF,
PSRF
IIH*5
–1.0
IIL*5
–1.0
–
+1.0
IIH
0
–
+100
IIL*5
VOH
–100
–
0
VCC–0.4
–
VCC–0.4
–
–
–
–
–
–
–
1.1
Output voltage
VOL
DoIF,
DoRF
VDOH
VDOL
DoIF,
DoRF
IOFF
LD/fout
IOH*5
IOL
Output current
DoIF,
DoRF
6
–
fin
fOSC
LD/fout
*1:
*2:
*3:
*4:
*5:
finIF = 500 MHz,
fosc = 12 MHz
finRF = 1200 MHz,
fosc = 12 MHz
OSCin
OSCin
High impedance
cutoff current
Condition
(VCC = 2.7 to 3.6 V, Ta = –40 to +85°C)
Value
Unit
Min.
Typ.
Max.
IDOH*5
IDOL
IF–PLL, 50 Ω load system
(Refer to the TEST CIRCUIT)
RF–PLL, 50 Ω load system
(Refer to the TEST CIRCUIT)
Vcc = 3.0 V, IOH = –1 mA
Vcc = 3.0 V, IOL = 1 mA
Vcc = 3.0 V, IOH = –1 mA
Vcc = 3.0 V, IOL = 1 mA
Vcc = 3.0 V
VOFF = GND to Vcc
Vcc = 3.0 V
Vcc = 3.0 V
Vcc = 3.0 V,
VDOH = 2.0 V, Ta = 25°C
Vcc = 3.0 V,
VDOL = 1.0 V, Ta = 25°C
+1.0
0.4
0.4
–
–
–1.0
1.0
–
–
–11
–
–6
8
–
15
µA
µA
V
V
µA
mA
mA
Conditions ; VccIF = 3.0 V, Ta = 25°C, in locking state.
Conditions; VccRF = 3.0 V, Ta = 25°C, in locking state.
Conditions ; Vcc = 3.0 V, fosc = 12.8 MHz (–2 dB), Ta = 25°C
AC coupling. The minimum frequency is specified with a connecting coupling capacitor of 1000 pF.
The symbol “–” means direction of current flow.
MB15F02
■ FUNCTIONAL DESCRIPTIONS
The divide ratio can be calculated using the following equation:
fVCO = {(M x N) + A} x fOSC ÷ R
fVCO:
M:
N:
A:
fOSC:
R:
(A < N)
Output frequency of external voltage controlled ocillator (VCO)
Preset divide ratio of dual modulus prescaler (16 or 32 for IF-PLL, 64 or 128 for RF-PLL)
Preset divide ratio of binary 11-bit programmable counter (5 to 2,047)
Preset divide ratio of binary 7-bit swallow counter (0≤ A ≤ 127)
Reference oscillation frequency
Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383)
Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF–PLL
sections, programmable reference dividers of IF/RF PLL sections are controlled individually.
Serial data of binary data is entered through Data pin.
On rising edge of clock, one bit of serial data is transferred into the shift register. When load enable signal is high,
the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting.
Table1. Control Bit
Control bit
Destination of serial data
CN1
CN2
L
L
The programmable reference counter for the IF-PLL.
H
L
The programmable reference counter for the RF-PLL.
L
H
The programmable counter and the swallow counter for the IF-PLL
H
H
The programmable counter and the swallow counter for the RF-PLL
Shift Register Configuration
Programmable Reference Counter
LS
MS
Data
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
C
N
1
C
N
2
T
1
T
2
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
10
R
11
R
12
R
13
R
14
CNT1, 2
: Control bit
R1 to R14 : Divide ratio setting bits for the programmable reference counter (5 to 16,383)
T1, 2
: Test purpose bit
NOTE: Start data input with MSB first.
[Table. 1]
[Table. 2]
[Table. 3]
7
MB15F02
Programmable Counter
LS
MS
Data
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
C
N
1
C
N
2
L
D
S
S
W
F
C
A
1
A
2
A
3
A
4
A
5
A
6
A
7
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
10
N
11
CNT1, 2
N1 to N14
A1 to A7
SW
: Control bit
: Divide ratio setting bits for the programmable counter (5 to 2,047)
: Divide ratio setting bits for the swallow counter (0 to 127)
: Divide ratio setting bit for the prescaler
(16/17 or 32/33 for the IF-PLL, 64/65 or 128/129 for the RF-PLL)
FC
: Phase control bit for the phase detector
LDS
: LD/fout signal select bit
NOTE: Start data input with MSB first.
[Table. 1]
[Table. 4]
[Table. 5]
[Table. 6]
[Table. 7]
[Table. 8]
Table2. Binary 14-bit Programmable Reference Counter Data Setting
Divide
ratio
(R)
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
5
0
0
0
0
0
0
0
0
0
0
0
1
0
1
6
0
0
0
0
0
0
0
0
0
0
0
1
1
0
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note: • Divide ratio less than 5 is prohibited.
Table.3 Test Purpose Bit Setting
8
T
1
T
2
LD/fout pin state
L
L
Outputs frIF.
H
L
Outputs frRF.
L
H
Outputs fpIF.
H
H
Outputs fpRF.
MB15F02
Table.4 Binary 11-bit Programmable Counter Data Setting
Divide
ratio
(N)
N
11
N
10
N
9
N
8
N
7
N
6
N
5
N
4
N
3
N
2
N
1
5
0
0
0
0
0
0
0
0
1
0
1
6
0
0
0
0
0
0
0
0
1
1
0
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
2047
1
1
1
1
1
1
1
1
1
1
1
Note: • Divide ratio less than 5 is prohibited.
Table.5 Binary 7-bit Swallow Counter Data Setting
Divide
ratio
(A)
A
7
A
6
A
5
A
4
A
3
A
2
A
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
127
1
1
1
1
1
1
1
Note: • Divide ratio (A) range = 0 to 127
Table. 6 Prescaler Data Setting
Prescaler
divide ratio
SW = ”H”
SW = ”L”
IF-PLL
16/17
32/33
RF-PLL
64/65
128/129
9
MB15F02
Table. 7 Phase Comparator Phase Switching Data Setting
FCIF/RF = H
FCIF/RF = L
DoIF/RF
(1)
fr > fp
H
L
fr = fp
Z
Z
fr < fp
L
H
VCO polarity
(1)
(2)
VCO Output
Frequency
Note: • Z = High–impedance
• Depending upon the VCO and LPF polarity,
FC bit should be set.
(2)
VCO Input Voltage
Table. 8 LD/fout Output Select Data Setting
LDS
LD/fout output signal
H
fout (frIF/RF, fpIF/RF) signals
L
LD signal
Serial Data Input Timing
MSB
Data
LSB
Clock
LE
t2
t1
t4
t5
t3
t7
t6
On rising edge of the clock, one bit of the data is transferred into the shift register.
Parameter
10
Min.
Typ.
Max.
Unit
Parameter
Min.
Typ.
Max.
Unit
t1
20
–
–
ns
t5
100
–
–
ns
t2
20
–
–
ns
t6
20
–
–
ns
t3
30
–
–
ns
t7
100
–
–
ns
t4
30
–
–
ns
MB15F02
■ PHASE DETECTOR OUTPUT WAVEFORM
frIF/RF
fpIF/RF
tWU
tWL
LD
(FC bit = High)
DoIF/RF
H
Z
L
(FC bit = Low)
DoIF/RF
Z
LD Output Logic Table
IF–PLL section
RF–PLL section
LD output
Locking state / Power saving state Locking state / Power saving state
H
Locking state / Power saving state Unlocking state
L
Unlocking state
Locking state / Power saving state
L
Unlocking state
Unlocking state
L
Note: • Phase error detection range = −2π to +2π
• Pulses on DoIF/RF signals are output to prevent dead zone.
• LD output becomes low when phase error is tWU or more.
• LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more.
• tWU and tWL depend on OSCin input frequency as follows.
tWU > 8/fosc: i.e. tWU > 625ns when foscin = 12.8 MHz
tWL < 16/fosc: i.e. tWL < 1250ns when foscin = 12.8 MHz
11
MB15F02
■ POWER SAVING MODE (INTERMITTENT MODE CONTROL CIRCUIT)
Setting a PSIF(RF) pin to Low, IF-PLL (RF-PLL) enters into power saving mode resultant current consumption can
be limited to 10µA (typ.). Setting PS pin to High, power saving mode is released so that the device works normally.
In addition, the intermittent operation control circuit is included which helps smooth start up from stand by mode.
In general, the power consumption can be saved by the intermittent operation that powering down or waking up the
synthesizer. Such case, if the PLL is powered up uncontrolled, the resulting phase comparator output signal is
unpredictable due to an undefined phase relation between reference frequency (fr) and comparison frequency (fp)
and may in the worst case take longer time for lock up of the loop.
To prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector
during power up. Thus keeping the loop locked.
Allow 1 µs after frequency stabilization on power-up for exiting the power saving mode (PS: L to H)
Serial data can be entered during the power saving mode.
During the power saving mode, the corresponding section except for indispensable circuit for the power saving
function stops working, then current consumption is reduced to 10µA per one PLL section.
At that time, the Do and LD become the same state as when a loop is locking. That is, the Do becomes high
impedance.
A VCO control voltage is naturally kept at the locking voltage which defined by a LPF’s time constant. As a result
of this, VCO’s frequency is kept at the locking frequency.
Note: PS pin must be set “L” at Power-ON. The power saving mode should be released at 1 µs after the power
supply becomes stable.
PSIF
PSRF
IF-PLL counters
RF-PLL counters
OSC input buffer
L
L
OFF
OFF
OFF
H
L
ON
OFF
ON
L
H
OFF
ON
ON
H
H
ON
ON
ON
ON
V
CC
Clock
Data
LE
PS
i1j
i2j
i3j
(1) PS = L (power saving mode) at Power-ON.
(2) Set serial data after power supply remains stable.
(3) Release saving mode (PS: LfiH) after setting serial data.
12
MB15F02
■ TYPICAL CHARACTERISTICS
Input sensivity of FIN (IF) vs. Input frequency
[Ta = +25°C]
x
+10
Main. counter div. ratio=1032
Swallow=“ON”, RF: Active
fosc=19.8 MHz (–2dB)
Vfin (dBm)
0
SPEC
x
x
–10
x
–20
x
x
x
x
x
x
x
x
VCC=2.7 V
VCC=3.0 V
–30
VCC=3.6 V
–40
0
1000
fin (MHz)
500
2000
1500
Input sensivity of FIN (RF) vs. Input frequency
Main. counter div. ratio=4104
Swallow=“ON”, IF: Active
fosc=19.8 MHz (–2dB)
[Ta = +25°C]
x
+10
0
Vfin (dBm)
SPEC
x
–10
x
x
–20
x
x
x
–30
x
x
x
VCC=2.7 V
VCC=3.0 V
VCC=3.6 V
x
–40
0
1000
2000
3000
fin (MHz)
(Continued)
13
MB15F02
(Continued)
Input sensivity of OSC (IF) vs. Input frequency
Ref. counter div. ratio=2048
RF: fin = 1005 MHz (VCO)
IF: fin = 270 MHz (VCO), Xfin = 1000 PF Pull DOWN
[Ta = +25°C]
x
+10
SPEC
Vosc (dBm)
0
x
–10
–20
x
x
x
x
–30
x
x
x
–40
x
x
VCC=2.7 V
VCC=3.0 V
VCC=3.6 V
–50
–60
0
100
fosc (MHz)
50
200
150
Input sensivity of OSC (RF) vs. Input frequency
Ref. counter div. ratio=2048
RF: fin = 1005 MHz (VCO)
IF: fin = 270 MHz (VCO), Xfin = 1000 PF Pull DOWN
[Ta = +25°C]
x
+10
SPEC
Vosc (dBm)
0
x
–10
–20
x
x
x
x
x
–30
–40
x
x
x
x
x
x
VCC=2.7 V
VCC=3.0 V
VCC=3.6 V
–50
–60
0
14
50
100
fosc (MHz)
150
200
MB15F02
(Continued)
Do output Current (IF)
Conditions: Ta = +25°C
VCC= 2.7, 3.0, 3.6 V
VOH (V)
5.000
3.6 V
.5000
/div
3.0 V
• DO = VCC = 1 V
• OSCin = 12.8 MHz (+10 dB)
• fin [IF/RF] = “H” (= VCC)
VCC = 2.7 V
.0000
.0000
2.500/div
(mA)
–25.00
IOH (mA)
VOL(V)
5.000
.5000
/div
VCC = 2.7 V
3.0 V
3.6 V
• DO = 1 V
• fin [IF] = 500 MHz (–10 dB)
• OSCin, fin [RF] = “H” (= VCC)
.0000
.0000
2.500/div
(mA)
25.00
IOL (mA)
(Continued)
15
MB15F02
(Continued)
Do output Current (RF)
Conditions: Ta = +25°C
VCC= 2.7, 3.0, 3.6 V
VOH (V)
5.000
3.6 V
.5000
/div
3.0 V
VCC = 2.7 V
• DO = VCC = 1 V
• OSCin = 12.8 MHz (+10 dB)
• fin [IF/RF] = “H” (= VCC)
.0000
.0000
2.500/div
(mA)
–25.00
IOH (mA)
VOL(V)
5.000
.5000
/div
VCC = 2.7 V
3.0 V
3.6 V
• DO = 1 V
• fin [RF] = 1.2 GHz (–10 dB)
• OSCin, fin [IF] = “H” (= VCC)
.0000
.0000
2.500/div
IOL (mA)
16
(mA)
25.00
MB15F02
(Continued)
Input Impedance
3: 26.805 Ω
–178.48 Ω 2.2294 pF
400.000 000 MHz
finIF Pin
1
3
1:
778.28 Ω
–824.12 Ω
50 MHz
2:
87.25 Ω
–357.03 Ω
200 MHz
4:
19.305 Ω
–138.94 Ω
500 MHz
2
4
4: 11.686 Ω
–40.426 Ω 3.2808 pF
1 200.000 000 MHz
finRF Pin
1:
312.84 Ω
–627.28 Ω
100 MHz
2:
30.344 Ω
–183.38 Ω
400 MHz
3:
12.746 Ω
–81 Ω
800 MHz
1
2
4
3
2: 316.75 Ω
OSCin Pin
–5.9348 kΩ 2.6817 pF
10.000 000 MHz
2
1
3 4
1:
7.401 kΩ
–20.347 kΩ
3 MHz
3:
116.75 Ω
–3.0649 kΩ
20 MHz
4:
083.88 Ω
–1.5473 kΩ
40 MHz
17
MB15F02
■ REFERENCE INFORMATION
Typical plots measured with the
test circuit are shown below.
Each plot shows lock up time,
phase noise and reference
leakage.
Test Circuit
S.G
OSCin
Do
fin
LPF
•
•
•
•
•
fvco = 1018 MHz
Kv = 20 MHz/v
fr = 200 kHz
fosc = 13 MHz
LPF:
15 kΩ
2.2 kΩ
Spectrum
Analyzer
VCO
2000 pF
PLL Lock Up Time = 440 µs
(1005.000 MHz → 1031.000 MHz, within ± 1kHz)
∆ MKr x : 439.90929 µs
y : 25.99986 MHz
A evts N/A
330 pF
20000 pF
PLL Phase Noise
@ within loop band = 75.5 dBc/Hz
REF –10.0 dBm
10dB/
ATT 10 dB
30.00300
MHz
RBW
300 Hz
SAMPLE
VBW
300 Hz
1.000
kHz/div
29.99800
MHz
SPAN 50.0 kHz CENTER 1.0180000 GH z
10.2449 µs
1.9902449 ms
PLL Lock Up Time = 440 µs
(1031.000 MHz → 1005.000 MHz, within ± 1kHz)
∆ MKr x : 440.02236 µs
y : –26.00006 MHz
PLL Reference Leakage
@ 200 kHz offset = 71.4 dBc
REF
–10.0 dBm ATT 10 dB
10dB/
30.00300
MHz
RBW
10 kHz
SAMPLE
VBW
10 kHz
1.00
kHz/div
29.99800
MHz
10.1378 µs
18
1.9901378 ms
SPAN 1.00 MHz CENTER 1.01800 GHz
MB15F02
■ TEST CIRCUIT (PRESCALER INPUT/PROGRAMMABLE REFERENCE DIVIDER INPUT SENSITIVITY TEST)
fout
Oscilloscope
VccIF
1000pF
0.1µF
P.G
50Ω
1000pF
GND
P.G
8
7
6
5
3
4
2
1
15
16
50Ω
MB15F02
9
10
11
12
13
14
P.G
1000pF
Controller (divide
ratio setting)
50Ω
VccRF
1000pF
0.1µF
Note: SSOP-16 pin
19
MB15F02
■ APPLICATION EXAMPLE
OUTPUT
LPF
VCO
3V
from controller
0.1µF
1000 pF
1000 pF
Clock Data
16
15
LE
finRF
VccRF
XfinRF
PSRF
DoRF
14
13
12
11
10
9
6
7
8
PSIF
DoIF
MB15F02
1
2
3
GNDRF OSCIN GNDIF
4
5
finIF
VccIF
LD/fout
3V
1000 pF
Lock Det.
1000 pF
0.1µF
TCXO
OUTPUT
VCO
LPF
Clock, Data, LE: Schmitt trigger circuit is provided (insert a pull-down or pull-up resistor to prevent oscillation
when open-circuited in the input).
Note: SSOP-16 pin
20
MB15F02
■ ORDERING INFORMATION
Part number
Package
MB15F02 PFV
16 pin, Plastic SSOP
(FPT-16P-M05)
MB15F02 PV
16 pin, Plastic BCC
(LCC-16P-M03)
Remarks
21
MB15F02
■ PACKAGE DIMENSIONS
* : These dimensions do not include resin protrusion.
16 pins, Plastic SSOP
(FPT-16P-M05)
+0.20
* 5.00±0.10(.197±.004)
1.25 –0.10
+.008
.049 –.004
0.10(.004)
INDEX
*4.40±0.10
(.173±.004)
0.65±0.12
(.0256±.0047)
4.55(.179)REF
C
1994 FUJITSU LIMITED F16013S-2C-4
+0.10
0.22 –0.05
+.004
.009 –.002
6.40±0.20
(.252±.008)
5.40(.213)
NOM
"A"
+0.05
0.15 –0.02
+.002
.006 –.001
Details of "A" part
0.10±0.10(.004±.004)
(STAND OFF)
0
10°
0.50±0.20
(.020±.008)
Dimensions in mm (inches)
(Continued)
22
MB15F02
16-pin, Plastic BCC
(LCC-16P-M03)
4.55±0.10
(.179±.004)
14
3.40(.134)TYP
0.80(.032)MAX
9
(Mounting height)
0.65(.026)TYP
9
14
0.40±0.10
(.016±.004)
3.25(.128)
TYP
4.20±0.10
(.165±.004)
45˚
"A"
1.55(.061)TYP
"B"
0.80(.032)
TYP
1
E-MARK
6
0.40(.016)
0.325±0.10
(.013±.004)
6
0.085±0.040
(.003±.002)
(STAND OFF)
Details of "A" part
1.725(.068)
TYP
1
Details of "B" part
0.75±0.10
(.030±.004)
0.60±0.10
(.024±.004)
0.05(.002)
0.40±0.10
(.016±.004)
C
1996 FUJITSU LIMITED C16014S-1C-1
0.60±0.10
(.024±.004)
Dimensions in mm (inches)
23
MB15F02
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-88, Japan
Tel: (044) 754-3753
Fax: (044) 754-3329
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
Fax: (408) 432-9044/9045
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281 0770
Fax: (65) 281 0220
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document presented
as examples of semiconductor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the
use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.
F9704
FUJITSU LIMITED
24
Printed in Japan