FUJITSU MB15F72SPPV

FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-21363-2E
ASSP
Dual Serial Input
PLL Frequency Synthesizer
MB15F72SP
■ DESCRIPTION
The Fujitsu MB15F72SP is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1300 MHz and a
350 MHz prescalers. A 64/65 or a 128/129 for the 1300 MHz prescaler, and a 8/9 or a 16/17 for the 350 MHz prescaler can be selected for the prescaler that enables pulse swallow operation.
MB15F72SP has the same configuration with MB15F02 or MB15F02L. The BiCMOS process is used , as a result
a supply current is typically 2.7 mA typ. at 2.7 V.The supply voltage range is from 2.4 V to 3.6 V. A refined charge
pump supplies well-balanced output current with 1.5 mA and 6 mA selectable by serial data.
The new package(BCC20) decreases a area of MB15F72SP more than 30 % comparing with the former BCC16
(for dual PLL).
MB15F72SP is ideally suited for wireless mobile communications, such as PDC
■ FEATURES
• High frequency operation:RF synthesizer: 1300 MHz max
:IF synthesizer: 350 MHz max
• Low power supply voltage: VCC = 2.4 to 3.6 V
• Ultra Low power supply current:ICC = 2.7 mA typ. (VCC = Vp = 2.7 V, SWIF = SWRF = 0,
Ta = +25°C, in IF, RF locking state)
• Direct power saving function:Power supply current in power saving mode
Typ. 0.1 µA (VCC = Vp = 2.7 V, Ta = +25°C)
Max. 10 µA (VCC = Vp = 2.7 V)
(Continued)
■ PACKAGES
20-pin plastic TSSOP
(FPT-20P-M06)
20-pad plastic BCC
(LCC-20P-M04)
MB15F72SP
(Continued)
• Software selectable charge pump current: 1.5 mA/6.0 mA (typ.)
• Dual modulus prescaler: 1300 MHz prescaler (64/65 or 128/129 )/350 MHz prescaler (8/9 or 16/17)
• 23 bit shift resister
• Serial input 14-bit programmable reference divider: R = 3 to 16,383
• Serial input programmable divider consisting of:
- Binary 7-bit swallow counter: 0 to 127
- Binary 11-bit programmable counter: 3 to 2,047
• On–chip phase control for phase comparator
• Built-in digital locking detector circuit to detect PLL locking and unlocking.
• Operating temperature: Ta = –40°C to +85°C
• Sireal data format compatible with MB15F02SL
• Small package BCC20 (3.4 mm × 3.6mm × 0.8mm)
■ PIN ASSIGNMENTS
(TSSOP-20)
(BCC-20)
TOP VIEW
TOP VIEW
OSCIN
1
20
Clock
GND
2
19
Data
finIF
3
18
LE
XfinIF
4
17
finRF
GNDIF
5
16
XfinRF
VCCIF
6
15
GNDRF
PSIF
7
14
VpIF
8
13
DoIF
9
12
VpRF
LD/fout
10
11
DoRF
finIF
1
XfinIF
2
GNDIF
VCCIF
3
4
VCCRF
PSIF
5
PSRF
VpIF
6
(FPT-20P-M06)
2
OSCIN Data
GND
Clock
20 19 18 17
7
8
9 10
16
LE
15
14
finRF
13
12
GNDRF
11
PSRF
DoIF
DoRF
LD/fout VpRF
(LCC-20P-M04)
XfinRF
VCCRF
MB15F72SP
■ PIN DESCRIPTION
Pin no.
TSSOP BCC
Pin name I/O
Descriptions
The programmable reference divider input. TCXO should be connected with a
AC coupling capacitor.
1
19
OSCIN
2
20
GND
3
1
finIF
I
Prescaler input pin for the IF-PLL.
Connection to an external VCO should be via AC coupling.
4
2
XfinIF
I
Prescaler complimentary input pin for the IF-PLL section.
This pin should be grounded via a capacitor.
5
3
GNDIF
6
4
VCCIF
7
5
PSIF
8
6
VpIF
 Power supply voltage input pin for the IF-PLL charge pump.
9
7
DOIF
O
Charge pump output for the IF-PLL section.
Phase characteristics of the phase detector can be reversed by FCbit.
10
8
LD/fout
O
Lock detect signal output (LD)/phase comparator monitoring
output (fout).The output signal is selected by LDS bit in the serial data.
LDS bit = “H” ; outputs fout signal / LDS bit = “L” ; outputs LD signal
11
9
DORF
O
Charge pump output for the RF-PLL section.
Phase characterstics of the phase detector can be reversed by FCbitt.
12
10
VpRF
 Power supply voltage input pin for the RF-PLL charge pump.
13
11
PSRF
I
Power saving mode control for the RF-PLL section. This pin must be set at “L”
Power-ON. (Open is prohibited.)
PSRF = “H” ; Normal mode / PSRF = “L” ; Power saving mode
14
12
VCCRF

Power supply voltage input pin for the RF-PLL section (except for the charge
pump circuit).
15
13
GNDRF
16
14
XfinRF
I
Prescaler complimentary input pin for the RF-PLL section.
This pin should be grounded via a capacitor.
17
15
finRF
I
Prescaler input pin for the RF-PLL.
Connection to an external VCO should be via AC coupling.
18
16
LE
I
Load enable signal input(with the schmitt trigger circuit).
When LE is set “H”, data in the shift register is transferred to the
corresponding latch according to the control bit in a serial data.
19
17
Data
I
Serial data input(with the schmitt trigger circuit).
A data is transferred to the corresponding latch(IF-ref. counter, IF-prog. counter,
RF-ref. counter, RF-prog. counter) according to the control bit in a serial data.
20
18
Clock
I
Clock input for the 23-bit shift register (with the schmitt trigger circuit).
One bit of data is shifted into the shift register on a rising edge of the clock.
I
 Ground for OSC input buffer and the shift register circuit.
 Ground for the IF-PLL section.
Power supply voltage input pin for the IF-PLL section(except for the charge
 pump circuit), the OSC input buffer and the shift register circuit.
When power is OFF, latched data of IF-PLL is lost.
I
Power saving mode control for the IF-PLL section. This pin must be set at “L”
Power-ON. (Open is prohibited.)
PSIF = “H” ; Normal mode / PSIF = “L” ; Power saving mode
 Ground for the RF-PLL section.
3
MB15F72SP
■ BLOCK DIAGRAM
VCCIF
(4) 6
PSIF 7
(5)
finIF 3
(1)
XfinIF 4
(2)
Intermittent
mode control
(IF-PLL)
3 bit latch
7 bit latch
LDS SWIF FCIF
Binary 7-bit
Binary 11-bit proswallow counter
grammable
(IF-PLL)
counter(IF-PLL)
VpIF
8 (6)
GNDIF
5 (3)
11 bit latch
fpIF
Charge Current
pump Switch
(IF-PLL)
Phase
comp.
(IF-PLL)
Prescaler
(IF-PLL)
(8/9, 16/17
9 DoIF
(7)
Lock Det.
(IF-PLL)
2 bit latch
T1
T2
14 bit latch
1 bit latch
Binary 14-bit programmable ref.
counter(IF-PLL)
LDIF
C/P setting
counter
frIF
OSCIN 1
(19)
T1
T2
OR
2 bit latch
( 15 )
finRF 17
XfinRF 16
( 14 )
PSRF 13
(11)
LE 18
( 16 )
( 17 )
Data 19
Clock 20
( 18 )
Binary 14-bit programmable ref.
counter(RF-PLL))
C/P setting
counter
14 bit latch
1 bit latch
LDS SWRF FCRF
Intermittent
mode control
(RF-PLL)
Schmitt
circuit
O : TSSOP
( ) : BCC
Phase
comp.
(RF-PLL)
Binary 11-bit proBinary 7-bit
swallow counter grammable
counter (RF-PLL)
(RF-PLL)
Charge Current
pump
Switch
(RF-PLL)
fpRF
3 bit latch
Schmitt
circuit
10 LD/
( 8 ) fout
Lock Det.
(RF-PLL)
7 bit latch
11 bit latch
Latch selector
C C
N N
1 2
23-bit shift register
2 ( 20 )
GND
4
LD
frIF
frRF
fpIF
fpRF
Prescaler
(RF-PLL)
(64/65, 128/129)
Schmitt
circuit
Selector
AND
frRF
( 12 ) 14
VCCRF
15 ( 13 )
GNDRF
12 ( 10 )
VpRF
11 DoRF
(9)
MB15F72SP
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Unit
Min.
Max.
VCC
−0.5
4.0
V
Vp
VCC
4.0
V
VI
−0.5
VCC + 0.5
V
LD/fout
VO
GND
VCC
V
DoIF, DoRF
VDO
GND
Vp
V
Tstg
−55
+125
°C
Power supply voltage
Input voltage
Output voltage
Rating
Storage temperature
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Unit
Remark
3.6
V
VCCRF = VCCIF
2.7
3.6
V
GND

VCC
V
−40

+85
°C
Min.
Typ.
Max.
VCC
2.4
2.7
Vp
VCC
Input voltage
VI
Operating temperature
Ta
Power supply voltage
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
5
MB15F72SP
■ ELECTRICAL CHARACTERISTICS
(VCC = 2.4 V to 3.6 V, Ta = −40 °C to +85 °C)
Symbol
Parameter
Power supply current
“H” level input voltage
“L” level input voltage
“H” level input voltage
“L” level input voltage
“H” level input current
“L” level input current
“H” level input current
“L” level input current
Unit
Min.
Typ.
Max.
ICCIF *1 IF PLL

1.1

mA
ICCRF *2 RF PLL

1.6

mA
*8
10
µA
PSIF = PSRF = “L”

0.1
IPSRF
PSIF = PSRF = “L”

0.1 *8
10
µA
fin
finIF
IF PLL
50

350
MHz
finRF *3
finRF
RF PLL
100

1300
MHz
OSCIN
fOSC
3

40
MHz
IF *3
Input sensitivity
Value
IPSIF
Power saving current
Operating frequency
Condition

finIF
PfinIF IF PLL, 50 Ω system
−15

+2
dBm
finRF
PfinRF RF PLL, 50 Ω system
−15

+2
dBm
OSCIN
VOSC
0.5

VCC
VP − P
Data,
LE,
Clock
VIH
Schmitt trigger input
0.7 VCC + 0.4


V
VIL
Schmitt trigger input


0.3 VCC − 0.4
V
PSIF,
PSRF
VIH

0.7 VCC


V
VIL



0.3 VCC
V
IIH *4

−1.0

+1.0
µA
IIL *4

−1.0

+1.0
µA
IIH

0

+100
µA
IIL *4

−100

0
µA
VCC − 0.4


V


0.4
V
Data,
LE,
Clock,
PSIF,
PSRF
OSCIN

VOH
VCC = Vp = 2.7 V,
IOH = −1 mA
“L” level output voltage
VOL
VCC = Vp = 2.7 V, IOL = 1 mA
“H” level output voltage
VDOH
VCC = Vp = 2.7 V,
IDOH = −0.5 mA
Vp − 0.4


V
VDOL
VCC = Vp = 2.7 V,
IDOL = 0.5 mA


0.4
V
IOFF
VCC = Vp = 2.7 V
VOFF = 0.5 V to Vp − 0.5 V


2.5
nA
IOH *4
VCC = Vp = 2.7 V


−1.0
mA
IOL
VCC = Vp = 2.7 V
1.0


mA
“H” level output voltage
“L” level output voltage
High impedance
cutoff current
“H” level output current
“L” level output current
LD/fout
DoIF,
DoRF
DoIF,
DoRF
LD/fout
(Continued)
6
MB15F72SP
(Continued)
(VCC = 2.4 V to 3.6 V, Ta = −40 °C to +85 °C)
Parameter
Symbol
“H” level output
current
DoIF
DoRF
IDOH *4
“L” level output
current
DoIF
DoRF
IDOL
IDOL/IDOH IDOMT *5
Charge pump
current rate
Value
Condition
Unit
Min.
Typ.
Max.
VCC = Vp = 2.7 V, CS bit = “H”
VDOH = Vp/2,
CS bit = “L”
Ta = +25 °C

−6.0

mA

−1.5

mA
VCC = Vp = 2.7 V, CS bit = “H”
VDOL = Vp/2,
CS bit = “L”
Ta = +25 °C

6.0

mA

1.5

mA
VDO = Vp / 2

3

%
vs. VDO
IDOVD *6
0.5 V ≤ VDO ≤ Vp − 0.5 V

10

%
vs.Ta
IDOTA *7
−40 °C ≤ Ta ≤ +85 °C,
VDO = Vp / 2

10

%
*1 : finIF = 270 MHz, fosc = 12.8 MHz, VCCIF = VpIF = 2.7 V, SWIF = 0, Ta = +25°C, in locking state.
*2 : finRF = 910 MHz, fosc = 12.8 MHz, VCCRF = VpRF = 2.7 V, SWRF = 0, Ta = +25°C, in locking state.
*3 : AC coupling. 1000pF capacitor is connected under the condition of min. operating frequency.
*4 : The symbol “–” (minus) means direction of current flow.
*5 : VCC = Vp = 2.7 V, Ta = +25°C
(||I3| – |I4||)/[(|I3| + |I4|)/2] × 100(%)
*6 : VCC = Vp = 2.7 V, Ta = +25°C (Applied to each IDOL, IDOH)
[(||I2| – |I1||)/2]/[(|I1| + |I2|)/2] × 100(%)
*7 : VCC = Vp = 2.7 V, Ta = +25°C (Applied to each IDOL, IDOH)
[||IDO(+85°C)| –|IDO(–40°C)||/2]/[|IDO(+85°C)| + |IDO(–40°C)|/2] × 100(%)
*8 : fosc = 12.8 MHz, VCCRF = VpRF = VCCIF = 2.7 V, Ta = +25°C
I1
I3
I2
IDOL
I4
IDOH
I1
0.5
Vp/2
Vp − 0.5
Vp
Charge pump output voltage (V)
7
MB15F72SP
■ FUNCTIONAL DESCRIPTION
1. Pulse swallow function :
fVCO = [(P × N) + A] × fOSC ÷ R
fVCO : Output frequency of external voltage controlled oscillator (VCO)
P : Preset divide ratio of dual modulus prescaler (8 or 16 for IF-PLL, 64 or 128 for RF-PLL)
N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
A : Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127, A < N)
fOSC : Reference oscillation frequency (OSCIN input frequency)
R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
2. Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-PLL sections, and programmable reference dividers of IF/RF-PLL sections are controlled individually.
Serial data of binary data is entered through Data pin.
On a rising edge of Clock, one bit of serial data is transferred into the shift register. On a rising edge of load enable
signal, the data stored in the shift register is transferred to one of latch of them depending upon the control bit data
setting.
The programmable
reference counter
for the IF-PLL
The programmable
reference counter
for the RF-PLL
The programmable
counter and the swallow
counter for the IF-PLL
The programmable
counter and the swallow
counter for the RF-PLL
CN1
0
1
0
1
CN2
0
0
1
1
(1) Shift Register Configuration
• Programmable Reference Counter
Data Flow
(LSB)
1
2
3
4
5
6
7
8
9 10 11 12 13 14
(MSB)
15
16
17
18 19 20 21 22 23
CN1 CN2 T1 T2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 CS X
CS
R1 to R14
T1, T2
CN1, CN2
X
X
: Charge pump currnet select bit
: Divide ratio setting bits for the programmable reference counter (3 to 16,383)
: Test purpose bit
: Control bit
: Dummy bits (Set “0” or “1”)
Note : Data input with MSB first.
8
X
X
MB15F72SP
• Programmable Counter
(LSB)
1
2
3
4
CN1 CN2 LDS
(MSB)
Data Flow
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
23
SWIF/ FCIF/
A1 A2 A3 A4 A5 A6 A7 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11
SWRF FCRF
A1 to A7
N1 to N11
LDS
SWIF/SWRF
FCIF/FCRF
CN1, CN2
: Divide ratio setting bits for the swallow counter (0 to 127)
: Divide ratio setting bits for the programmable counter (3 to 2,047)
: LD/fout signal select bit
: Divide ratio setting bit for the prescaler (IF : SWIF,RF : SWRF)
: Phase control bit for the phase detector (IF: FCIF, RF: FCRF)
: Control bit
Note: Data input with MSB first.
(2) Data setting
• Binary 14-bit Programmable Reference Counter Data Setting (R1 to R14)
Divide ratio
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
•
•
•
16383
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
1
•
•
•
1
0
•
•
•
1
0
•
•
•
1
Note : Divide ratio less than 3 is prohibited.
• Binary 11-bit Programmable Counter Data Setting (N1 to N11)
Divide ratio
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
3
0
0
0
0
0
0
0
0
0
1
1
4
•
•
•
2047
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
1
•
•
•
1
0
•
•
•
1
0
•
•
•
1
Note : Divide ratio less than 3 is prohibited.
• Binary 7-bit Swallow Counter Data Setting (A1 to A7)
Divide ratio
A7
A6
A5
A4
A3
A2
A1
0
0
0
0
0
0
0
0
1
•
•
•
127
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
1
•
•
•
1
9
MB15F72SP
• Prescaler Data Setting (SW)
SW = “1”
SW = “0”
Prescaler divide ratio IF-PLL
8/9
16/17
Prescaler divide ratio RF-PLL
64/65
128/129
Divide ratio
• Charge Pump Current Setting (CS)
• LD/fout Output Select Data Setting (LDS)
Current value
CS
LD/fout output signal
LDS
±6.0 mA
1
fout signal
1
±1.5 mA
0
LD signal
0
• Test Purpose Bit Setting (T1, T2)
LD/fout pin state
T1
T2
Outputs frIF.
0
0
Outputs frRF.
1
0
Outputs fpIF.
0
1
Outputs fpRF.
1
1
• Phase Comparator Phase Switching Data Setting (FCIF, FCRF)
Phase comparator input
FCIF = “1”
FCRF = “1”
FCIF = “0”
FCRF = “0”
DoIF
DoRF
DoIF
DoRF
fr > fp
H
L
fr < fp
L
H
fr = fp
Z
Z
Z : High-impedance
Depending upon the VCO and LPF polarity, FC bit should be set.
High
(1)
(1) VCO polarity FC = “1”
(2) VCO polarity FC = “0”
VCO Output
Frequency
(2)
LPF Output voltage
Note : Give attention to the polarity for using active type LPF.
10
Max.
MB15F72SP
3. Power Saving Mode (Intermittent Mode Control Circuit)
Status
PSIF/PSRF pins
Normal mode
H
Power saving mode
L
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pins low, the device enters into the power saving mode, reducing the current consumption.
See the Electrical Characteristics chart for the specific value.
The phase detector output, Do, becomes high impedance.
For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table.
Setting the PS pins high, releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is
because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr)
which can cause a major change in the comparator output, resulting in a VCO frequency jump and an increase
in lockup time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error
signal from the phase detector when it returns to normal operation.
Notes •When power (VCC) is first applied, the device must be in standby mode, PSIF = PSRF = Low, for at least 1 µs.
•PS pins must be set at “L” for Power-ON.
OFF
V CC
ON
tV ≥ 1 µs
Clock
Data
LE
tPS ≥ 100 ns
PS IF
PS RF
(1)
(2)
(3)
(1) PS IF = PSRF = “L” (power saving mode) at Power-ON
(2) Set serial data 1 µs later after power supply remains stable (VCC > 2.2 V).
(3) Release power saving mode (PS IF, PSRF : “L” → “H”) 100 ns later after setting serial data.
11
MB15F72SP
4. SERIAL DATA INPUT TIMING
Frequency multiplier setting is performed through a serial interface using the Data pin, Clock pin, and LE pin.
Setting data is read into the shift register at the rise of the clock signal, and transferred to a latch at the rise of
the LE signal. The following diagram shows the data input timing.
2nd data
1st data
Control bit
Data
MSB
Invalid data
LSB
Clock
t1
t2
t3
t6
t7
LE
t4
Max. Unit
Parameter
Min.
Typ.
Parameter
Min.
Typ.
t1
20


ns
t5
100


ns
t2
20


ns
t6
20


ns
t3
30


ns
t7
100


ns
t4
30


ns
Note : LE should be “L” when the data is transferred into the shift register.
12
t5
Max. Unit
MB15F72SP
■ PHASE COMPARATOR OUTPUT WAVEFORM
fr IF / fr RF
fp IF / fp RF
t WU
t WL
LD
(FC bit = “1”)
Do IF / Do RF
H
Z
L
(FC bit = “0”)
H
D o IF / Do RF
Z
L
• LD Output Logic
IF-PLL section
RF-PLL section
LD output
Locking state/Power saving state
Locking state/Power saving state
H
Locking state/Power saving state
Unlocking state
L
Unlocking state
Locking state/Power saving state
L
Unlocking state
Unlocking state
L
Notes:•Phase error detection range = –2π to +2π
•Pulses on DoIF/DoRF signals are output to prevent dead zone during locking state.
•LD output becomes low when phase error is tWU or more.
•LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more.
•tWU and tWL depend on OSCIN input frequency as follows.
tWU > 2/fosc : e.g. tWU > 156.3 ns when fosc = 12.8 MHz
tWU < 4/fosc : e.g. tWL < 312.5 ns when fosc = 12.8 MHz
13
MB15F72SP
■ TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCIN)
fout
Oscilloscope
1000 pF
VCCIF
VpIF
0.1 µF
1000 pF
S.G.
50 Ω
0.1 µF
1000 pF
LD/
fout
DoIF
VpIF
PSIF
VCCIF
GNDIF
XfinIF
finIF
GND
OSCIN
10
9
8
7
6
5
4
3
2
1
11
12
13
14
15
16
17
18
19
20
DoRF
VpRF
PSRF
VCCRF
GNDRF
XfinRF
finRF
LE
Data
Clock
50 Ω
1000 pF
Controller
(divide ratio setting)
1000 pF
VpRF
0.1 µF
VCCRF
0.1 µF
Note : Terminal number shows that of TSSOP-20.
14
50 Ω
S.G.
S.G.
MB15F72SP
■ TYPICAL CHARACTERISTICS
1. fin input sensitivity
RF-PLL input sensitivity - Input frequency
Ta = +25 °C
Input sensitivity PfinRF (dBm)
10
,,,,,,,,,,,,,,
,,,,,,,,,,,,,,
,,,,,,,,,,,,,,
5
0
−5
SPEC
−10
−15
−20
−25
−30
VCC = 2.4 V
−35
VCC = 2.7 V
−40
VCC = 3.0 V
−45
VCC = 3.6 V
−50
0
200
400
600
800
1000
1200
1400
1600
1800
2000
Input frequency finRF (MHz)
IF-PLL input sensitivity - Input frequency
Ta = +25 °C
10
,,,,,,,,,,
,,,,,,,,,,
,,,,,,,,,,
Input sensitivity PfinIF (dBm)
5
0
−5
SPEC
−10
−15
−20
−25
−30
VCC = 2.4 V
−35
VCC = 2.7 V
−40
VCC = 3.0 V
−45
VCC = 3.6 V
−50
0
50
100
150
200
250
300
350
400
450
500
550
600
650
700
Input frequency finIF (MHz)
15
MB15F72SP
2. OSCIN input sensitivity
,,,,
,,,,
Input sensitivity VOSC (dBm)
10
Input sensitivity vs Input frequency
Ta = +25 °C
SPEC
0
−10
−20
−30
VCC = 2.4 V
−40
VCC = 2.7 V
−50
VCC = 3.0 V
VCC = 3.6 V
−60
0
20
40
60
80
100
120
140
Input frequency fOSC (MHz)
16
160
180
200
220
MB15F72SP
3. RF-PLL Do output current
• 1.5 mA mode
Charge pump output current IDO (mA)
IDO - VDO
10.0
Ta = +25 °C
VCC = Vp = 2.7 V
IDOL
0.0
IDOH
−10.0
1.0
0.0
2.0
2.7
Charge pump output voltage VDO (V)
• 6.0 mA mode
Charge pump output current IDO (mA)
IDO - VDO
10.0
Ta = +25 °C
VCC = Vp = 2.7 V
IDOL
0.0
IDOH
−10.0
0.0
1.0
2.0
2.7
Charge pump output voltage VDO (V)
17
MB15F72SP
4. IF-PLL Do output current
IDO − VDO
• 1.5 mA mode
Charge pump output current IDO (mA)
10.0
Ta = +25 °C
VCC = Vp = 2.7 V
IDOL
0.0
IDOH
−10.0
0.0
1.0
2.0
2.7
Charge pump output voltage VDO (V)
• 6.0 mA mode
IDO − VDO
Charge pump output current IDO (mA)
10.0
Ta = +25 °C
VCC = Vp = 2.7 V
IDOL
0.0
IDOH
−10.0
0.0
1.0
2.0
Charge pump output voltage VDO (V)
18
2.7
MB15F72SP
5. fin input impedance
finRF input impedance
VCC = 2.7 V
1 : 266.06 Ω
−661.69 Ω
100 MHz
2 : 21.406 Ω
−146.27 Ω
500 MHz
3 : 11.1 Ω
−62.982 Ω
1 GHz
1
4 : 10.35 Ω
−38.861 Ω
1.3 GHz
2
4
3
START 100.000 000 MHz
STOP 1 500.000 000 MHz
finIF input impedance
VCC = 2.7 V
1 : 712.91 Ω
−967.81 Ω
50 MHz
2 : 251.59 Ω
−650.97 Ω
100 MHz
3 : 40.648 Ω
−241.14 Ω
300 MHz
1
2
4
START 50.000 000 MHz
4 : 20.391 Ω
−141.98 Ω
500 MHz
3
STOP 500.000 000 MHz
19
MB15F72SP
6. OSCIN input impedance
OSCIN input impedance
VCC = 2.7 V
1 : 10.693 kΩ
−11.664 kΩ
3 MHz
2 : 1.8725 kΩ
−6.3285 kΩ
10 MHz
3 : 124.25 Ω
−1.6726 kΩ
40 MHz
4
21 4 : 31.188 Ω
3
−664.28 Ω
100 MHz
START 3.000 000 MHz
20
STOP 100.000 000 MHz
MB15F72SP
■ REFERENCE INFORMATION
(for Lock-up Time, Phase Noise and Reference Leakage)
Test Circuit
S.G.
OSCIN
LPF
DO
fin
Spectrum
Analyzer
fVCO = 680 MHz
KV = 50 MHz/V
fr = 25 kHz
fOSC = 14.4 MHz
LPF
VCC = 3.0 V
VVCO = 2.2 V
Ta = + 25 °C
CP : 6 mA mode
1.0 kΩ
VCO
2200 pF
2.2 kΩ
4700 pF
0.047 pF
• PLL Reference Leakage
ATTEN 10 dB
RL
0 dBm
VAVG 72
10 dB/
∆MKR −73.67 dB
25.0 kHz
∆MKR
25.0 kHz
−73.67 dB
CENTER 680.0000 MHz
RBW 1.0 kHz VBW 1.0 kHz
SPAN 200.0 kHz
SWP 500 ms
• PLL Phase Noise
ATTEN 10 dB
RL
0 dBm
VAVG 23
10 dB/
∆MKR −55.00 dB
5.37 kHz
∆MKR
5.37 kHz
−55.00 dB
CENTER 680.0000 MHz
RBW 100 Hz VBW 100 Hz
SPAN 20.00 kHz
SWP 1.60 s
(Continued)
21
MB15F72SP
(Continued)
• PLL Lock Up time
• PLL Lock Up time
755 MHz→680 MHz within ± 1 kHz
Hch→Lch 1.133 ms
680 MHz→755 MHz within±1 kHz
Lch→Hch 1.244 ms
755.004250 MHz
680.004000 MHz
755.000250 MHz
680.000000 MHz
754.996250 MHz
−822 µs
9.178 ms
679.996000 MHz
−822 µs
855.00 MHz
780.00 MHz
755.00 MHz
680.00 MHz
655.00 MHz
580.00 MHz
−822 µs
22
4.178 ms
1.000 ms/div
−822 µs
4.178 ms
1.000 ms/div
9.178 ms
4.178 ms
1.000 ms/div
9.178 ms
4.178 ms
1.000 ms/div
9.178 ms
MB15F72SP
■ APPLICATION EXAMPLE
VCO
OUTPUT
2.7 V
1000 pF
from controller
LPF
2.7 V
1000 pF
0.1 µF
0.1 µF
Clock
Data
LE
finRF
XfinRF
GNDRF
VCCRF
PSRF
VpRF
DoRF
20
19
18
17
16
15
14
13
12
11
MB15F72SP
1
2
3
4
5
6
7
8
9
10
OSCIN
GND
finIF
XfinIF
GNDIF
VCCIF
PSIF
VpIF
DoIF
LD/fout
Lock Det.
1000 pF
1000 pF
2.7 V
2.7 V
1000 pF
0.1 µF
0.1 µF
TCXO
OUTPUT
VCO
LPF
Notes : • Clock, Data, LE : Schmitt trigger circuit is provided(insert a pull-down or pull-up registor to
prevent oscillation when open-circuit in the input).
• Terminal number shows that of TSSOP-20.
23
MB15F72SP
■ USAGE PRECAUTIONS
(1) VCCRF, VpRF, VCCIF and VpIF must equal equal voltage.
Even if either RF-PLL or IF-PLL is not used, power must be supplied to both VCCRF, VpRF, VCCIF and VpIF to
keep them equal. It is recommended that the non-use PLL is controlled by power saving function.
(2) To protect against damage by electrostatic discharge, note the following handling precautions:
-Store and transport devices in conductive containers.
-Use properly grounded workstations, tools, and equipment.
-Turn off power before inserting or removing this device into or from a socket.
-Protect leads with conductive sheet, when transporting a board mounted device.
■ ORDERING INFORMATION
Part number
24
Package
MB15F72SPPFT
20-pin plastic TSSOP
(FPT-20P-M06)
MB15F72SPPV
20-pad plastic BCC
(LCC-20P-M04)
Remarks
MB15F72SP
■ PACKAGE DIMENSIONS
20-pin plastic TSSOP
(FPT-20P-M06)
Note 1 ) * : These dimensions do not include resin protrusion.
Note 2 ) Pins width and pins thickness include plating thickness.
* 6.50±0.10(.256±.004)
0.17±0.05
(.007±.002)
11
20
* 4.40±0.10
6.40±0.20
(.173±.004) (.252±.008)
INDEX
Details of "A" part
1.05±0.05
(Mounting height)
(.041±.002)
LEAD No.
1
10
0.65(.026)
"A"
0.24±0.08
(.009±.003)
0.13(.005)
M
0~8°
+0.03
(0.50(.020))
0.10(.004)
C
1999 FUJITSU LIMITED F20026S-2C-2
0.45/0.75
(.018/.030)
+.001
0.07 –0.07 .003 –.003
(Stand off)
0.25(.010)
Dimensions in mm (inches)
(Continued)
25
MB15F72SP
(Continued)
20-pad plastic BCC
(LCC-20P-M04)
3.00(.118)TYP
3.60±0.10(.142±.004)
16
0.80(.031)MAX
(Mounting height)
11
11
0.25±0.10
(.010±.004)
16
0.50(.020)
TYP
0.25±0.10
(.010±.004)
INDEX AREA
3.40±0.10
(.134±.004)
2.70(.106)
TYP
"D"
"A"
1
6
"C"
6
Details of "A" part
0.50±0.10
(.020±.004)
1
0.50(.020)
TYP
2.80(.110)REF
0.085±0.04
(.003±.002)
(Stand off)
0.05(.002)
"B"
Details of "B" part
0.50±0.10
(.020±.004)
Details of "C" part
0.50±0.10
(.020±.004)
Details of "D" part
0.30±0.10
(.012±.004)
C0.20(.008)
0.60±0.10
(.024±.004)
C
26
1999 FUJITSU LIMITED C20055S-1C-1
0.30±0.10
(.012±.004)
0.60±0.10
(.024±.004)
0.40±0.10
(.016±.004)
Dimensions in mm (inches)
MB15F72SP
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka,
Nakahara-ku, Kawasaki-shi,
Kanagawa 211-8588, Japan
Tel: +81-44-754-3763
Fax: +81-44-754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, USA
Tel: +1-408-922-9000
Fax: +1-408-922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: +1-800-866-8608
Fax: +1-408-922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
http://www.fujitsu-fme.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
http://www.fmap.com.sg/
F0002
 FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without
notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipments, industrial, communications, and
measurement equipments, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded
(such as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.