FUJITSU SEMICONDUCTOR DATA SHEET DS04-21364-3E ASSP Dual Serial Input PLL Frequency Synthesizer MB15F78SP ■ DESCRIPTION The Fujitsu MB15F78SP is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2550 MHz prescaler and a 1200 MHz prescaler. A 32/33 or a 64/65 for the 2550 MHz prescaler, and a 16/17 or a 32/33 for the 1200 MHz prescaler can be selected for the prescaler that enables pulse swallow operation. The BiCMOS process is used , as a result a supply current is typically 5.5 mA at 2.7 V. The supply voltage range is from 2.4 V to 3.6 V. A refined charge pump supplies well-balanced output current with 1.5 mA and 6 mA selectable by serial data. The new package (BCC20) decreases an area of MB15F78SP more than 30 % comparing with the former BCC16 (for dual PLL). MB15F78SP is ideally suited for wireless mobile communications, such as GSM. ■ FEATURES • High frequency operatio • • • • : RX synthesizer : 2550 MHz max : TX synthesizer : 1200 MHz max Low power supply voltage : VCC = 2.4 to 3.6 V Ultra Low power supply current : ICC = 5.5 mA typ. (VCC = Vp = 2.7 V, Ta = +25°C, SWTX = SWRX = 0, in TX/RX locking state) Direct power saving function : Power supply current in power saving mode Typ. 0.1 µA (VCC = Vp = 2.7 V, Ta = +25°C), Max. 10 µA (VCC = Vp = 2.7 V) Software selectable charge pump current: 1.5 mA/6.0 mA typ. (Continued) ■ PACKAGES 20-pin plastic TSSOP (FPT-20P-M06) 20-pad plastic BCC (LCC-20P-M04) MB15F78SP (Continued) • Dual modulus prescaler : 2550 MHz prescaler (32/33 or 64/65 )/1200 MHz prescaler (16/17 or 32/33) • 23-bit shift register • Serial input binary 14-bit programmable reference divider : R = 3 to 16,383 • Serial input programmable divider consisting of: - Binary 7-bit swallow counter : 0 to 127 - Binary 11-bit programmable counter: 3 to 2,047 • Built-in high-speed tuning, low-noise phase comparator, current-switching type constant current circuit • On–chip phase control for phase comparator • Built-in digital locking detector circuit to detect PLL locking and unlocking • Operating temperature : Ta = –40 to +85°C • Sireal data format compatible with MB15F08SL ■ PIN ASSIGNMENTS (TSSOP-20) TOP VIEW (BCC-20) TOP VIEW OSCIN 1 20 Clock GND 2 19 Data finTX 3 18 LE XfinTX 4 17 finRX GNDTX 5 16 XfinRX VCCTX 6 15 GNDRX PSTX 7 14 VCCRX VpTX 8 13 PSRX DoTX 9 12 VpRX LD/fout 10 11 DoRX (FPT-20P-M06) 2 OSCIN Data GND Clock finTX 1 XfinTX 2 GNDTX VCCTX 3 4 PSTX 5 VpTX 6 20 19 18 17 16 15 14 13 12 7 8 9 10 11 DoRX DoTX LD/fout VpRX (LCC-20P-M04) LE finRX XfinRX GNDRX VCCRX PSRX MB15F78SP ■ PIN DESCRIPTION Pin no. Pin name I/O Descriptions TSSOP BCC 1 19 OSCIN I 2 20 GND 3 1 finTX I Prescaler input pin for the TX-PLL. Connection to an external VCO should be via AC coupling. 4 2 XfinTX I Prescaler complimentary input pin for the TX-PLL section. This pin should be grounded via a capacitor. 5 3 GNDTX Ground for the TX-PLL section. 6 4 VCCTX Power supply voltage input pin for the TX-PLL section(except for the charge pump circuit), the oscillator input buffer and the shift register. 7 5 PSTX I 8 6 VpTX Power supply voltage input pin for the TX-PLL charge pump. 9 7 DOTX O Charge pump output for the TX-PLL section. 10 8 LD/fout O Lock detect signal output (LD)/phase comparator monitoring output (fout).The output signal is selected by LDS bit in the serial data. LDS bit = “H” ; outputs fout signal / LDS bit = “L” ; outputs LD signal 11 9 DORX O Charge pump output for the RX-PLL section. 12 10 VpRX Power supply voltage input pin for the RX-PLL charge pump. 13 11 PSRX I 14 12 VCCRX Power supply voltage input pin for the RX-PLL section(except for the charge pump circuit). 15 13 GNDRX Ground for the RX-PLL section. 16 14 XfinRX I Prescaler complimentary input pin for the RX-PLL section. This pin should be grounded via a capacitor. 17 15 finRX I Prescaler input pin for the RX-PLL. Connection to an external VCO should be via AC coupling. 18 16 LE I Load enable signal input(with the schmitt trigger circuit). When LE is set “H”, data in the shift register is transferred to the corresponding latch according to the control bit in a serial data. 19 17 Data I Serial data input(with the schmitt trigger circuit). A data is transferred to the corresponding latch(TX-ref. counter, TX-prog. counter, RX-ref.counter, RX-prog.counter) according to the control bit in a serial data. 20 18 Clock I Clock input for the 23-bit shift register (with a schmitt trigger circuit). One bit of data is shifted into the shift register on a rising edge of the clock. The programmable reference divider input. TCX0 should be connected with a AC coupling capacitor. Ground for OSC input buffer and the shift register circuit. Power saving mode control for the TX-PLL section. This pin must be set at “L” Power-ON. (Open is prohibited.) PSTX = “H” ; Normal mode / PSTX = “L” ; Power saving mode Power saving mode control for the RX-PLL section. This pin must be set at “L” Power-ON. (Open is prohibited.) PSRX = “H” ; Normal mode / PSRX = “L” ; Power saving mode 3 MB15F78SP ■ BLOCK DIAGRAM VCCTX (4) 6 PSTX 7 (5) Intermittent mode control (TX-PLL) 3 bit latch LDS SWTX FCTX finTX 3 (1) XfinTX 4 (2) GNDTX 5 (3) VpTX 8 (6) 11 bit latch 7 bit latch Binary 7-bit Binary 11-bit proswallowcounter grammable TX-PLL) counter(TX-PLL) fpTX Prescaler (TX-PLL) (16/17, 32/33) Phase comp. (TX-PLL) Charge Current pump Switch (TX-PLL). 9 DoTX (7) Lock Det. (TX-PLL) 2 bit latch T1 T2 14 bit latch 1 bit latch Binary 14-bit programmable ref. counter(TX-PLL) C/P setting counter LDTX frTX OSCIN 1 (19) T1 T2 OR 2 bit latch ( 15 ) finRX 17 XfinRX 16 ( 14 ) PSRX 13 (11) LE 18 ( 16 ) ( 17 ) Data 19 Clock 20 ( 18 ) Binary 14-bit programmable ref. counter(RX-PLL) C/P setting counter 14 bit latch 1 bit latch Intermittent mode control (RX-PLL) Schmitt circuit Schmitt circuit O : TSSOP ( ) : BCC 10 LD/ ( 8 ) fout Lock Det. (RX-PLL) LDS SWRX FCRX Binary 7-bit swallow counter (RX-PLL) Binary 11-bit programmable counter(RX-PLL) 3 bit latch 7 bit latch 11 bit latch Phase comp. (RX-PLL) Charge Current pump Switch (RX-PLL) fpRX Latch selector C C N N 1 2 23-bit shift register 2 ( 20 ) GND 4 LD frTX frRX fpTX fpRX Prescaler (RX-PLL) (32/33, 64/65) Schmitt circuit Selector AND frRX ( 12 ) 14 15 ( 13 ) VCCRX GNDRX 12 ( 10 ) VpRX 11 DoRX (9) MB15F78SP ■ ABSOLUTE MAXIMUM RATINGS Parameter Rating Symbol Unit Min. Max. VCC −0.5 4.0 V Vp VCC 4.0 V VI −0.5 VCC + 0.5 V LD/fout VO GND VCC V DoTX, DoRX VDD GND Vp V Tstg −55 +125 °C Power supply voltage Input voltage Output voltage Storage temperature WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Value Unit Min. Typ. Max. VCC 2.4 2.7 3.6 V Vp VCC 2.7 3.6 V Input voltage VI GND VCC V Operating temperature Ta −40 +85 °C Power supply voltage WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 5 MB15F78SP ■ ELECTRICAL CHARACTERISTICS (VCC = 2.4 V to 3.6 V, Ta = −40 °C to +85 °C) Parameter Symbol “H” level input voltage “L” level input voltage “H” level input voltage “L” level input voltage “H” level input current “L” level input current “H” level input current “L” level input current “H” level output voltage “L” level output voltage High impedance cutoff current “H” level output current “L” level output current Typ. Max. Unit 2.2 mA ICCRX *2 RX PLL 3.3 mA IPSTX PSTX = PSRX = “L” 0.1 *8 10 µA IPSRX PSTX = PSRX = “L” 0.1 *8 10 µA finTX *3 finTX TX PLL 50 1200 MHz finRX *3 finRX RX PLL 400 2550*9 MHz OSCIN fOSC 3 40 MHz finTX PfinTX TX PLL, 50 Ω system −15 +2 dBm finRX PfinRX RX PLL, 50 Ω system −15 *9 +2 dBm OSCIN VOSC 0.5 VCC VP - P Data, LE, Clock VIH Schmitt trigger input 0.7 VCC + 0.4 V VIL Schmitt trigger input 0.3 VCC − 0.4 V PSTX PSRX VIH 0.7 VCC V VIL 0.3 VCC V IIH *4 −1.0 +1.0 µA IIL *4 −1.0 +1.0 µA IIH 0 +100 µA IIL *4 −100 0 µA VCC − 0.4 V 0.4 V Data LE Clock PSTX PSRX OSCIN LD/fout “L” level output voltage “H” level output voltage Min. TX PLL Power saving current Input sensitivity Value ICCTX *1 Power supply current Operating frequency Condition DoTX DoRX DoTX DoRX LD/fout VOH VCC = Vp = 2.7 V, IOH = −1 mA VOL VCC = Vp = 2.7 V, IOL = 1 mA VDOH VCC = Vp = 2.7 V, IDOH = −0.5 mA Vp − 0.4 V VDOL VCC = Vp = 2.7 V, IDOL = 0.5 mA 0.4 V IOFF VCC = Vp = 2.7 V VOFF = 0.5 V to Vp − 0.5 V 2.5 nA IOH *4 VCC = Vp = 2.7 V −1.0 mA IOL VCC = Vp = 2.7 V 1.0 mA (Continued) 6 MB15F78SP (Continued) (VCC = 2.4 V to 3.6 V, Ta = −40 °C to +85 °C) Parameter “H” level output current “L” level output current Charge pump current rate Symbol Condition DoTX DoRX IDOH *4 DoTX DoRX IDOL Value Unit Min. Typ. Max. VCC = Vp = 2.7 V, CS bit = “H” VDOH = Vp/2, CS bit = “L” Ta = +25 °C −6.0 mA −1.5 mA VCC = Vp = 2.7 V, CS bit = “H” VDOL = Vp/2, CS bit = “L” Ta = +25 °C 6.0 mA 1.5 mA IDOL/IDOH IDOMT *5 VDO = Vp / 2 3 % vs VDO IDOVD *6 0.5 V ≤ VDO ≤ Vp − 0.5 V 10 % vs Ta IDOTA *7 10 % −40 °C ≤ Ta ≤ +85 °C, VDO = Vp / 2 *1 : finTX = 910 MHz, fosc = 12.8 MHz, VCCTX = VpTX = 2.7 V, SWTX = 0, Ta = +25 °C, in locking state. *2 : finRX = 2500 MHz, fosc = 12.8 MHz, VCCRX = VpRX = 2.7 V, SWRX = 0, Ta = +25 °C, in locking state. *3 : AC coupling. 1000 pF capacitor is connected under the condition of minimum operating frequency. *4 : The symbol “–” (minus) means direction of current flow. *5 : VCC = Vp = 2.7 V, Ta = +25 °C (||I3| – |I4||) / [ (|I3| + |I4|) / 2 ] × 100 (%) *6 : VCC = Vp = 2.7 V, Ta = +25 °C (Applied to each IDOL, IDOH) [ (||I2| – |I1||) / 2 ] / [ (|I1| + |I2|) / 2 ] × 100 (%) *7 : VCC = Vp = 2.7 V, Ta = +25 °C (Applied to each IDOL, IDOH) [ ||IDO (+85°C) | – |IDO (–40 °C) || / 2 ] / [ (|IDO (+85°C) | + |IDO (–40°C) |) / 2 ] × 100 (%) *8 : fosc = 12.8 MHz, VCCRX = VpRX = VCCTX = VpTX = 2.7 V, Ta = +25°C *9 : 2500 MHz to 2550 MHz, VCC = 2.7 V to 3.6 V, Pfinmin = −10 dBm I1 I3 I2 IDOL IDOH I4 I2 I1 0.5 Vp/2 Vp − 0.5 Vp Charge pump output voltage (V) 7 MB15F78SP ■ FUNCTIONAL DESCRIPTION 1. Pulse swallow function fVCO = [(P × N) + A] × fOSC ÷ R fVCO : Output frequency of external voltage controlled oscillator (VCO) P : Preset divide ratio of dual modulus prescaler (16 or 32 for TX-PLL, 32 or 64 for RX-PLL) N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047) A : Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127, A < N) fOSC : Reference oscillation frequency (OSCIN input frequency) R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383) 2. Serial Data Input Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of TX/RX-PLL sections, programmable reference dividers of TX/RX-PLL sections are controlled individually. Serial data of binary data is entered through Data pin. On rising edge of Clock, one bit of serial data is transferred into the shift register. On a rising edge of load enable signal, the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting. The programmable The programmable reference counter reference counter for the TX-PLL for the RX-PL The programmable counter and the swallow counter for the TX-PLL The programmable counter and the swallow counter for the RX-PLL CN1 0 1 0 1 CN2 0 0 1 1 (1) Shift Register Configuration • Programmable Reference Counter Data Flow (LSB) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (MSB) 15 16 17 18 19 20 21 22 23 CN1 CN2 T1 T2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 CS X CS R1 to R14 T1, 2 CN1,2 X : Charge pump currnet select bit : Divide ratio setting bits for the programmable reference counter (3 to 16,383) : Test purpose bit : Control bit : Dummy bits (Set “0” or “1”) Note : Data input with MSB first. 8 X X X MB15F78SP • Programmable Counter Data Flow (LSB) 1 2 3 4 5 6 7 8 9 (MSB) 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CN1 CN2 LDS SW FC A1 A2 A3 A4 A5 A6 A7 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 A1 to A7 N1 to N11 LDS SW FC CN1, 2 : Divide ratio setting bits for the swallow counter (0 to 127) : Divide ratio setting bits for the programmable counter (3 to 2,047) : LD/fout signal select bit : Divide ratio setting bit for the prescaler : Phase control bit for the phase detector : Control bit Note : Data input with MSB first. (2) Data setting • Binary 14-bit Programmable Reference Counter Data Setting Divide ratio R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 3 0 0 0 0 0 0 0 0 0 0 0 0 1 1 4 • • • 16383 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 1 • • • 1 0 • • • 1 0 • • • 1 Note : Divide ratio less than 3 is prohibited. • Binary 11-bit Programmable Counter Data Setting Divide ratio N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 3 0 0 0 0 0 0 0 0 0 1 1 4 • • • 2047 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 1 • • • 1 0 • • • 1 0 • • • 1 Note : Divide ratio less than 3 is prohibited. • Binary 7-bit Swallow Counter Data Setting Divide ratio A7 A6 A5 A4 A3 A2 A1 0 0 0 0 0 0 0 0 1 • • • 127 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 0 • • • 1 1 • • • 1 9 MB15F78SP • Prescaler Data Setting SW = “H” SW = “L” Prescaler divide ratio TX-PLL 16/17 32/33 Prescaler divide ratio RX-PLL 32/33 64/65 Divide ratio • Charge Pump Current Setting • LD/fout Output Select Data Setting Current value CS LD/fout output signal LDS ±6.0 mA 1 fout signal 1 ±1.5 mA 0 LD signal 0 • Test Purpose Bit Setting LD/fout pin state T1 T2 Outputs frTX. 0 0 Outputs frRX. 1 0 Outputs fpTX. 0 1 Outputs fpRX. 1 1 • Phase Comparator Phase Switching Data Setting FC = “H” FC = “L” DoTX/DoRX DoTX/DoRX fr > fp H L fr < fp L H fr = fp Z Z Phase comparator input Z : High-impedance Depending upon the VCO and LPF polarity, FC bit should be set. High (1) (1) VCO polarity FC = “H” (2) VCO polarity FC = “L” VCO Output Frequency (2) LPF Output voltage Note : Give attention to the polarity for using active type LPF. 10 Max. MB15F78SP 3. Power Saving Mode (Intermittent Mode Control Circut) Status PSTX/PSRX pins Normal mode H Power saving mode L The intermittent mode control circuit reduces the PLL power consumption. By setting the PS pins low, the device enters into the power saving mode, reducing the current consumption. See the Electrical Characteristics chart for the specific value. The phase detector output, Do, becomes high impedance. For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table. Setting the PS pins high, releases the power saving mode, and the device works normally. The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation. When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup time. To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation. Notes: •When power (VCC) is first applied, the device must be in standby mode, PSTX = PSRX = Low, for at least 1 µs. •PS pins must be set at “L” for Power-ON OFF V CC ON tV ≥ 1 µs Clock Data LE tPS ≥ 100 ns PS TX PS RX (1) (2) (3) (1) PSTX = PSRX = “L” (power saving mode) at Power-ON (2) Set serial data 1 µs later after power supply remains stable (VCC > 2.2 V). (3) Release power saving mode (PSTX, PSRX : “L” → “H”) 100 ns later after setting serial data. 11 MB15F78SP 4. Serial data input timing Frequency multiplier setting is performed through a serial interface using the Data pin, Clock pin, and LE pin. Setting data is read into the shift register at the rise of the clock signal, and transferred to a latch at the rise of the LE signal. The following diagram shows the data input timing. 1st data 2nd data Control bit Data MSB Invalid data LSB Clock t1 t2 t5 t4 t7 LE t3 Parameter Min. Typ. Max. Unit Parameter Min. Typ. Max. Unit t1 20 ns t5 30 ns t2 20 ns t6 100 ns t3 30 ns t7 100 ns t4 20 ns Note : LE should be “L” when the data is transferred into the shift register. 12 t6 MB15F78SP ■ PHASE COMPARATOR OUTPUT WAVEFORM fr TX / fr RX fp TX / fp RX t WU t WL LD (FC bit = High) Do TX / Do RX H Z L (FC bit = Low) Do TX / Do RX H Z L LD Output Logic Table TX-PLL section RX-PLL section LD output Locking state/Power saving state Locking state/Power saving state H Locking state/Power saving state Unlocking state L Unlocking state Locking state/Power saving state L Unlocking state Unlocking state L Notes: • Phase error detection range = –2 π to + 2 π • Pulses on DoTX/DoRX signals are output to prevent dead zone. • LD output becomes low when phase error is tWU or more. • LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more. • tWU and tWL depend on OSCIN input frequency as follows. tWU > 2/fosc: e.g. tWU > 156.3 ns when fosc = 12.8 MHz tWU < 4/fosc: e.g. tWL < 312.5 ns when fosc = 12.8 MHz 13 MB15F78SP ■ TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCIN) fout Oscilloscope 1000 pF VCCTX VpTX 0.1 µF 1000 pF S.G. 50 Ω 0.1 µF 1000 pF LD/ fout DoTX VpTX PSTX VCCTX GNDTX XfinTX finTX GND OSCIN 10 9 8 7 6 5 4 3 2 1 11 12 13 14 15 16 17 18 19 20 DoRX VpRX PSRX VCCRX GNDRX XfinRX finRX LE Data Clock 50 Ω 1000 pF Controller (divide ratio setting) 1000 pF VpRX 0.1 µF VCCRX 0.1 µF Note : The terminal number shows that of TSSOP-20 14 50 Ω S.G. S.G. MB15F78SP ■ TYPICAL CHARACTERISTICS 1. finRX input sensitivity RX-PLL input sensitivity vs. Input frequency Input sensitivity PfinRX (dBm) Ta = +25 °C ,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,, 10 0 SPEC −10 −20 VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V −30 −40 −50 0 500 1000 1500 2000 2500 3000 Input frequency finRX (MHz) 2. finTX input sensitivity TX-PLL input sensitivity vs. Input frequency Input sensitivity PfinTX (dBm) 10 0 −10 −20 ,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,, Ta = +25 °C SPEC VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V −30 −40 −50 0 200 400 600 800 1000 1200 1400 Input frequency finTX (MHz) 15 MB15F78SP 3. OSCIN input sensitivity ,,,, ,,,, Input sensitivity VOSC (dBm) 10 Input sensitivity vs. Input frequency Ta = +25 °C SPEC 0 −10 −20 −30 VCC = 2.4 V −40 VCC = 2.7 V −50 VCC = 3.0 V VCC = 3.6 V −60 0 20 40 60 80 100 120 140 Input frequency fOSC (MHz) 16 160 180 200 220 MB15F78SP 4. Do output current (RX PLL) • 1.5 mA mode IDO vs. VDO Charge pump output current IDO (mA) 10.0 Ta = +25 °C VCC = Vp = 2.7 V IDOL 0.0 IDOH −10.0 0.0 1.0 2.0 2.7 Charge pump output voltage VDO (V) • 6.0 mA mode IDO vs. VDO Charge pump output current IDO (mA) 10.0 Ta = +25 °C VCC = Vp = 2.7 V IDOL 0.0 IDOH −10.0 0.0 1.0 2.0 2.7 Charge pump output voltage VDO (V) 17 MB15F78SP 5. Do output current (TX PLL) • 1.5 mA mode IDO vs. VDO Charge pump output current IDO (mA) 10.0 Ta = +25 °C VCC = Vp = 2.7 V IDOL 0.0 IDOH −10.0 0.0 1.0 2.0 2.7 Charge pump output voltage VDO (V) • 6.0 mA mode IDO vs. VDO Charge pump output current IDO (mA) 10.0 Ta = +25 °C VCC = Vp = 2.7 V IDOL 0.0 IDOH −10.0 0.0 1.0 2.0 Charge pump output voltage VDO (V) 18 2.7 MB15F78SP 6. fin input impedance finTX input impedance 4 : −11.723 Ω −45.613 Ω 2.9077 pF 1 200.000 000 MHz 1 : 749.72 Ω −841.66 Ω 50 MHz 2 : 32.047 Ω −182.58 Ω 400 MHz 3 : 14.746 Ω −84.391 Ω 800 MHz 1 2 4 3 START 50.000 000 MHz STOP 1 200.000 000 MHz finRX input impedance 4 : 24.681 Ω 15.306 Ω 974.39 pH 2 500.000 000 MHz 1 : 314.47 Ω −609.53 Ω 100 MHz 2 : 15.457 Ω −64.836 Ω 1 GHz 4 3 : 15.612 Ω −6.8101 Ω 2 GHz 1 3 2 START 100.000 000 MHz STOP 2 500.000 000 MHz 19 MB15F78SP 7. OSCIN input impedance OSCIN input impedance 4 : 34.313 Ω −679.06 Ω 2.3437 pF 100.000 000 MHz 1 : 12.448 kΩ −10.978 kΩ 3 MHz 2 : 521.62 Ω −3.3743 kΩ 20 MHz 3 : 133.38 Ω −1.7066 kΩ 40 MHz 4 1 2 3 START 3.000 000 MHz 20 STOP 100.000 000 MHz MB15F78SP ■ REFERENCE INFORMATION (for Look-up time, Phase noise and Reference leakage) Test Circuit S.G. OSCIN LPF DO fVCO = 1733 MHz KV = 44 MHz/V fr = 200 kHz fOSC = 13 MHz LPF fin VCC = 3.0 V VVCO = 3.5 V Ta = +25 °C CP : 6 mA mode 27 kΩ Spectrum Analyzer 2200 pF VCO 2.0 kΩ 180 pF 0.022 pF • PLL Reference Leakage VAVG 34 10 dB/ ∆MKR −73.67 dB 200 kHz ∆MKR 200 kHz D −73.67 dB S CENTER 1.733000 GHz RBW 3.0 kHz VBW 3.0 kHz SPAN1.000 MHz SWP 280 ms • PLL Phase Noise VAVG 42 10 dB/ ∆MKR −53.33 dB 14.75 kHz ∆MKR 14.75 kHz −53.33 dB D S CENTER 1.73300000 GHz RBW 100 Hz VBW 100 Hz SPAN 50.00 kHz SWP 4.00 s (Continued) 21 MB15F78SP (Continued) • PLL Lock-up time • PLL Lock-up time 1733 MHz→1803 MHz within ± 1 kHz Lch→Hch 400 µs 1803 MHz→1733 MHz within ± 1 kHz Hch→Lch 378 µs 1.90300 GHz 1.83300 GHz 1.80300 GHz 1.73300 GHz 1.70300 GHz −2.189 ms T1 400 µs 1.63300 GHz −2.189 ms T1 400 µs 1.803005250 GHz 1.733004500 GHz 1.803001250 GHz 1.733000500 GHz 1.802997250 GHz −2.189 ms T1 400 µs 22 311 µs 2.811 ms 500.0 µs/div T2 800 µs ∆ 400 µs 311 µs 2.811 ms 500.0 µs/div T2 778 µs ∆ 378 µs 1.732996500 GHz 311 µs 2.811 ms 500.0 µs/div T2 800 µs ∆ 400 µs −2.189 ms T1 400 µs 311 µs 2.811 ms 500.0 µs/div T2 778 µs ∆ 378 µs MB15F78SP ■ APPLICATION EXAMPLE VCO OUTPUT from controller LPF 2.7 V 1000 pF 2.7 V 1000 pF 0.1 µF 0.1µ F Clock Data LE finRX XfinRX GNDRX VCCRX PSRX VpRX DoRX 20 19 18 17 16 15 14 13 12 11 MB15F78SP 1 2 3 4 5 6 7 8 9 10 OSCIN GND finTX XfinTX GNDTX VCCTX PSTX VpTX DoTX LD/fout Lock Det. 1000 pF 1000 pF 2.7 V 2.7 V 1000 pF 0.1 µF 0.1 µF TCXO OUTPUT VCO LPF Notes : • Clock, Data, LE : Schmitt trigger circuit is provided (insert a pull-down or pull-up register to prevent oscillation when open-circuit in the input). • The terminal number shows that of TSSOP-20. 23 MB15F78SP ■ USAGE PRECAUTIONS (1) VCCRX, VpRX, VCCTX and VpTX must equal equal voltage. Even if either RX-PLL or TX-PLL is not used, power must be supplied to both VCCRX, VpRX, VCCTX and VpTX to keep them equal. It is recommended that the non-use PLL is controlled by power saving function. (2) To protect against damage by electrostatic discharge, note the following handling precautions: -Store and transport devices in conductive containers. -Use properly grounded workstations, tools, and equipment. -Turn off power before inserting or removing this device into or from a socket. -Protect leads with conductive sheet, when transporting a board mounted device. ■ ORDERING INFORMATION Part number 24 Package MB15F78SPPFT 20-pin, plastic TSSOP (FPT-20P-M06) MB15F78SPPV 20-pad, plastic BCC (LCC-20P-M04) Remarks MB15F78SP ■ PACKAGE DIMENSIONS 20-pin plastic TSSOP (FPT-20P-M06) Note 1 ) * : These dimensions do not include resin protrusion. Note 2 ) Pins width and pins thickness include plating thickness. * 6.50±0.10(.256±.004) 0.17±0.05 (.007±.002) 20 11 * 4.40±0.10 6.40±0.20 (.173±.004) (.252±.008) INDEX Details of "A" part 1.05±0.05 (Mounting height) (.041±.002) LEAD No. 1 10 0.65(.026) "A" 0.24±0.08 (.009±.003) 0.13(.005) M 0~8° +0.03 (0.50(.020)) 0.10(.004) C 1999 FUJITSU LIMITED F20026S-2C-2 0.45/0.75 (.018/.030) +.001 0.07 –0.07 .003 –.003 (Stand off) 0.25(.010) Dimensions in mm (inches) (Continued) 25 MB15F78SP (Continued) 20-pad plastic BCC (LCC-20P-M04) 3.60±0.10(.142±.004) 16 16 3.00(.118)TYP 0.80(.031)MAX (Mounting height) 11 11 11 11 0.25±0.10 (.010±.004) 0.50(.020) TYP 0.25±0.10 (.010±.004) INDEX AREA 3.40±0.10 (.134±.004) 2.70(.106) TYP "D" "A" 1 1 6 6 6 6 0.085±0.04 (.003±.002) (Stand off) 0.05(.002) 16 16 Details of "A" part 0.50±0.10 (.020±.004) Details of "B" part 0.50±0.10 (.020±.004) "B" "C" 0.50(.020) TYP 2.80(.110)REF Details of "C" part 0.50±0.10 (.020±.004) 1 1 Details of "D" part 0.30±0.10 (.012±.004) C0.20(.008) 0.60±0.10 (.024±.004) C C 26 1999 FUJITSU LIMITED C20055S-1C-1 0.30±0.10 (.012±.004) 0.60±0.10 (.024±.004) 0.40±0.10 (.016±.004) Dimensions in mm (inches) MB15F78SP FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8588, Japan Tel: +81-44-754-3763 Fax: +81-44-754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 F0005 FUJITSU LIMITED Printed in Japan All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. 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