Mitsumi MM1327XD Wide discriminator monolithic ic Datasheet

MITSUMI
Wide Discriminator MM1327
Wide Discriminator
Monolithic IC MM1327
Outline
This IC identifies the letter box portion of wide broadcast, etc. video signals. The luminance and chroma
signals are used so that the rate of identification on dark screens is increased. Output is the total of 6bit ADC
data and character signal, etc. white peak signal discriminator bit, for 7bit data output.
In addition, an EDTV2 simple discrimination function is built-in.
Features
1. Signal level discrimination using composite luminance and chroma signal
2. Discrimination of video signal within horizontal scanning interval can be done every scan due to integrated
output
3. Built-in white peak detection circuit for subtitles
4. Built-in EDTV2 simple discrimination function
5. 22H discrimination output (COMB-THROUGH) circuit built-in
6. Built-in window limiter circuit
7. Data output is 7bit serial output format : 6bit ADC + peak detection
8. Operates on +5V single power supply
Package
SDIP-30
Applications
Wide TV
MITSUMI
Wide Discriminator MM1327
Block Diagram
Pin Assignment
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SDIP-30
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
I
Q
Y
AGND
MAX
VCOM
ZR
INT IN
INT OUT
S/H
DA
DGND
HD
VD
GP
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
ADCLK
NRZCLK
DATA
EDTV2
VDO
COMB-TH
LIMIT-SW
COMB-SW
NTSC/PAL
IR
DELAY
SEPA-LEVEL
LIMIT-LEVEL
GC
VCC
MITSUMI
Wide Discriminator MM1327
Pin Description
Pin no.
Pin name
1
I
2
Q
3
Y
4
AGND
12
DGND
5
MAX
Function
Video signal input pin
Composite output of input
video signal maximum
value
6
VCOM
Internal reference voltage
output
Connect 1µF between this
pin and GND.
7
ZR
Connection pin for MAX
output clamp capacitor
8
INT IN
Integrated circuit input pin
Integrated reset done at GP
timing.
Internal equivalent circuit diagram
MITSUMI
Wide Discriminator MM1327
Pin no.
Pin name
9
INT OUT
10
S/H
Function
Integrated output pin and
sample and hold pins
S/H of integration results
at HD timing
11
DA
DAC output for consecutive
comparison ADC
--------------------------------------
13
HD IN
Timing pulse input pins
15
GP IN
GP operates even on SCP
input (5VP-P).
14
VD IN
Timing pulse input pin
VD operates even on SCP
input (5VP-P).
16
ADCLK
Clock input pin for
consecutive ADC
Internal equivalent circuit diagram
MITSUMI
Wide Discriminator MM1327
Pin no.
Pin name
17
NRZCLK
25
IR
26
DELAY
18
DATA
19
EDTV2
20
VDO
21
COMB-TH
22
LIMIT-SW
23
COMB-SW
24
NTSC/PAL
27
SEPA LEVEL
Function
Clock input pins for NRZ
discrimination
Input CLK is integrated by
resistor connected between
Pin 25 and GND and
internal 20pF, and delay is
set by Pin 26 voltage.
Data output pins
Switching pins
NRZ discrimination
luminance signal SEPA
level adjustment pin
28
LIMIT LEVEL
MAX composite output
limit level adjustment pin
Limit area:
NTSC : 42~241H
PAL : 46~291H
29
GAIN
30
VCC
I, Q gain adjustment pin
Internal equivalent circuit diagram
MITSUMI
Wide Discriminator MM1327
Absolute Maximum Ratings
Item
Symbol
Ratings
Units
Operating temperature
TOPR
-20~+75
°C
Storage temperature
TSTG
-40~+125
°C
Power supply voltage
VCC max.
V
Input voltage
VIN max.
7.0
<
GND = VIN <= VCC
Allowable loss
Pd
800
mW
V
Recommended Operating Conditions
Item
Symbol
Ratings
Units
Operating temperature
TOPR
-20~+75
°C
Operating voltage
VOPR
4.5~5.5
V
MITSUMI
Wide Discriminator MM1327
Electrical Characteristics
(Except where noted otherwise, Ta=25°C, VCC=5.0V)
Item
Symbol
Consumption current
ICC
Measurement conditions
Min. Typ. Max. Units
20
30
2.0
2.2
2.4
2.0
2.2
2.4
2.0
2.2
2.4
2.0
2.2
2.4
mA
MAX amp
Clamping level
Y
VYIN
I
VIIN
Q
VQIN
V max.
MAX output pin voltage
Maximum input level
Y
V max.Y
1.0
I
V max.I
0.6
Q
V max.Q
0.6
GY
Y input voltage gain
Maximum gain
VCA
Minimum gain
*1
*1
*1
*1
*2
I
G max.I
VGC=1.2V
Q
G max.Q
VGC=1.2V
I
G min.I
VGC=3.6V
Q
G min.Q
VGC=3.6V
GIQ
I, Q gain difference
-0.5
*3
*3
*3
*3
GIQ=GI-GQ
V
V
VP-P
0.0
0.5
+11.5 +12.0 +12.5
dB
dB
+11.5 +12.0 +12.5
-0.5
0.0
0.5
-0.5
0.0
0.5
-0.5
0.0
0.5
5
7
dB
dB
EDTV II discrimination
NRZ detection level
NRZ detection readout timing
NRZCLK pin input current
L
VYSL
H
VYSH
L
VCSL
H
VCSH
L
INRZCL
VNRZCLK=0.4V
1
H
INRZCH
VNRZCLK=4.5V
1
27
30
0.4
1.5
0.7
1.8
IR pin voltage
VIR
EDTV II output voltage L
VNL
INL=1mA
HDIN
VTHD
HD
2.30
2.50
2.70
VDIN
VTVD
VD or SCP
0.63
0.83
1.03
GPIN
VTGP
GP or SCP
3.69
3.89
4.09
L
IHDL
VHD=0.4V
1
H
IHDH
VHD=4.5V
1
L
IVDL
VVD=0.4V
1
H
IVDH
VVD=4.5V
1
L
IGPL
VGP=0.4V
1
H
IGPH
VGP=4.5V
1
L
VTCOSL
H
VTCOSH
2.2
2.4
IRE
µS
µA
2.6
V
0.4
V
Trigger signal
Sync signal separation level
HD pin input current
VD pin input current
GP pin input current
COMB-SW switching voltage
0.7
2.1
V
µA
µA
µA
V
COMB-TH output voltage L
VOCOMB
ICOMB=1mA
0.4
V
VDO output voltage L
VOVDO
IVDO=1mA
0.4
V
MITSUMI
Wide Discriminator MM1327
Note 1 : 1 Clamp level and MAX output pin voltage
Measure voltage on each pin when GPIN and HDIN are connected to VCC.
*
Note 2 : 2 Y input voltage gain
Input a sweep signal to Y input, input a clamp pulse synchronized to HSYNC to GPIN pin, and
measure voltage gain at MAX pin for 100kHz.
*
Note 3 : 3 I, Q max/min gain
Input a square wave signal as shown below and a GPIN signal to I input (or Q input) and GPIN
pin, and measure voltage gain at MAX pin.
*
0.3V
I or Q signal
0V
5V
GP pin
0V
2µS
63.5µS
Note 4 : 4 MAX amp limit level
Measure limit level at MAX pin when LIMIT-SW pin is high. However, the limit range is as follows
for the NTSC/PAL pin.
*
Note 5 : 5 Offset voltage for reset
Connect GPIN pin to VCC and measure potential difference between INT IN pin and INT OUT pin.
*
Note 6 : 6 Integrated limit voltage
Input a 100% white signal to Y input and a clamp pulse synchronized to HSYNC to GPIN pin.
Measure INT OUT pin voltage at integration end at this time.
*
Y input
100IRE
INT OUT output
VINTL
MITSUMI
Wide Discriminator MM1327
Timing Chart 1
1st field
259H 260H 261H 262H 1H
2nd field
2H
3H
4H
5H
6H
7H
8H
9H
10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 20H 21H 22H 23H 24H 25H
Composite
-5V
-2.8V
-1.7V
-0V
SCP
-5V
GP
-0V
-5V
VB
-0V
-5V
RB
-0V
VDO
COMB-TB
1st field
260H 261H 262H 263H 1H
2nd field
2H
3H
4H
5H
6H
7H
8H
9H
10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 20H 21H 22H 23H 24H 25H
Composite
SCP
-5V
-2.8V
-1.7V
-0V
-5V
GP
-0V
-5V
VB
-0V
-5V
RB
-0V
VDO
COMB-TB
MITSUMI
Wide Discriminator MM1327
Timing Chart 2
100IRE
50IRE
50IRE
0IRE
Y input
+0.15V
I (Q) input
-0.15
MAX output
tegrated output
3FM
S/H
00M
GP
HD
ADCLX
DATA
PEAK 05
00
1. The largest of Y, I and Q video input signals is output on MAX output pin.
2. MAX output date is integrated during horizontal scanning.
3. Integration results are sampled and held at HD pulse timing.
4. Consecutive comparison ADC outputs data as serial data.
(Serial data is 1H delayed from video signal input.)
5. Output data configuration is as shown in the table below.
Data configuration
PEAK
Video
DATA
Peak of more than 50IRE
1
White scanning
00
No peak of more than 50IRE
0
Black scanning
⇔
Y input
3F
Timing Chart 3
1
0
1
1
0
YIN (22H)
NRZCLK
Integrated NRZCLK
(Internal circuit)
DELAY
NRZ discrimination timing
1. When YIN input signal matches "10110" at NRZ discrimination timing, it is identified as an EDTV2 signal.
EDTV2 pin is high for EDTV2 identification.
MITSUMI
Measuring Circuit
Wide Discriminator MM1327
Similar pages