FUJITSU SEMICONDUCTOR DATA SHEET DS04-27707-2E ASSP for Power Supply Applications (For Secondary Battery) Li-Ion Battery Protection IC MB3836 ■ DESCRIPTION The MB3836 is a lithium-ion battery protection IC for three cells series lithium-ion battery pack in a notebook PC’s. This IC supports charging at 12.6 V and detects an over-charge, over-discharge, and over-current to control charging and discharging. The IC has a built-in function that makes the battery rechargeable even when the battery voltage has decreased to 0 V. Upon detection of an over-discharge from the lithium-ion battery, the IC outputs a preliminary signal to stop discharging. This feature allows the notebook PC to save its memory data to hard disk. In addition, the IC allows the battery to be used up to the over-discharge level of each cell, increasing the operating time. After detecting an over-discharge, the IC disconnects all of its biases so that its current consumption becomes 0 µA. The IC can therefore make the battery pack rechargeable even when it has been left for an extended period of time with the output disconnected due to over-discharging. The battery can also be set into a quasi-over-discharged state even when the cell voltage is equal to or greater than the over-discharge detection voltage. When the notebook PC is shipped, the IC can prevent the battery pack from being discharged and turn off its bias sources, allowing the battery pack to be stored for a long time. The IC’s remote on/off function can turn off the output from the detached battery pack without the need for an external logic circuit or any mechanism on the notebook PC. This prevents the output from being short-circuited by a malfunction and facilitates the handling of the battery pack itself. The MB3836 is the best IC for protecting the lithium-ion battery pack used for a notebook PC. ■ PACKAGE 20-pin plastic SSOP (FPT-20P-M03) MB3836 ■ FEATURES • • • • • • • Power supply voltage range : 6 V to 13.5 V High-precision over-charge detection voltage : 4.325 V ± 0.025 V Circuit power consumption after detecting over-discharge : 0 µA (Typ) Built-in quasi-over-discharge function Built-in pre-alarm function before shutting down of over-discharge Built-in remoting ON/OFF function Built-in over-discharge current detecting function with 2-step delay time : Vth = 300 mV→7 ms (Typ) : Vth = 600 mV→500 µs (Typ) • Built-in charge recovery function for 0 V cell ■ PIN ASSIGNMENT (TOP VIEW) OCV : 1 20 : OUTON COUT : 2 19 : PF DOUT : 3 18 : PDWN N.C. : 4 17 : MSW2 VS : 5 16 : MSW1 VCC : 6 15 : VMON BATH : 7 14 : COVT BATM : 8 13 : COCT BATL : 9 12 : CUVT GND : 10 11 : CPDT (FPT-20P-M03) 2 MB3836 ■ PIN DESCRIPTIONS Pin no. Pin name I/O Description 1 OCV I Over-current state and discharging/charging state detection terminal 2 COUT O Pch MOS control output terminal for charging control switch 3 DOUT O Pch MOS control output terminal for discharging control switch 4 N.C. No connection 5 VS O “H” level output terminal for remoting ON function 6 VCC Power supply terminal 7 BATH I Battery connection terminal 8 BATM I Battery connection terminal 9 BATL I Battery connection terminal 10 GND GND terminal 11 CPDT Capacitor connection terminal for setting power-down delay time 12 CUVT Capacitor connection terminal for setting PF output delay time 13 COCT Capacitor connection terminal for setting over-current detection time 14 COVT Capacitor connection terminal for setting over-charge detection time 15 VMON O Output terminal of monitoring cell voltage Switching signal of monitoring cell voltage input terminal 16 17 MSW1 MSW2 I I MSW1 MSW2 VMON output Cell voltage input block SW L L Depend on over-charge detection block L H H cell voltage Off H L M cell voltage Off H H L cell voltage Off 18 PDWN I Power down signal input terminal After input “H” level, Latch 3 will be set, DOUT=”H” level, and OCV=”L” level. At this time, all battery connecting terminal will be released, and all bias will be set OFF. 19 PF O PF signal output terminal 20 OUTON I Remoting ON signal input terminal After input “L” level, the bias of over-charge detection block will be set OFF. At this time, DOUT and COUT value will be equal to “H” level. 3 4 300 mV ON/OFF 600 mV Delay circuit + (7 ms) (500 µs) − Latch1 bias ON/OFF [Over-current detection block] 600 Ω Reset + [Cell voltage input block] BATH 7 − OCV 1 [Cell voltage monitoring block] ×1 + [Over-charge detection block] − 100 kΩ Reset Delay circuit (23 ms) 5 Latch2 20 OUTON + − BATM 8 VS [Remote ON circuit block] ×1 + 100 kΩ − 4.325 V (± 0.6%) BATL 9 100 kΩ [Over-discharge detection, and power fail circuit block] − − − ×1 + 2.75 V (±2%) Reset Latch3 Decoder 10 GND 15 16 17 VMON MSW1 MSW2 19 PF PF output time (2 s) 18 PDWN Power down delay time (20 s) 13 14 11 12 COCT COVT CPDT CUVT MB3836 bias Reference voltage block COUT 2 ■ BLOCK DIAGRAM DOUT 3 VCC 6 MB3836 ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Conditions VCC Input voltage Rating Unit Min Max 20 V VI BATH, OCV, PDWN, OUTON, PF, MSW1, MSW2 terminals 20 V Collector output voltage VO COUT terminal 25 V Output current IO DOUT, COUT terminals (DC) 2 mA Peak output current IO DOUT, COUT terminals Duty = tON / t 2 / Duty mA Power dissipation PD Ta ≤ + 25 °C 540 * mW Operating temperature Ta −30 + 85 °C Tstg −55 + 125 °C Power supply voltage Storage temperature * : When mounted on a 10 cm square double-sided epoxy board. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Power supply voltage Symbol Conditions VCC Input voltage VI OCV, PDWN, OUTON, MSW1, MSW2 terminals Output current IO VS terminal External OCV terminal resistor Capacitor for setting delay time Value Unit Min Typ Max 6.0 12.6 13.5 V 0 18 V −10 0 mA ROCV 10 Ω COVT 220 10000 pF CUVT 0.001 0.15 µF CPDT 0.001 1.5 µF COCT 220 560 pF WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 5 MB3836 ■ ELECTRICAL CHARACTERISTICS Parameter Detection voltage Over-charge Hysteresis width detection block Input current Pin No. VTH 2, 7, 8, 9 VH IIN 4.300 4.325 4.350 V Ta = 0 °C to + 70 °C, Each cell voltage 4.280 4.325 4.370 V 0.14 0.20 0.26 V 7, 8, 9 Each cell voltage = 4.2 V 0.1 0.5 µA 11.5 23 34.5 ms 2, 7, 8, 9 COVT = 0.01 µF Output voltage VOL 2 COUT = 1 mA 0.75 1.0 V Output leakage current ILEAK 2 COUT = 13.5 V 0 0.5 µA Detection voltage VTH 7, 8, 9, 19 2.695 2.75 2.805 V PF output delay time tD1 19 CUVT = 0.15 µF, VCC = 8.5 V 1 2 3 s PF Min pulse width tP 19 CUVT = 0.15 µF, VCC = 8.5 V 7* ms Output voltage VOL 19 PF = 1 mA 0.75 1.0 V Output leakage current ILEAK 19 PF = 13.5 V 0 0.5 µA Input threshold voltage VTH 2.0 3.5 5.0 V Input current IIN 18 PDWN = 5 V 50 100 µA Power-down delay time tD2 3 CPDT = 1.5 µF, VCC = 8.5 V 10 20 30 s VTH1 1, 3, 13 Voltage between VCC terminal and OCV terminal 0.22 0.30 0.38 V VTH2 1, 3, 13 Voltage between VCC terminal and OCV terminal 0.45 0.60 0.75 V tD1 3 COCT = 560 pF VTH2 > VCC−OCV > VTH1 4 7 10 ms tD2 3 COCT = 560 pF VCC−OCV > VTH2 250 500 750 µs VOL 3 DOUT = 1 mA 1.0 V VOH 3 DOUT = −0.4 mA VCC− 0.4 V 22.5 45 67.5 µA 0.6 * V 3, 18 Each cell voltage = 2 V Delay time Output voltage Cell voltage input block Ta = + 25 °C, Each cell voltage 2 Detection voltage Overcurrent detection block Conditions tD Delay time Overdischarge detection, power-fail circuit block Symbol (VCC = 12.6 V, Ta = + 25 °C) Value Unit Min Typ Max Input current at over-charge IIN 7, 8, 9 Each cell voltage = 4.5 V Short cell detection voltage VTH Cell voltage without 7, 8, 9 measuring cell = 3.6 V at COUT = “L”→“H” *: Standard design value (Continued) 6 MB3836 (Continued) Symbol Pin No. Conditions VTLH 1, 2 Input current IIN 1 Input resistance at power-down RI 1 Input thereshold voltage VTH 20 Input current IIN 20 OUTON = 13.5 V Output voltage VOH 5 VS = −4 mA Output current IO 5 VS = 0 V −30 Output leakage current ILEAK 5 VS = 0 V, Each cell voltage = 2 V Voltage gain AV 15 Cell voltage = 2.9 V to 4.2 V Input thereshold voltage VTH 16, 17 IIN 16, 17 MSW1 = MSW2 = 5 V Parameter Input thereshold voltage Remoting ON circuit block Cell voltage Input current monitoring Output source block current Output sink current All device (VCC = 12.6 V, Ta = + 25 °C) Value Unit Min Typ Max Power supply current 0.8 1.4 2.0 V 10 20 µA 480 600 720 Ω 0.8 1.4 2.0 V 13 17 µA V −11 mA −0.5 0 µA 0.98 1.0 1.02 V/V 0.8 1.4 2.0 V 50 100 µA OCV = 13.5 V VCC−0.5 VCC−0.2 IOH 15 Each cell voltage = 2.9 V, MON = 1.9 V −350 −180 µA IOL 15 Each cell voltage = 2.9 V, MON = 3.9 V 40 80 µA ICC1 6 VCC = 12.6 V, normal state, OUTON = 5 V 75 110 µA ICC2 6 VCC = 8.7 V, normal state, OUTON = 5 V 65 95 µA ICC3 6 VCC = 12.6 V, Cell voltage monitoring state 130 200 µA ICC4 6 VCC = 6 V, Shutting over-discharge state 0* µA * : Standard design value. 7 MB3836 Power supply current ICC (µ µA) Power Supply Current vs.Power Supply Voltage 200 Ta = +25 °C BATH = VCC H cell voltage = M cell voltage = L cell voltage OUTON = 5 V 180 160 140 Cell voltage monitoring state MSW1 = OPEN MSW2 = 5 V 120 100 80 60 40 Normal state MSW1 = MSW2 = OPEN 20 0 0 2 4 6 8 10 12 14 16 Over-charge detection voltage VTH (V) ■ TYPICAL CHARACTERISTICS Over-charge Detection Voltage vs. Ambient Temperature 4.40 4.38 4.36 4.34 4.32 4.30 Typical H cell OUTON = 5 V BATH = VCC BATM = 8.4 V BATL = 4.2 V 4.28 4.26 4.24 4.22 4.20 −40 −20 Delay time of alarm output tD (s) Delay time tD (ms) 1000 100 10 1 1000 10000 100000 80 100 Ta = +25 °C 10 1 0.1 0.01 0.0001 0.001 0.01 0.1 1 10 Capacitor for setting alarm output time CUVT (µ µF) Delay Time on Over-discharge Detection Block Delay Time of Over-current Detection 100 Ta = +25 °C Delay time tD1, tD2 (ms) Power failure permission signal wait time tD (s) 60 Delay Time on Over-discharge Detection Block Capacitor for setting delay time COVT (pF) 1000 40 100 Ta = +25 °C 0.1 100 20 Ambient temperature Ta (°°C) Power supply voltage VCC (V) Delay Time on Over-charge Detection Block 0 100 tD1 VCC − OCV = 0.5 V Ta = +25 °C 10 10 1 0.1 0.01 0.0001 0.001 0.01 0.1 1 10 Capacitor for setting power failure permission signal wait time CPDT (µ µF) 1 0.1 100 tD2 VCC − OCV = 1 V 1000 10000 Capacitor for setting delay time COCT (pF) (Continued) 8 MB3836 (Continued) Power Dissipation vs. Ambient Temperature Characteristics Power dissipation PD (mW) 600 540 500 400 300 200 100 0 −40 −20 0 20 40 60 80 Ambient temperature Ta (°°C) 100 9 MB3836 ■ FUNCTIONAL DESCRIPTION (1) Over-charge Detection Block When the battery is being charged, the over-charge detection block monitors each cell voltage. If any cell voltage reaches or exceeds the over-charge detection voltage (4.325 V Typ) as in Figure 1 (see "1. Over-charge detection block and cell voltage input block " in "■OPERATION TIMING CHART"), the COUT terminal (pin 2) goes “H” level, after a delay time (23 ms Typ) managed by the capacitor (COVT) connected between the COVT terminal (pin 14) and GND, to turn off the Pch MOS FET for external charge control, thereby stopping charging the battery. When all the cell voltages in the over-charge detected state become the over-charge release voltage (4.125 V Typ) or less, the COUT terminal (pin 2) goes “L” level to turn on the Pch MOS FET for external charge control. Even when a cell voltage reaches or exceeds the over-charge detection voltage as in Figure 2, the cell voltage does not enter the over-charge detected state if it falls below the over-charge detection voltage within the delay time (23 ms Typ). (2) Cell Voltage Input Block If any cell voltage reaches or exceeds the over-charge detection voltage (4.325 V Typ) as in Figures 1 and 2 (see "1. Over-charge detection block and cell voltage input block" in "■OPERATION TIMING CHART"), the COUT terminal (pin 2) goes high to turn off the Pch MOS FET for external charge control after a delay time (23 ms Typ) managed by the capacitor (COVT) connected between the COVT terminal (pin 14) and GND. At the same time, the cell voltage input block switch for the cell exceeding the over-charge detection value is turned on to supply the cell voltage input current to that cell so that high-voltage cells are lowered in voltage. When the cell voltage in the over-charge detected state becomes the over-charge release voltage ( 4.125 V Typ) or less, the cell voltage input block switch is turned off. (3) Over-discharge Detection/Power Fail Circuit Block When the battery is being discharged, the over-discharge detection/power fail circuit block monitors each cell voltage. If any cell voltage becomes the over-discharge detection voltage (2.75 V Typ) as in Figure 5 (see "3. Over-discharge detection/power fail circuit" in "■OPERATION TIMING CHART"), the PF terminal (pin 19) outputs a “L” level PF signal to the notebook PC after a PF output delay time (2 s Typ) managed by the capacitor (CUVT) connected between the CUVT terminal (pin 12) and GND. At the same time, after a power-down delay time (20 s Typ) managed by the capacitor (CPDT) connected between the CPDT terminal (pin 11) and GND, the DOUT terminal (pin 3) goes “H” level to turn off the Pch MOS FET for external discharge control, thereby stopping discharging the battery. (4) Over-current Detection Block The over-current detection block monitors the discharge current from the battery. It detects an over-current if the potential difference between the VCC and OCV terminals by RON of Pch MOS FET for external charge control becomes 300 mV or more as in Figure 6 (see "4. Over-current detection block 1" in "■OPERATION TIMING CHART"). After a delay time (7 ms Typ) managed by the capacitor (COCT) connected between the COCT terminal (pin 13) and GND, the DOUT terminal (pin 3) goes “H” level to turn off the Pch MOS FET for external discharge control, thereby stopping discharging the battery. When the discharge current is large, if the potential difference between the VCC and OCV terminals becomes 600 mV or more as in Figure 7 (see "5. Over-current detection block 2" in "■OPERATION TIMING CHART"), the DOUT terminal (pin 3) goes “H” level to turn off the Pch MOS FET for external discharge control, thereby stopping discharging the battery, after a power-down delay time (500 µs Typ) managed by the capacitor (COCT) connected between the COCT terminal (pin 13) and GND. Note that, if an over-current is detected, the VS terminal (pin 5) goes “L” level in the same way as when the overdischarge detection function works. As discharging is stopped, the OCV terminal (pin 1) goes “L” level to 10 MB3836 completely turn off the bias source of this IC, so that the battery pack enters the power-down state. To return from that state, perform recharging operation, or set the OCV terminal (pin 1) to “H” level. (5) Remote ON Circuit Block When the battery pack is detached from the notebook PC, the OUTON terminal (pin 20) pulled up to the VS terminal (pin 5) on the notebook PC side goes “L” level to turn off the bias of the over-current detection block. At the same time, the COUT terminal (pin 2) and DOUT terminal (pin 3) go “H” level to turn off the Pch MOS FET for external charge/discharge control. Even when the OUTON terminal (pin 20) is “L” level with charging/discharging off, the IC is operating and the over-discharge detection function is working to protect the battery. If the VS terminal (pin 5) is “H” level, connecting the battery pack to the main unit makes it readily available. (6) Cell Voltage Monitor Block The cell to be monitored can be selected depending on the voltage levels at the MSW1 terminal (pin 16) and MSW2 terminal (pin 17). When the monitor function is operating, the cell voltage input block switch does not work even when an over-charge is detected. Condition of monitoring cell voltage Voltage level at MSW1 terminal Voltage level at MSW2 terminal VMON output SW at cell voltage input block L L Depend on over-charge detection block L H H cell voltage Off H L M cell voltage Off H H L cell voltage Off 11 MB3836 ■ SETTING DELAY TIME for OVER-CHARGE DETECTION BLOCK For over-charge detection, you can set the delay time from when charging the capacitor (COVT) connected to the COVT terminal (pin 14) is started and the COVT terminal voltage increases until the COUT terminal (pin 2) voltage goes “H” level (with the open-collector output off) with the COVT terminal at the threshold voltage. Over-charge detection block delay time : tD (s) =: 2.3 × COVT (µF) ■ SETTING PF OUTPUT DELAY TIME For over-discharge detection, you can set the delay time from charging the capacitor (CUVT) connected to the CUVT terminal (pin 12) is started and the CUVT terminal voltage increases until the PF terminal (pin 19) voltage goes “L” level with the CUVT terminal at the threshold voltage. PF output delay time : tD1 (s) =: 13.3 × CUVT (µF) ■ SETTING POWER-DOWN DELAY TIME You can set the delay time from charging the capacitor (CPDT) connected to the CPDT terminal (pin 11) is started after “L” level output to the PF terminal (pin 19) at over-discharge detection and the CPDT terminal voltage increases until the DOUT terminal (pin 3) voltage goes high with the CPDT terminal at the threshold voltage. Power-down delay time : tD2 (s) =: 13.3 × CPDT (µF) After the DOUT terminal goes “H” level to stop overdischarging, the OCV terminal (pin 1) goes “L” level to turn off the entire internal circuitry of the IC so that the circuit current becomes 0 µA. Considering the time constant based on the notebook PC’s capacitor connected to the OCV terminal, the discharge time constant of CPDT terminal is used to prevent recovery (return) and shutdown (power-down) from being repeated in response to variations in battery voltage. The capacitor connected to the OCV terminal on the notebook PC side requires the restriction expressed below based on the value of the capacitor (CPDT) connected to the CPDT terminal. OCV terminal external capacitor : COCV (µF) < 1790 × CPDT (µF) ■ SETTING DELAY TIME for OVER-CURRENT DETECTION BLOCK For over-current detection when 0.6 V (Typ) > VCC - OCV > 0.3 V (Typ), you can set the delay time from when charging the capacitor (COCT) connected to the COCT terminal (pin 13) is started and the COCT terminal voltage increases until the DOUT terminal (pin 3) voltage goes “H” level with the COUT terminal at the threshold voltage. Over-current detection block delay time : tD1 (s) =: 12.5 × COCT (µF) For over-current detection when VCC - OCV > 0.6 V (Typ), you can set the delay time from when charging the capacitor (COCT) connected to the COCT terminal (pin 13) is started and the COCT terminal voltage increases until the DOUT terminal (pin 3) voltage goes “H” level with the COCT terminal at the threshold voltage. Over-current detection block delay time : tD2 (s) =: 0.9 × COCT (µF) 12 MB3836 ■ OPERATION at LOW VOLTAGE If cell voltages cause extreme imbalance or one or more cells enter the short-circuited state (0.6 V Typ) or less, the short-circuit cell detection function sets the COUT terminal (pin 2) to “H” level (with the open-collector output off). If the VCC terminal (pin 6) voltage becomes 4.2 V (Typ) or less, however, the short-circuit cell detection function is disabled, the COUT terminal (pin 2) goes “L” level, enabling 0 V cell charging, with the OCV terminal (pin 1) at a voltage of 1.4 V (Typ) or higher. When VCC is less than 4.2 V, the DOUT terminal (pin 3) is fixed at “H” level. 13 MB3836 ■ OPERATION TIMING CHART 1. Over-charge Detection Block and Cell Voltage Input Block (1) When cell 3 does not exceed VTH and cells 1 and 2 are lowered in voltage by cell voltage input current and self-discharging If any cell voltage reaches or exceeds the over-charge detection voltage (4.325 V Typ), the COUT terminal (pin 2) goes “H” level to turn off the Pch MOS FET for external charge control, after a delay time (23 ms Typ) managed by the capacitor (COVT) connected between the COVT terminal (pin 14) and GND, thereby stopping charging the battery. At this time, the cell voltage input block switch is turned on to supply the cell voltage input current to that cell so that high-voltage cells are lowered in voltage. When all the cell voltages in the over-charge detected state become the over-charge release voltage (4.125 V Typ) or less, the COVT terminal (pin 14) and COUT terminal (pin 2) go “L” level to turn on the Pch MOS FET for external charge control. When any cell voltage in the over-charge detected state becomes the over-charge release voltage (4.125 V Typ) or less, the cell voltage input block switch is turned off. VTH (4.325 V) Cell voltage VH (0.2 V) (4.125 V) Cell 1 Cell voltage input current Cell 2 Cell 1 Cell 2 (45 µA) (0 µA) (45 µA) (0 µA) (6.26 V) COVT terminal COUT terminal tD (23 ms) Figure 1 14 MB3836 (2) When the voltage is lowered by cell voltage input current and self-discharge after pulsed charge Even when a cell voltage reaches or exceeds the over-charge detection voltage (4.325 V Typ), the cell voltage does not enter the over-charge detected state if it falls below the over-charge detection voltage (4.325 V Typ) within the delay time (23 ms Typ) managed by the capacitor (COVT) connected between the COVT terminal (pin 14) and GND. If a cell voltage reaches or exceeds the over-charge detection voltage (4.325 V Typ), the COUT terminal (pin 2) goes “H” level to turn off the Pch MOS FET for external charge control, stopping charging the battery, after a delay time (23 ms Typ) managed by the capacitor (COVT) connected between the COVT terminal (pin 14) and GND. At this time, the cell voltage input block switch is turned on to supply the cell voltage input current to that cell so that high-voltage cells are lowered in voltage. When all the cell voltages in the over-charge detected state become the over-charge release voltage (4.125 V Typ) or less, the COVT terminal (pin 14) and COUT terminal (pin 2) go “L” level to turn on the Pch MOS FET for external charge control. When any cell voltage in the over-charge detected state becomes the over-charge release voltage (4.125 V Typ) or less, the cell voltage input block switch is turned off. VTH (4.325 V) Cell voltage VH (0.2 V) (4.125 V) Cell voltage input current (45 µA) (0 µA) (6.26 V) COVT terminal COUT terminal tD (23 ms) Figure 2 15 MB3836 →"L"→ →"H" after detection of an over-charge (3) When the OUTON terminal changes "H"→ VTH (4.325 V) Cell voltage VH (0.2 V) (4.125 V) Cell voltage input current COVT terminal (45 µA) (0 µA) (6.26 V) COUT terminal OUTON terminal DOUT terminal OCV terminal (0 V) VS terminal (0 V) tD (23 ms) Figure 3 When the OUTON terminal (pin 20) changes from “H” level to “L” level after detection of an over-charge, the DOUT terminal (pin 3) goes “H” level to turn off the Pch MOS FET for external discharge control, thereby setting the OCV terminal (pin 1) to “L” level. When the OUTON terminal (pin 20) changes from “H” level to “L” level after all the cell voltages in the overcharge detected state become the over-charge release voltage (4.125 V Typ) or less, the COUT terminal (pin 2) goes “L” level to turn on the Pch MOS FET for external charge control. When the OCV terminal (pin 1) changes from “L” level to “H” level at this time, the DOUT terminal (pin 3) goes “L” level to turn on the Pch MOS FET for external discharge control. 16 MB3836 2. Over-charge Detection Block, Discharge Detection Block, and Cell Voltage Input Block • When battery is discharged after detection of an over-charge or re-discharged after detection of an over-charge by recharging If a cell voltage reaches or exceeds the over-charge detection voltage (4.325 V Typ), the COUT terminal (pin 2) goes “H” level to turn off the Pch MOS FET for external charge control after a delay time (23 ms Typ) managed by the capacitor (COVT) connected between the COVT terminal (pin 14) and GND. This stops charging the battery and puts it into the over-charge detected state. When a discharge is started in the over-charge detected state, the OCV terminal voltage is lowered by the body diode voltage of the Pch MOS FET for external charge control. When the potential difference between the VCC terminal and OCV terminal (pin 1) becomes 300 mV or more, the COUT terminal (pin 2) goes “L” level to turn on the Pch MOS FET for external charge control and the cell voltage input block switch is turned off at the same time. An over-charge caused by recharging can be detected even with cell voltages remaining above the over-charge release voltage (4.125 V Typ). Discharge start↓ ↓Charge start ↓Discharge start VTH (4.325 V) Cell voltage VH (0.2 V) (4.125 V) Cell voltage input current (45 µA) (0 µA) (6.26 V) COVT terminal COUT terminal OCV terminal (VCC) VTH (VCC − 0.3 V) tD (23 ms) tD (23 ms) Figure 4 17 MB3836 3. Over-discharge Detection/Power Fail Circuit • When no “H” level signal is input to the PDWN terminal after over-discharge detection If any cell voltage becomes the over-discharge detection voltage (2.75 V Typ), the PF terminal (pin 19) outputs a “L” level PF signal to the notebook PC after a PF output delay time (2 s Typ) managed by the capacitor (CUVT) connected between the CUVT terminal (pin 12) and GND. At the same time, after a power-down delay time (20 s Typ) managed by the capacitor (CPDT) connected between the CPDT terminal (pin 11) and GND, the DOUT terminal (pin 3) goes “H” level to turn off the Pch MOS FET for external discharge control, thereby stopping discharging the battery. The VS terminal (pin 5) goes “L” level at this time. As discharging is stopped, the OCV terminal (pin 1) goes “L” level to completely turn off the bias source in the IC. That is, an over-discharge state is detected when a cell voltage does not return to the over-discharge detection voltage (2.75 V Typ) or more within the power-down delay time (20 s Typ), an over-discharge state is detected. When the OCV terminal (pin 1) goes “H” level, the DOUT terminal (pin 3) goes “L” level to turn on the Pch MOS FET for external discharge control and the VS terminal (pin 5) goes “H” level. If the cell voltage remains not exceeding the over-discharge detection voltage (2.75 V Typ) at this time, the PF terminal (pin 19) outputs a “L” level PF signal to the notebook PC again after a PF output delay time (2 s Typ) managed by the capacitor (CUVT) connected between the CUVT terminal (pin 12) and GND. If the cell voltage reaches or exceeds the overdischarge detection voltage (2.75 V Typ) within the power-down delay time (20 s Typ), however, the PF terminal goes “H” level and an over-discharge state is not detected. 18 MB3836 ↓Charge start Cell voltage VTH (2.75 V) (4.9 V) CUVT terminal PF terminal CPDT terminal PDWN terminal (4.9 V) 0V DOUT terminal OCV terminal 0V OUTON terminal 0V VS terminal 0V tD1 (2 s) tD2 (20 s) tD1 (2 s) Internal bias : Off Figure 5 19 MB3836 4. Over-current Detection Block 1 When a discharge current is relatively small as an over-current, if the potential difference between the VCC terminal and OCV terminal (pin 1) by RON of the Pch MOS FET for external charge control becomes 300 mV or more, the capacitor (COCT) connected between the COCT terminal (pin 13) and GND is charged. No overcurrent is detected if the OCV terminal voltage returns to the battery voltage level within the delay time (7 ms Typ). If the potential difference between the VCC terminal and OCV terminal (pin 1) by RON of the Pch MOS FET for external charge control becomes 300 mV or more again, an over-current is detected after a delay time (7 ms Typ) managed by the capacitor (COCT) connected between the COCT terminal (pin 13) and GND. At this time, the DOUT terminal (pin 3) goes “H” level to turn off the Pch MOS FET for external discharge control and the bias source in the IC is completely turned off as well. Recharging can be restarted by setting the OCV terminal (pin 1) to “H” level to set the DOUT terminal (pin 3) to “L” level and VS terminal (pin 5) to “H” level, respectively. ↓Charge start (VCC) OCV terminal VTH (VCC - 0.3 V) VTH (VCC - 0.6 V) 0V (5.8 V) COCT terminal DOUT terminal VS terminal 0V tD (7 ms) Figure 6 20 Internal bias : Off MB3836 5. Over-current Detection Block 2 When a discharge current is relatively large as an over-current, if the potential difference between the VCC terminal and OCV terminal (pin 1) by RON of the Pch MOS FET for external charge control becomes 300 mV or more, the capacitor (COCT) connected between the COCT terminal (pin 13) and GND is charged. No overcurrent is detected if the OCV terminal voltage returns to the battery voltage level within the delay time (7 ms Typ). If the potential difference between the VCC terminal and OCV terminal (pin 1) of the Pch MOS FET for external charge control becomes 600 mV or more, an over-current is detected after a delay time (500 ms Typ) managed by the capacitor (COCT) connected between the COCT terminal (pin 13) and GND. At this time, the DOUT terminal (pin 3) goes “H” level to turn off the Pch MOS FET for external discharge control, both of the VS terminal (pin 5) and OCV terminal (pin 1) go “L” level, and the bias source in the IC is completely turned off as well. Recharging can be restarted by setting the OCV terminal (pin 1) to “H” level to set the DOUT terminal (pin 3) to “L” level and VS terminal (pin 5) to “H” level, respectively. ↓Charge start (VCC) OCV terminal VTH (VCC - 0.3 V) VTH (VCC - 0.6 V) 0V (5.8 V) COCT terminal DOUT terminal VS terminal 0V tD (500 µs) Internal bias : Off Figure 7 21 MB3836 ■ TREATMENT WHEN VOLTAGE MONITOR FUNCTION IS NOT USED When the voltage monitor function is not used, connect the MSW1 terminal (pin 16) and MSW2 terminal (pin 17) to GND by taking their shortest ways and leave the VMON terminal (pin 15) open. MSW2 17 MSW1 16 “Open” VMON 15 When voltage monitor function is not used ■ NOTE ON VS TERMINAL If the battery is charged through the body diode of the internal Pch MOS FET connected to the VS terminal (pin 5), the over-charge protection function cannot be disabled. Be careful not to apply a voltage equal to or higher than the VCC terminal voltage to the VS terminal. ■ NOTE ON ELECTROSTATIC APPLICATION This IC has a built-in function to set ICC to 0 µA in power-down mode to extend the battery life. As a charger is required to return the IC from power-down mode, use meticulous care not to let it malfunction, for example, with applied static electricity. To prevent electrostatic noise from coming into each input pin of the IC, it is advisable to lower impedance, for example, by adding a capacitor. The capacitor used for this purpose should be placed as close to the IC as possible. 22 MB3836 ■ I/O TERMINAL EQUIVALE CIRCUIT [Over-current detection block] OCV 1 VCC 6 300 kΩ 300 kΩ ESD protection element 3 2 kΩ GND 10 COCT 13 [Over-discharge detection/power fail circuit block] [Over-charge detection block] PDWN 18 VCC VCC COUT 2 2 kΩ 1 kΩ CUVT 12 500 kΩ 100 kΩ 2 kΩ 20 kΩ COVT 14 2 kΩ GND GND PF 19 CPDT 11 [Remote ON circuit block] [Cell voltage input block] BATH 7 VCC X1 100 kΩ BATM 8 OCV X1 100 kΩ BATL 20 OUTON 50 Ω 600 Ω 1 MΩ 9 X1 100 kΩ 700 kΩ GND GND 55 VS [Cell voltage monitor block] 17 MSW2 16 MSW1 VCC 15 VMON 100 kΩ 100 kΩ 100 kΩ 100 kΩ GND 23 24 L cell M cell H cell Litium-Ion battery 1 kΩ R3 1 kΩ R2 1 kΩ R1 0.1 µF C1 BATL BATM BATH 9 8 10 GND 100 kΩ 100 kΩ 100 kΩ [Cell voltage input block] ON/OFF 7 VCC Reference voltage source 6 bias ×1 ×1 ×1 + − + − detection block] [Over-charge Decoder 2.75 V (±2%) + − − − 4.325 V (±0.6%) − + − + − + 13 Latch1 Reset (7 ms) (500 µs) Delay circuit 15 16 17 VMON MSW1 MSW2 C9 C10 C11 4700 pF 4700 pF 4700 pF [Cell voltage monitor block] 600 mV 300 mV Latch2 14 COCT COVT C7 C6 560 pF 0.01µF Latch3 Reset M2 COUT bias ON/OFF DOUT 11 CPDT C2 1.5 µF Power down delay time (20 s) [Over-discharge detection/ power fail circuit block] Delay circuit (23 ms) 3 Reset [Over-current detection block] R13 10 kΩ R9 1 MΩ M1 12 600 Ω C13 0.1 µF R6 10 Ω OCV [Remote ON circuit block] 1 CUVT C5 0.15 µF PF output time (2 s) 2 R5 1 MΩ R14 10 kΩ Pch MOS FET for charge control Pch MOS FET for discharge control C14 0.1 µF 100 Ω VS 1 MΩ R4 (+) (G) Note PC side 0.22 µF C12 PDWN 18 PF 19 R8 100 kΩ OUTON 20 R7 5 ZD1 18 V C15 0.1 µF MB3836 ■ APPLICATION EXAMPLE MB3836 ■ PARTS LIST COMPONENT ITEM SPECIFICATION VENDOR PARTS No. M1, M2 FET VDS = −30 V VISHAY SILICONIX Si4425DY ZD1 Diode 200 mW, 18 V ± 7% TOSHIBA 02CZ18-Y C1 C2 C5 C6 C7 C9, C10, C11 C12 C13, C14, C15 Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser 0.1 µF 1.5 µF 0.15 µF 560 pF 0.01 µF 4700 pF 0.22 µF 0.1 µF 25 V (10%) 16 V (10%) 16 V (10%) 50 V (5%) 25 V (10%) 25 V (10%) 25 V (10%) 25 V (10%) R1, R2, R3 R4, R5, R9 R6 R7 R8 R13, R14 Resistor Resistor Resistor Resistor Resistor Resistor 1 kΩ 1 MΩ 10 Ω 100 Ω 100 kΩ 10 kΩ 1/16 W, 5% 1/16 W, 5% 1/16 W, 5% 1/16 W, 5% 1/16 W, 5% 1/16 W, 5% Note: VISHAY SILICONIX : VISHAY Intertechnology, Inc. TOSHIBA : TOSHIBA CORPORATION ■ USAGE PRECAUTION •Printed circuit board ground lines should be set up with consideration for common impedance. •Take appropriate static electricity measures. • Containers for semiconductor materials should have anti-static protection or be made of conductive material. • After mounting, printed circuit boards should be stored and shipped in conductive bags or containers. • Work platforms, tools, and instruments should be properly grounded. • Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ between body and ground. 25 MB3836 ■ ORDERING INFORMATION Part number MB3836PFV 26 Package 20-pin plastic SSOP (FPT-20P-M03) Remarks MB3836 ■ PACKAGE DIMENSION Note 1) *1: Resin protrusion. (Each side: +0.15 (.006) Max). Note 2) *2: These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. 20-pin plastic SSOP (FPT-20P-M03) *1 6.50±0.10(.256±.004) 0.17±0.03 (.007±.001) 11 20 *24.40±0.10 6.40±0.20 (.173±.004) (.252±.008) INDEX Details of "A" part +0.20 1.25 –0.10 +.008 .049 –.004 LEAD No. 1 10 0.65(.026) "A" 0.24±0.08 (.009±.003) 0.10(.004) C (Mounting height) 0.13(.005) M 0~8˚ 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.10±0.10 (Stand off) (.004±.004) 0.25(.010) 2003 FUJITSU LIMITED F20012S-c-4-6 Dimensions in mm (inches). Note: The values in parentheses are reference values. 27 MB3836 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0310 FUJITSU LIMITED Printed in Japan