FUJITSU SEMICONDUCTOR DATA SHEET ASSP DS04-28203-4E Image Processing BIPOLAR A/D Converter (1-channel, 8-bit low-power model with built-in clamp circuit) MB40568 ■ DESCRIPTION The MB40568 is an all-parallel (flash type) A/D converter for 8-bit video applications, and uses high-speed bipolar process technology for low-power consumption and high-speed conversion. This A/D converter is capable of converting analog signals into digital signals at a rate of DC to 20 MSPS (megasamples per second). Additional circuitry including a clamp circuit and reference voltage generator circuits are build in, to make the MB40568 ideally suited for video signal processing. ■ FEATURES • • • • Resolution: 8 bits Linearity error: ±0.15 % typ. Maximum conversion rate: 20 MSPS min. Analog input voltage: 0 to 3 V in 2 VP-P (clamp circuit) 3 to 5 V (without clamp circuit) • Digital input/output level: TTL Levels • Power supply voltage: +5 V single power supply • Power dissipation: 200 mW typ. ■ PACKAGES 22-pin Plastic SK-DIP 24-pin Plastic SOP (DIP-22P-M04) (FPT-24P-M02) MB40568 ■ PIN ASSIGNMENTS (Top view) (Top view) D.GND 1 22 A.GND D.GND 1 24 A.GND D8 (LSB) 2 21 VCCD D8 (LSB) 2 23 VCCD D7 3 20 VCCA D7 3 22 VCCA D6 4 19 VRB D6 4 21 VRB D5 5 18 VINA D5 5 20 VREF D4 6 17 VCLMP D4 6 19 VRM D3 7 16 VOUTC D3 7 18 VINA D2 8 15 VINC D2 8 17 VCLMP 9 14 VCCA 9 16 VOUTC CLK 10 13 VCCD CLK 10 15 VINC D.GND 11 12 A.GND D.GND 11 14 VCCA A.GND 12 13 VCCD D1 (MSB) (DIP-22P-M04) D1 (MSB) (FPT-24P-M02) ■ PIN DESCRIPTIONS Pin no. Symbol Function DIP SOP 1, 11 1, 11 D.GND Ground pin Should be connected to the analog system ground. 2 to 9 2 to 9 D8 to D1 Digital signal output pin 10 10 CLK 12, 22 12, 24 A.GND 13, 21 13, 23 VCCD Power supply voltage input pin Also functions as VCCA power supply, and should be in the same voltage level as VCCA pin. 14, 20 14, 22 VCCA Power supply voltage input pin Also functions as VCCD power supply, and should be in the same voltage level as VCCD pin. 15 15 VINC Clamp circuit input pin The clamp circuit is a diode-clamp type sync chip clamp circuit. Should be shorted to ground if the clamp circuit is not used. 16 16 VOUTC Clock input pin Ground pin Should be connected to the analog system ground. Clamp circuit output pin A capacitor of at least 1 µF should be connected between this pin and the VCLMP pin. Should be left open if the clamp circuit is not used. (Continued) 2 MB40568 (Continued) Pin no. Symbol Function DIP SOP 17 17 VCLMP 18 18 VINA Analog signal input pin 19 — VRB Analog reference voltage pin In the DIP model, this pin is internally connected to the reference circuit. Always be sure that a capacitor is connected immediately next to the IC, between this pin and the ground. The capacitor must be at least 1 µF with excellent frequency characteristics. — 19 VRM Reference voltage monitor pin Set to the midpoint of resistance between VCCA and VRB. Should be left open in normal use. — 20 VREF Reference voltage output pin Should be left open when no reference voltage source is used. — 21 VRB Analog reference voltage input pin When an internal reference voltage source is used, this pin should be shorted to the VREF pin. In this case, always be sure that a capacitor is connected immediately next to the IC, between this pin and the ground. The capacitor must be at least 1 µF with excellent frequency characteristics. When an external reference voltage source is used, this pin will carry a current of up to 8.5 mA, therefore it is necessary to use a voltage source with sufficient sync capacity. A capacitor connection should also be used similar to that used with internal reference voltage sources. Clamp voltage output pin A capacitor of at least 1 µF should be connected between this pin and the VOUTC pin. Should be left open if the clamp circuit is not used. 3 MB40568 ■ BLOCK DIAGRAMS 1. SK-DIP 13 CLK 10 VINA 18 VCCA VCCA 14 20 21 V CCD V CCD R1 1 R 2 9 R 8 127 R/2 R/2 7 Latch & Buffer 255 to 8 Encoder 128 6 5 4 3 2 R R 254 255 R2 VRB 1 19 11 0.6 × VCC 12 4 VINC 15 VOUTC 16 VCLMP 17 D1 (MSB) D2 D3 D4 D5 D6 D7 D8 (LSB) 22 Clamp Circuit 0.6 × VCC + 200 mV Reference D.GND D.GND A.GND A.GND MB40568 2. SOP 13 CLK 10 VINA 18 VCCA VCCA 14 22 23 VCCD VCCD R1 1 R 2 9 R 8 127 VRM 19 R/2 7 Latch & Buffer 255 to 8 R/2 Encoder 128 6 5 4 3 2 R R 1 254 11 D.GND D.GND 255 R2 VRB VREF D1 (MSB) D2 D3 D4 D5 D6 D7 D8 (LSB) 1 12 21 24 20 A.GND A.GND 0.6 × VCC VINC 15 VOUTC 16 VCLMP 17 Clamp Circuit 0.6 × VCC + 200 mV Reference 5 MB40568 ■ ABSOLUTE MAXIMUM RATINGS (See WARNING) Parameter Symbol Rating Unit Power supply voltage VCCA, VCCD –0.5 to +7.0 V Digital input voltage VIND –0.5 to +7.0 V Analog input voltage VINA –0.5 to VCC + 0.5 V Analog reference voltage* VRB –0.5 to VCC + 0.5 V Clamp circuit input voltage VINC –0.5 to VCC + 0.5 V Storage temperature Tstg –55 to +125 °C * : Package : SOP VCCA = 2.0 ± 0.1 V, VRB = 2.0 ± 0.1 V WARNING: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min. Typ. Max. Unit Power supply voltage*1 VCCA, VCCD 4.75 5.00 5.25 V Analog input voltage VINA VRB — VCCA V VRB 2.75 3 3.25 V Clamp circuit input voltage* VINC 0 — 3 V Clamp capacitance CCLMP 1 — — µF Digital high-level output voltage IOH –400 — — µA Digital low-level output voltage IOL — — 1.6 mA Clock pulse width at high-level W+ t 22.5 — — ns Clock pulse width at low-level tW– 22.5 — — ns Operating temperature Top 0 — 70 °C Analog reference voltage*2 3 *1: VCCA and VCCD must be used in the same voltage level. *2: Package : SOP VCCA = 2.0 ± 0.1 V, VRB = 2.0 ± 0.1 V *3: VINC must have an amplitude of VCCA – VCLMP. 6 Value MB40568 ■ ELECTRIC CHARACTERISTICS 1. DC Characteristics (1) Analog DC Characteristics (VCCA = VCCD = 4.75 to 5.25 V, Ta = 0°C to +70°C) Parameter Symbol Value Min. Typ. Max. Unit Remarks Resolution — — — 8 bits Linearity error* LE — ±0.15 ±0.3 % DC Accuracy Equivalent analog input resistance RINA 300 — — kΩ RINA = Analog input capacitance CINA — 40 50 pF fINA = 1MHz Analog high-level input current IIHA — — 45 µA VINA = VCCA Analog low-level input current IILA — — 40 µA VINA = VRB Clamp circuit input current IINC –600 –200 — µA VINC = 0 V SK-DIP22P package VRB 0.6 × VCC –0.1 0.6 × VCC 0.6 × VCC +0.1 V VCLMP — VRB + 0.2 — V IRB –8.5 –5.5 –3.0 mA Reference voltage VREF Clamp voltage Reference current VCCA – VRB IIHA – IILA SOP24P package Short between VREF and VRB SOP24P package * : VCCA = VCCD = 5.00 V, Ta = +25°C (2) Digital DC Characteristics (VCCA = VCCD = 4.75 to 5.25 V, Ta = 0°C to +70°C) Parameter Symbol Value Min. Typ. Max. Unit Remarks Digital high-level output voltage VOH 2.7 — — V IOH = –400 µA Digital low-level output voltage VOL — — 0.4 V IOL = 1.6 mA Digital high-level input voltage VIHD 2.0 — — V Digital low-level input voltage VILD — — 0.8 V Maximum input current IID — — 100 µA VID = 7 V High-level input current IIHD — 0 20 µA VIHD = 2.7 V Digital low-level input current IILD –100 –10 — µA VILD = 0.4 V Power supply current ICC — 40* 85 mA * : VCCA = VCCD = 5.00 V, Ta = +25°C 7 MB40568 2. Switching Characteristics (VCCA = VCCD = 4.75 to 5.25 V, Ta = 0°C to +70°C) Parameter Value Symbol Min. Typ. Max. Unit Maximum conversion rate fS 20 — — MSPS Digital output delay time tpd 8 15 30 ns ■ TIMING DIAGRAM tW + tW – 3V CLK 1.5 V 0V SAMPLEN + 2 SAMPLEN + 1 SAMPLEN VINA tpd VOH D1 to D8 DATAN – 1 VOL 8 DATAN 1.5 V DATAN + 1 MB40568 ■ TYPICAL CHARACTERISTIC CURVES Maximum conversion rate vs. Temperature Power supply current vs. Temperature 70 80 60 VCC = 5.25 V VCC = 5.00 V VCC = 4.75 V 40 20 10 –25 0 25 50 75 Ambient temperature Ta (°C) Maximum conversion rate (MHz) Power supply current ICC (mA) 100 60 50 40 30 20 –25 100 VCC = 5.00 V VRB = 3.00 V VCC = 5.00 V VREF—VRB Short Reference current IRB (mA) Reference voltage VREF (V) 100 10 3.00 2.90 2.80 2.70 –25 0 25 50 75 Ambient temperature Ta (°C) Reference current vs. Temperature Reference voltage vs. Temperature 3.20 3.10 VCC = 5.00 V 0 25 50 75 Ambient temperature Ta (°C) 100 8 6 4 2 0 –25 0 25 50 75 Ambient temperature Ta (°C) 100 (Continued) 9 MB40568 (Continued) Digital low-level output voltage vs. Temperature Digital high-level output voltage vs. Temperature 0.5 Digital low-level output voltage VOL (V) Digital high-level output voltage VOH (V) 5.0 4.0 3.0 2.0 VCC = 4.75 V IOH = –400 µA 1.0 0 –25 0 25 50 75 Ambient temperature Ta (°C) 0.4 0.3 0.2 0.1 0 –25 100 VCC = 4.75 V IOL = 1.6 mA 0 25 50 75 Ambient temperature Ta (°C) 100 Linerity error vs. Temperature Clamp voltage vs. Temperature 3.40 0.4 VCC = 5.00 V VCC = 5.00 V Linearity error LE (%) Clamp voltage VCLMP (V) 3.30 3.20 3.10 0.2 +LE 0 –LE –0.2 3.00 –0.4 2.90 –25 0 25 50 75 Ambient temperature Ta (°C) 100 –25 Digital output delay time vs. Power supply voltage 0 25 50 75 Ambient temperature Ta (°C) 100 Clock pulse width vs. Power supply voltage 10 50 40 Clock pulse width tW (ns) Digital output delay time tpd (ns) Ta = +25°C 30 20 10 0 4.50 tPHL tPLH 4.75 5.0 5.25 Power supply voltage VCC (V) 8 6 tW – 4 t W+ 2 5.50 0 4.50 4.75 5.0 5.25 Power supply voltage VCC (V) 5.50 (Continued) 10 MB40568 (Continued) Clock pulse width vs. Temperature Digital output delay time vs. Temperature 10 VCC = 5.00 V 40 30 tPHL 20 tPLH 10 0 –25 0 25 50 75 Ambient temperature Ta (°C) VCC = 5.00 V 8 Clock pulse width tW (ns) Digital output delay time tpd (ns) 50 6 tW – tW + 4 2 0 -25 100 50 50 40 40 Ta = +70°C Ta = +25°C S/Nq (dB) S/Nq (dB) 30 Ta = 0°C 20 20 VCC = 5.00 V fCLK = 20 MHz Ta = +25°C VCC = 5.00 V fin = 4.0 MHZ 10 0 10 10 20 30 40 50 Clock frequency (MHz) 100 S/Nq (RMS Signal/RMS Noise) vs. Analog input frequency S/Nq (RMS Signal/RMS Noise) vs. Clock frequency 30 0 25 50 75 Ambient temperature Ta (°C) 60 0 0 2 4 6 8 10 Analog input frequency (MHz) 11 MB40568 ■ EQUIVALENT CIRCUIT 1. Analog Input Equivalent Circuit VCCA VCCA VINA VINA VD RINA CINA IBIAS × 255 CIRCUITS A.GND A.GND CINA : Non-linear Emitter-Follower Junction Capacitance RINA : Linear Resistance Model for Input Current Transition by Comparator Switching Infinite value for VINA < VRB or when CLK + High VRB : Voltage at VRB terminal. IBIAS : Constant Input Bias Current VD : The base-collector junction diode of emitter-follower transistor 2. Equivalent Circuit of Clamp Circuit Block VCCA 2 mA 0.6 × VCC + 200 mV + VBE 850 kΩ VINC A.GND VOUTC VCLMP – + CCLMP 12 VRB MB40568 3. Equivalent Circuit of Reference Circuit Block VCCA 20 kΩ Buffer VRB pin IRB 30 kΩ A.GND 4. Digital Input Equivalent Circuit VCCD 50 kΩ 6.5 kΩ 3.2 kΩ 50 kΩ 3.2 kΩ VREF = 1.4 V Clock input D.GND 5. Load Circuit for Output Buffer To output pin Measurement point CL CL = 15 pF D.GND Note: CL = 15 pF including scope and jig capacitance 13 MB40568 ■ LINEARITY ERROR 1. Ideal Conversion Characteristics STEP OUTPUT CODE 255 11111111 254 11111110 253 • • • 129 11111101 • • • 10000001 128 10000000 127 • • • 2 01111111 • • • 00000010 1 00000001 0 00000000 VZT 3.006 V V INA VFT 4.996 V The values for VZT and VFT are typical values under conditions that VCCA = VCCD = 5.000 V and VRB = 3.000 V. 14 MB40568 2. Actual Conversion Characteristics STEP OUTPUT CODE 255 11111111 254 11111110 253 • • • 129 11111101 • • • 10000001 128 10000000 127 • • • 2 01111111 • • • 00000010 1 00000001 0 00000000 LE253 LE129 LE128 LE127 LE2 LE1 VZT VINA VFT LEn max = Linearity error FS 15 MB40568 ■ CLAMP CIRCUIT OPERATION The MB40568’s internal clamp circuit is a peak-detection type circuit, which clamps compound synchronized signals using the lowest sync point as clamp voltage (VCLMP) (see illustration below). The clamp voltage is set at 0.6 × VCC + 0.2 V (typical). If the clamp circuit is not used, the signal pins should be handled as follows: Pin name Description VINC Connect to GND VOUTC Leave open VCLMP Leave open • Clamp Circuit VCCA VCCA 2 mA Bias circuit Video signal VINC 15 A.GND VOUTC CCLMP 16 3.2 V – + VCLMP VINA 17 18 A/D converter (Pin No.: SK-DIP22P) Signal level at VINC pin Signal level at VINA pin VCCA = 5.0 V A.GND 16 VCLMP 3.2 V VRB 3.0 V MB40568 ■ TYPICAL CONNECTION EXAMPLES 1. On-Chip Input PNP Transistor Utilized +5 V +5 V VCCA VCCD 15 VINC Video signal input 16 VOUTC 1µF MB40568 – + 17 VCLMP 18 VINA A.GND D.GND (Pin No.: SK-DIP22P) 17 MB40568 2. Input PNP Transistor of Clamp Circuit is Put Externally +5 V +9 V +5 V External circuit VCCA VCCD 15 VINC 16 VOUTC 2.2 kΩ 17 VCLMP MB40568 – + 18 VINA 1 µF Video signal input 2SA933 A.GND D.GND (Pin No.: SK-DIP22P) 18 MB40568 ■ ORDERING INFORMATION Part number MB40568P-SK MB40568PF Package Remarks 20 pin Plastic SK-DIP (DIP-20P-M04) 24 pin Plastic SOP (FPT-24P-M02) 19 MB40568 ■ PACKAGE DIMENSIONS 20-pin Plastic SK-DIP (DIP-22P-M04) +0.20 27.18 –0.30 1.070 +.008 –.012 INDEX-1 6.60±0.25 (.260±.010) INDEX-2 4.36(.172)MAX 0.51(.020)MIN 3.00(.118)MIN 0.25±0.05 (.010±.002) 0.46±0.08 (.018±.003) +0.50 0.86 –0 .034 +.020 –0 1.27(.050) MAX C 1994 FUJITSU LIMITED D22008S-4C-3 +0.50 1.27 –0 +.020 –0 .050 2.54(.100) TYP 7.62(.300) TYP 15°MAX Dimensions in mm (inches) (Continued) 20 MB40568 (Continued) 24-pin Plastic SOP (FPT-24P-M02) +0.25 +.010 15.24 –0.20 .600 –.008 2.80(.110)MAX 0.05(.002)MIN (STAND OFF) 7.60±0.30 10.20±0.40 (.299±.012) (.402±.016) 9.20±0.30 (.362±.012) 1 PIN INDEX 0.45±0.10 (.018±.004) 1.27(.050)TYP +0.05 Ø0.13(.005) M 0.15 –0.02 +.002 .006 –.001 0.50±0.20(.020±.008) Details of "A" part 0.20(.008) 0.10(.004) "A" 13.97(.550)REF 0.60(.024) 0.18(.007)MAX 0.68(.027)MAX C 1994 FUJITSU LIMITED F24008S-4C-4 Dimensions in mm (inches) 21 MB40568 MEMO 22 MB40568 MEMO 23 MB40568 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete information sufficient for construction purposes is not necessarily given. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. Fujitsu reserves the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu. The information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear control systems or medical equipments for life support. F9702 FUJITSU LIMITED Printed in Japan 24 *DS04-28203