FUJITSU SEMICONDUCTOR DATA SHEET DS04-28310-2E ASSP 1 CHANNEL 10-BIT D/A CONVERTER MB40730 MB40730 is a low-power consumption, high-speed 10-bit D/A converter. The MB40730 is characterized by ECL (10 kH) compatible digital inputs, an analog output voltage from -2 to 0 V, and a maximum conversion rate of 60 MHz. It provides a reference voltage from a potential divider and band-gap reference, and can also use an external reference voltage. 20-PIN PLASTIC DIP The MB40730 D/A converter is suitable for high-resolution TVs or VTRs. • Resolution: 10 bits • Conversion characteristics: -Maximum conversion rate: 60 MHz (Minimum) -Linearity error: ±0.1 % (Maximum) -Differential linearity error: ±0.1 % (Maximum) • Input and output: -Digital input voltage: ECL (10 kH) levels -Analog output voltage: 2 Vp-p (-2 V to 0 V) • Reference voltage: (DIP-20P-M01) -VROUT1: Potential divider circuit (VEEA 2/5.2) -VROUT2: Band-gap reference circuit (-2 V) • - Others: Supply voltage: -5.2 V single power supply Power dissipation: 180 mW (Typical value at analog output voltage 2 Vp-p) 140 mW (Typical value at analog output voltage 1 Vp-p) 20-PIN PLASTIC SOP ABSOLUTE MAXIMUM RATINGS (See NOTE) (VCCA=VCCD=0 V, Ta=+25°C) Parameter Symbol Value Unit Analog power supply voltage VEEA -7.0 to 0 V Digital power supply voltage VEED -7.0 to 0 V VEED-VEEA 1.0 V Digital signal input voltage VID 0 to VEE V Storage Temperature Tstg -55 to +125 °C Power supply voltage difference NOTE: Permanent device damage may occur if the above Absolute Maximum Rating are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. (FPT-20P-M01) This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. 1 MB40730 ■ PIN ASSIGNMENT (TOP VIEW) (MSB) (LSB) D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 CLK VCCD VCCA A.OUT VROUT2 VRIN VROUT1 COMP VEEA VEED (DIP-20P-M01) (FPT-20P-M01) ■ 2 PIN DESCRIPTIONS Pin No. Symbol I/O Description 1 to 10 D1 to D10 I Data signal input pin (D1: MSB, D10: LSB) 20 CLK I Clock signal input pin 19 VCCD - Digital ground pin (0 V) 18 VCCA - Analog ground pin (0 V) 11 VEED - Digital power pin (-5.2 V) 12 VEEA - Analog ground pin (-5.2 V) 15 VRIN I Reference voltage input pin Analog output dynamic range setup pin Connect to pin 14 or 16 to use the built-in reference voltage When using an external reference voltage, the voltage on this pin must be from -2.20 V to -0.70 V 14 VROUT1 O Reference voltage output pin 1 The output voltage of the potential divider reference is fixed at VEEA 2/5.2. When this pin is connected to pin 15, the analog output voltage ranges from VEEA 2/5.2 to 0 V 16 VROUT2 O Reference voltage output pin 2 The output voltage of the band-gap reference is fixed at -2.0 V. When the pin is connected to pin 15, the analog output voltage ranges from -2 V to 0 V 13 COMP - Phase compensation capacitor pin Insert a capacitor of 0.1 µF or greater between VEEA and COMP for phase compensation 17 A. OUT O Analog signal output pin MB40730 ■ BLOCK DIAGRAM CLK A.OUT (MSB) D1 R D2 R 2R D3 R 2R D4 D5 Input Buffer D6 10 Masterslave Flip Flop 10 Buffer 10 Current Switch R 2R R 2R R 2R D7 R 2R D8 R R D9 D10 (LSB) VCCA VCCD Reference Resistor Amplifier Reference Voltage 1 (potential divider reference) Reference Voltage 2 (band-gap reference) VCCA VEED VEEA VROUT1 VROUT2 VRIN COMP 3 MB40730 ■ DIGITAL INPUT EQUIVALENT CIRCUIT VCCD D1 to D10 CLK Threshold voltage = -1.3 V VEED ■ ANALOG OUTPUT EQUIVALENT CIRCUIT VCCA RO = 240 Ω A.OUT IO VEEA ■ REFERENCE VOLTAGE OUTPUT EQUIVALENT CIRCUIT VCCA VCCA 4 kΩ VROUT1 BGR 6 kΩ VEEA + VROUT2 RS * *: Overcurrent-prevention resistor (2 kΩ) for a short to GND. 4 MB40730 ■ TYPICAL CONNECTION EXAMPLE VCCD VCCA A. OUT D1 to D10 DATA Input VROUT2 VRIN VROUT1 COMP CLK Input CLK VEED 0.01 µ Connect to VROUT1, VROUT2 or external reference voltage. 47 µ 0.1 m VEEA 2.2 µ 47 µ 2.2 µ 0.01 µ -5.2 V ■ RECOMMENDED OPERATING CONDITIONS (VCCA=VCCD=0 V, Ta=-20°C to +75°C) Standard value Parameter Symbol Unit Min. Typ. Max. Analog power supply voltage VEEA -5.46 -5.20 -4.94 V Digital power supply voltage VEED -5.46 -5.20 -4.94 V VEEA-VEED -0.2 - 0.2 V VRIN -2.20 -2.00 -0.70 V -20°C - - -0.88 V 25°C -1.13 - -0.81 V 75°C - - -0.735 V -20°C -1.95 - - V 25°C -1.95 - -1.48 V 75°C -1.95 - - V fCLK - - 60 MHz Setup time tsu 8 - - ns Hold time th 2 - - ns Clock minimum pulse width high twH 6.5 - - ns Clock minimum pulse width low twL 6.5 - - ns Phase compensation capacitor CCOMP 0.1 - - µF Top -20 - 75 °C Power supply voltage Power supply voltage difference Analog reference voltage Digital input high voltage Digital input low voltage Clock frequency Operating temperature VIHD VILD 5 MB40730 ■ DC CHARACTERISTICS (VEEA=VEED=-5.46 to -4.94 V, Ta=-20°C to +75°C) Parameter Resolution Linearity error Symbol Condition - - LE Differential linearity error DLE Digital input current high IIHD DC accuracy Standard values Max. Unit Min. Typ. - - 10 bit - - ±0.1 % - - ±0.1 % - - - 5 µA Digital input current low IILD - -0.1 - - µA Reference input current IRIN VRIN=-2.000V - - 10 µA Reference voltage VROUT1 VEEA = -5.20 V VEED = -5.20 V -2.100 -2.000 -1.900 V Reference voltage VROUT2 - -2.100 -2.000 -1.900 V - - - 100 - ppm/°C Full-scale output voltage VOFS - -20 0 - mV Zero-scale output voltage VOZS VEEA = -5.20 V VEED = -5.20 V VRIN = -2.000 V -2.068 -1.998 -1.928 V RO Ta=+25°C 192 240 288 Ω IEE VEEA = -5.46 V VEED = -5.46 V VRIN = VROUT -59 -34* - mA Potential divider reference Band-gap reference Temperature coefficient Output resistance Power dissipation * : VEEA = VEED = -5.20 V ■ AC CHARACTERISTICS (VEEA= VEED=-5.46 to -4.94 V, Ta=-20°C to +75°C) Standard values Parameter Maximum conversion rate FS Output propagation delay time tpd Output rise time tr Output fall time tf Settling time 6 Symbol tset Conditions CL = 15 pF A.OUT pin terminating resistance = 240 Ω Unit Min. Typ. Max. 60 - - MSPS - 7 - ns - 5 - ns - 5 - ns - -17.5 - ns MB40730 ■ TIMING CHART VIHD tsu th -0.9 V Data input -1.3 V VILD -1.7 V twH twL VIHD -0.9 V -1.3 V Clock input -1.7 V VILD +1/2LSB VOFS 90% 90% 50% 50% Analog output 10% 10% +1/2LSB VOZS tr tf tsetLH tPLH tsetHL tPHL 7 MB40730 ■ DAC OUTPUT VOLTAGE CHARACTERISTICS Input Output D1 to D10 A.OUT 1023 0 (VCCA) VOFS 0.000 V 0.000 V VOZS (VRIN) -1.998 V -2.000 V 1 LSB = 2 mV ■ DAC OUTPUT VOLTAGE FORMULA IN IDEAL CONDITIONS 1023 - N (VCCA - VRIN) 1024 (N : Digital input code from 0 to 1023) A.OUT = VCCA - VOFS = VCCA VOZS = VCCA - 1023 1024 (VCCA - VRIN) NOTES 8 1. Preventing Switching Noise To prevent switching noise in the analog output signal, connect noise limiting capacitors to the VEEA and VEED pins as close to the VCCA and VCCD pins as possible. 2. Power Pattern To reduce parasitic impedance, the PC board pattern to the VCCA, VCCD, VEEA and VEED pins should be as wide as possible. MB40730 ■ TYPICAL CHARACTERISTICS CURVES 1. Power Supply Current v.s. Ambient Temperature 2. Linearity Error v.s. Ambient Temperature VEE = -5.46 V VRIN = VROUT1 IEE, Power supply current (mA) VEE = -5.20 V VRIN = -2.000 V 0 0.1 -20 0.08 LEM , -40 Linearity error (%) 0.06 -60 0.04 -80 0.02 0 -100 -25 0 25 50 75 -25 100 Ambient temperature Ta ( °C) 0 25 50 75 100 Ambient temperature Ta ( °C) 3. Differential Linearity Error v.s. Ambient Temperature 4. Output Resistance v.s. Ambient Temperature VEE = -5.20 V VRIN = -2.000 V DLEM , Differential linearity error (%) 0.1 300 0.08 280 0.06 RO, Output resistance (Ω) 260 0.04 240 0.02 220 0 200 -25 0 25 50 75 Ambient temperature Ta ( °C) 100 -25 0 25 50 75 100 Ambient temperature Ta ( °C) 9 MB40730 5. Full-Scale Output Voltage v.s. Ambient Temperature 6. Zero-Scale Output Voltage v.s. Ambient Temperature VEE = -5.20 V VRIN = -2.000 V VEE = -5.20 V VRIN = -2.000 V VCC (Reference) -1.900 -10 VOFS, Full-scale output voltage (mV) -1.950 -20 VOZS, Zero-scale output voltage (V) -30 -2.000 -2.050 -40 -2.100 -50 -25 0 25 50 75 100 -25 Ambient temperature Ta ( °C) VEE = -5.20 V -1.900 -1.950 -1.950 VROUT2, Reference output voltage (V) VROUT1, Reference -2.000 output voltage (V) -2.050 -2.100 -2.100 50 75 Ambient temperature Ta ( °C) 10 75 100 -2.000 -2.050 25 50 VEE = -5.20 V -1.900 0 25 8. VROUT2 Reference Output Voltage v.s. Ambient Temperature 7. VROUT1 Reference Output Voltage v.s. Ambient Temperature -25 0 Ambient temperature Ta ( °C) 100 -25 0 25 50 75 Ambient temperature Ta ( °C) 100 MB40730 9. VROUT2 Reference Output Voltage v.s. Power Supply Voltage 10. Setup Time v.s. Ambient Temperature Ta = 25°C VEE = -5.20 V 10 -1.900 Reference output voltage VROUT2 (V) 8 -1.950 tsu, Setup time (ns) -2.000 6 4 -2.050 2 -2.100 0 -6.5 -6.0 -5.5 -5.0 -4.5 -25 -4.0 11. Setup Time v.s. Power Supply Voltage 50 75 100 12. Hold Time v.s. Ambient Temperature Ta = 25°C VEE = -5.20 V 10 6 8 4 6 2 tn, Hold time (ns) 4 0 2 -2 0 -4 -6.5 25 Ambient temperature Ta ( °C) Power supply voltage VCC (V) tsu, Setup time (ns) 0 -6.0 -5.5 -5.0 -4.5 Power supply voltage VEE (V) -4.0 -25 0 25 50 75 100 Ambient temperature Ta ( °C) 11 MB40730 13. Hold Time v.s. Power Supply Voltage 14. Minimum Clock Pulse Width v.s. Ambient Temperature Ta = 25 °C tn, Hold time (ns) VEE = -5.20 V 6 10 4 8 2 twL/twH, Minimum clock pulse width (ns) 0 6 twL 4 twH 2 -2 0 -4 -6.5 -6.0 -5.5 -5.0 -4.5 -4.0 -25 50 75 100 16. Rise Time / Fall Time v.s. Ambient Temperature 15. Minimum Clock Pulse Width v.s. Power Supply Voltage VEE = -5.20 V VRIN = -2.000 V CL = 15 pF Analog output 240 Ω termination (1 V amplitude) Ta = 25 °C 10 10 8 8 6 tr/tf, Rise time and fall time (ns) 6 4 4 twL 2 2 twH 0 0 -6.5 -6.0 -5.5 -5.0 -4.5 Power supply voltage VEE (V) 12 25 Ambient temperature Ta ( °C) Power supply voltage VEE (V) twL/twH, Minimum clock pulse width (ns) 0 -4.0 -25 0 25 50 75 Ambient temperature Ta ( °C) 100 MB40730 17. Rise Time / Fall Time v.s. Power Supply Voltage Ta = 25 °C VRIN = -2.000 V CL = 15 pF Analog output 240 Ω termination (1 V amplitude) tr/tf, Rise time and fall time (ns) 18. Quantization Noise v.s. Analog Output Frequency 10 70 8 60 6 4 50 S/Nq, Quantization noise (dB) 40 2 30 0 -6.5 fCLK = 15 MHz fCLK = 30 MHz fCLK = 60 MHz 20 -6.0 -5.5 -5.0 -4.5 Power supply voltage VEE (V) -4.0 0 5 10 15 20 25 Analog output frequency fOUT (MHz) 13 MB40730 ■ PACKAGE DIMENSIONS 20-LEAD PLASTIC DUAL IN-LINE PACKAGE (CASE No.: DIP-20P-M01) 15°MAX +.008 +0.20 .970 -.012 (24.64 -0.30 ) INDEX-1 .260±.010 (6.60±0.25) .300(7.62) TYP INDEX-2 +.012 .034 -0 (0.86+0.30 ) -0 .010±.002 +.012 .050 -0 (1.27 +0.30 ) -0 (0.25±0.05) .172(4.36) MAX .118(3.00) MIN .100(2.54) .050(1.27) MAX TYP 1991 FUJITSU LIMITED D20005S-3C 14 .018±.003 (0.46±0.08) .020(0.51) MIN Dimensions in inches (millimeters) MB40730 ■ PACKAGE DIMENSIONS (Continued) 20-LEAD PLASTIC FLAT PACKAGE (CASE No.: FPT-20P-M01) .089(2.25) MAX +0.25 +.010 .500-.008 (12.70 -0.20 ) (MOUNTING HEIGHT) .002(0.05) MIN (STAND OFF HEIGHT) .307±.016 (7.80±0.40) INDEX .209±.012 +0.40 +.016 .268-.008 (6.80 -0.20 ) (5.30±0.30) .020±.008 (0.50±0.20) .050(1.27) TYP .018±.004 (0.45±0.10) ∅.005(0.13) M +.002 +0.05 .006 (0.15 ) -.001 -0.02 Details of “A” part “A” .004(0.10) .450(11.43) REF 1991 FUJITSU LIMITED F20003S-5C .008(0.20) .020(0.50) .007(0.18) MAX .027(0.68) MAX Dimensions in inches (millimeters) 15 MB40730 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 1015, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211, Japan Tel: (044) 754-3753 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. 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