ICST ICS501MLFT Loco pll clock multiplier Datasheet

ICS501
LOCO™ PLL CLOCK MULTIPLIER
Description
Features
The ICS501 LOCOTM is the most cost effective way to
generate a high-quality, high-frequency clock output
from a lower frequency crystal or clock input. The name
LOCO stands for Low Cost Oscillator, as it is designed
to replace crystal oscillators in most electronic
systems. Using Phase-Locked Loop (PLL) techniques,
the device uses a standard fundamental mode,
inexpensive crystal to produce output clocks up to 160
MHz.
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Stored in the chip’s ROM is the ability to generate nine
different multiplication factors, allowing one chip to
output many common frequencies (see table on page
2).
The device also has an output enable pin which
tri-states the clock output when the OE pin is taken low.
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined or guaranteed.
For applications which require defined input to output
skew, use the ICS570B.
Packaged as 8-pin SOIC or die
Available in Pb (lead) free package
ICS’ lowest cost PLL clock
Zero ppm multiplication error
Input crystal frequency of 5 - 27 MHz
Input clock frequency of 2 - 50 MHz
Output clock frequencies up to 160 MHz
Extremely low jitter of 25 ps (one sigma)
Compatible with all popular CPUs
Duty cycle of 45/55 up to 160 MHz
Nine selectable frequencies
Operating voltage of 3.3V or 5.5V
Tri-state output for board level testing
25mA drive capability at TTL levels
Ideal for oscillator replacement
Industrial temperature version available
Advanced, low-power CMOS process
Block Diagram
VDD
S1:0
2
PLL Clock
Multiplier
Circuitry
and ROM
X1/ICLK
Crystal or
Clock input
Crystal
Oscillator
CLK
X2
Optional crystal capacitors
OE
GND
1
MDS 501 K
I n t e gra te d C i r c u i t S y s t e m s
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ICS501
LOCO™ PLL Clock Multiplier
Pin Assignment
Clock Output Table
S1 S0
CLK
Minimum Input
0
0
4X input
per page 4
X1/ I CLK
1
8
X2
0
M
5.3125X input
20 MHz
VDD
2
7
OE
0
1
5X input
per page 4
GND
3
6
S0
M
0
6.25X input
4 MHz
M
M
2X input
per page 4
M
1
3.125X input
8 MHz
1
0
6X input
per page 4
1
M
3X input
per page 4
1
1
8X input
per page 4
S1
5
4
CLK
8 Pi n ( 150 mi l ) SOI C
0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (floating)
Common Output Frequency Examples (MHz)
Output
20
24
30
32
33.33
37.5
40
48
50
60
62.5
Input
10
12
10
16
16.66
12
10
12
16.66
10
20
M, M
M, M
1, M
M, M
M, M
M, 1
0, 0
0, 0
1, M
1, 0
M, 1
Output
64
66.66
72
75
80
83.33
90
100
106.25
120
125
Input
16
16.66
12
12
10
16.66
15
20
20
15
20
Selection (S1, S0)
0, 0
0, 0
1, 0
M, 0
1, 1
0, 1
1, 0
0, 1
0, M
1, 1
M, 0
Selection (S1, S0)
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
1
XI/ICLK
Input
Crystal connection or clock input.
2
VDD
Power
Connect to +3.3 V or +5 V.
3
GND
Power
Connect to ground.
4
S1
Tri-level Iinput
5
CLK
Output
6
S0
Tri-level Input
7
OE
Input
8
X2
Output
Select 1 for output clock. Connect to GND or VDD or float.
Clock output per table above.
Select 0 for output clock. Connect to GND or VDD or float.
Output enable. Tri-states CLK output when low. Internal pull-up.
Crystal connection. Leave unconnected for clock input.
2
MDS 501 K
In te grated Circuit Systems
Pin Description
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ICS501
LOCO™ PLL Clock Multiplier
External Components
Crystal Load Capacitors
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
ICS501 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and the GND. It must be connected
close to the ICS501 to minimize lead inductance. No
external power supply filtering is required for the
ICS501.
Series Termination Resistor
A 33Ω terminating resistor can be used next to the CLK
pin for trace lengths over one inch.
The value (in pF) of these crystal caps should equal
(CL -12 pF)*2. In this equation, CL= crystal load
capacitance in pF. Example: For a crystal with a 16 pF
load capacitance, each crystal capacitor would be 8 pF
[(16-12) x 2] = 8.
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MDS 501 K
In te grat ed Circuit Syst ems
The total on-chip capacitance is approximately 12 pF. A
parallel resonant, fundamental mode crystal should be
used. The device crystal connections should include
pads for small capacitors from X1 to ground and from
X2 to ground. These capacitors are used to adjust the
stray capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors, if
needed, must be connected from each of the pins X1
and X2 to ground.
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525 Ra ce St reet , San Jose, CA 9512 6
Revision 071304
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ICS501
LOCO™ PLL Clock Multiplier
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS501. These ratings, which
are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
7V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature
-40 to +85°C
Storage Temperature
-65 to +150°C
Soldering Temperature
260°C
Recommended Operation Conditions
Parameter
Min.
Max.
Units
0
+70
°C
+3.0
+5.5
V
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Typ.
DC Electrical Characteristics
VDD=5.0 V ±5% , Ambient temperature 0 to +70°C, unless stated otherwise
Parameter
Operating Voltage
Symbol
Conditions
Min.
VDD
Typ.
3.0
Input High Voltage, ICLK only
VIH
ICLK (pin 1)
Input Low Voltage, ICLK only
VIL
ICLK (pin 1)
Input High Voltage
VIH
OE (pin 7)
Input Low Voltage
VIL
OE (pin 7)
Input High Voltage
VIH
S0, S1
Input Low Voltage
VIL
S0, S1
Output High Voltage
VOH
IOH = -25 mA
Output Low Voltage
VOL
IOL = 25 mA
Max.
Units
5.5
V
(VDD/2)+1
V
(VDD/2)-1
2.0
V
V
0.8
VDD-0.5
V
V
0.5
2.4
V
V
0.4
V
IDD Operating Supply Current, 20
No load, 100M
20
mA
Short Circuit Current
CLK output
+70
mA
4
MDS 501 K
In te grat ed Circuit Syst ems
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525 Ra ce St reet , San Jose, CA 9512 6
Revision 071304
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ICS501
LOCO™ PLL Clock Multiplier
Parameter
Symbol
Conditions
On-Chip Pull-up Resistor
Pin 7
Input Capacitance, S1, S0, and OE
Pins 4, 6, 7
Min.
Typ.
Nominal Output Impedance
Max.
Units
270
kΩ
4
pF
20
Ω
AC Electrical Characteristics
VDD = 5.0 V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Symbol
Conditions
Min.
Typ.
Max. Units
Input Frequency, crystal input
FIN
5
27
MHz
Input Frequency, clock input
FIN
2
50
MHz
0°C to +70°C
13
160
MHz
-40°C to +85°C
13
140
MHz
0°C to +70°C
13
100
MHz
-40°C to +85°C
13
90
MHz
Output Frequency, VDD = 4.5 to 5.5 V
Output Frequency, VDD = 3.0 to 3.6 V
FOUT
FOUT
Output Clock Rise Time
tOR
0.8 to 2.0 V, Note 1
1
ns
Output Clock Fall Time
tOF
2.0 to 8.0 V, Note 1
1
ns
Output Clock Duty Cycle
tOD
1.5 V, up to
160 MHz
45
PLL Bandwidth
49-51
10
55
%
kHz
Output Enable Time, OE high to
output on
50
ns
Output Disable Time, OE low to
tri-state
50
ns
+70
ps
25
ps
Absolute Clock Period Jitter
tja
One Sigma Clock Period Jitter
tjs
Deviation from
mean
Note 1: Measured with 15 pF load.
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MDS 501 K
In te grat ed Circuit Syst ems
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525 Ra ce St reet , San Jose, CA 9512 6
Revision 071304
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ICS501
LOCO™ PLL Clock Multiplier
Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches
8
Symbol
E
A
A1
B
C
D
E
e
H
h
L
α
H
INDEX
AREA
1 2
D
A
Min
Max
Min
1.35
1.75
0.10
0.25
0.33
0.51
0.19
0.25
4.80
5.00
3.80
4.00
1.27 BASIC
5.80
6.20
0.25
0.50
0.40
1.27
0°
8°
Max
.0532
.0688
.0040
.0098
.013
.020
.0075
.0098
.1890
.1968
.1497
.1574
0.050 BASIC
.2284
.2440
.010
.020
.016
.050
0°
8°
h x 45
A1
C
-Ce
SEATING
PLANE
B
L
.10 (.004)
C
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
ICS501M
ICS501MT
ICS501MI
ICS501MIT
ICS501MLF
ICS501MLFT
ICS501-DWF
ICS501-DPK
ICS501M
ICS501M
ICS501I
ICS501I
501MLF
501MLF
-
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Die on uncut, probed wafers
Tested die in waffle pack
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
“LF” denotes Pb (lead) free package.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
6
MDS 501 K
In te grat ed Circuit Syst ems
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525 Ra ce St reet , San Jose, CA 9512 6
Revision 071304
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t el (4 08) 297 -1 201
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w w w. i c s t . c o m
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