FUJITSU SEMICONDUCTOR DATA SHEET DS04-13514-2E Linear IC Converter CMOS D/A Converter for Digital Tuning MB40D001 ■ DESCRIPTION The MB40D001 is an 8-bit D/A converter with 12 built-in channels. The 12 sets of analog outputs have built-in OP amps to enable use with large current drive applications. CS (chip select) data input/output format is used to enable connection to a serial bus. A built-in 12-bit I/O expander provides serial <=> parallel conversion (8 of the 12 bits are also used with analog output). The MB40D001 can be adapted for microcontroller port expansion, or replacement of electronic volume control or semi-fixed calibration resistance. Also, the MB40D001 is function- and pin-compatible with the MB88146A, for easy replacement when reducing sysytem operating voltage. ■ FEATURES • • • • • • • • • • Supply voltage 2.7 V to 3.6 V (Power consumption 0.7 mW/ch typ.) Compact package: SSOP-24 R-2R type 8-bit D/A converter with 12 built-in channels Built-in 12-bit I/O expander (8 of 12 bits also used with analog output) Built-in analog amplifier (sink current max. 0.4 mA, source current max. 1.0 mA) Built-in power-on detector circuit (detects VccD power-on, and performs initialization) Separate MCU interface power supply (VccD), OP amp supply (VccA), D/A converter supply VDD Analog output range 0 V to VccA. Serial data input/output operation to maximum of 2.5 MHz (1.5 MHz in cascade operation) CMOS process ■ PACKAGES 24-pin plastic SSOP (FPT-24P-M03) MB40D001 ■ PIN ASSIGNMENT (TOP VIEW) AO1 1 24 GND AO2 2 23 VCCA AO3 3 22 CS AO4 4 21 SO D11/AO5 5 20 SI D10/AO6 6 19 CLK D9/AO7 7 18 D0 D8/AO8 8 17 D1 D7/AO9 9 16 D2 D6/AO10 10 15 D3 D5/AO11 11 14 VCCD D4/AO12 12 13 VDD SSOP-24 (FPT-24P-M03) 2 MB40D001 ■ PIN DESCRIPTION Pin no. Symbol Description 1 to 4 AO1 to AO4 D/A converter analog output pins (VDD-GND output). (Default state: #00 setting level output) 5 to 12 D11/AO5 to D4/AO12 I/O expander parallel I/O pins (VccA/GND output 0.5 VccA/0.2 VccA input), also used as D/A converter analog output pins (VDD - GND output). Pin state is controlled by input data. See “Data Configuration”. (Default state: Input mode, high-impedance state.) 13 VDD*1 14 VCCD*1 MCU interface power supply (Power supply for I/O expander). 15 to 18 D3 to D0 I/O expander parallel I/O pins (VccD/GND output 0.5 VccD/0.2VccD input). Pin state is controlled by input data. See “Data Configuration”. (Default state: Input mode, high-impedance state.) 19 CLK*2 Shift clock input pin. When CS = “L”, SI data is loaded into the shift register at the rise of the shift clock signal. 20 SI*2 Data input pin (serial input pin). Used for 16-bit serial data input. 21 SO Data output pin (serial output pin). First-bit (LSB) data from the 16-bit shift register is output in synchronization with the fall of the shift clock signal. When CS = “H”, this pin is in high impedance state. 22 CS*2 23 VCCA*1 24 GND D/A converter reference power supply pin. Chip select signal input pin. Input to shift registers is enabled when the CS signal falling edges. Shift register contents can be executed when the CS signal rising edges. Analog unit power supply pin (Power supply for the OP amp.). Common GND pin. *1: Be sure that VCCA ≥ VCCD, and that VCCA ≥ VDD. *2: Do not leave this pin in floating state. 3 MB40D001 ■ BLOCK DIAGRAM CS SI SO 16-bit shift resister & controller CLK VCCD DF DF DE DE DD DD DC DC DB DB BA D9 BA D9 I/O expander D8 D7 D8 D7 DF DE D6 D6 D5 CNTL D4 D5 D4 D5 D4 D0 D1 D2 D3 12 Data bus DF D8 DF 8-bit latch DF DF DF + − DF − D8 8-bit latch D8 R - 2R Ladder circuit Ladder circuit + D8 8-bit latch D8 R - 2R − DF 8-bit latch D8 VDD VCCA D8 DF D8 R - 2R R - 2R Ladder circuit Ladder circuit + − GND + 8 AO1 4 AO4 D11/AO5 D4/AO12 MB40D001 ■ DATA CONFIGURATION 1. Data Configuration MSB (last) LSB (first) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Setting data Channel select 2. Channel Select D3 D2 D1 D0 Function 0 0 0 0 Don’t Care/special function 0 0 0 1 AO1 selected 0 0 1 0 AO2 selected to to to to to 1 0 1 1 AO11 selected 1 1 0 0 AO12 selected 1 1 0 1 I/O expander (serial → parallel) 1 1 1 0 I/O expander (parallel → serial) 1 1 1 1 Expander status register (ESR) 5 MB40D001 3. Setting Data • Don’t Care/special function (Channel select = “0000”) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 Analog output voltage level × × × × × × × × 0 0 0 0 Don’t Care to to to to to to to to to to to to Don’t Care × × × × × × × × 1 0 1 1 Don’t Care 0 0 0 0 0 0 0 0 1 1 0 0 GND (all channels) 0 0 0 0 0 0 0 1 1 1 0 0 VDD/256 × 1 (all channels) 0 0 0 0 0 0 1 0 1 1 0 0 VDD/256 × 2 (all channels) to to to to to to to to to to to to to 1 1 1 1 1 1 1 0 1 1 0 0 VDD/256 × 254 (all channels) 1 1 1 1 1 1 1 1 1 1 0 0 VDD/256 × 255 (all channels) × × × × × × × × 1 1 0 1 High impedance (I/O expander state)* × × × × × × × × 1 1 1 0 Reset (state when power is ON) × × × × × × × × 1 1 1 1 Don’t Care ×: Don’t care *: Hi-Z output on all channels of AO5 through AO12 • D/A Converter (Channel select = “0001” to “1100”) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 0 0 0 0 0 0 0 0 0 0 0 0 GND 0 0 0 0 0 0 0 1 0 0 0 0 VDD/256 × 1 0 0 0 0 0 0 1 0 0 0 0 0 VDD/256 × 2 0 0 0 0 0 0 1 1 0 0 0 0 VDD/256 × 3 to to to to to to to to to to to to to 1 1 1 1 1 1 0 1 0 0 0 0 VDD/256 × 253 1 1 1 1 1 1 1 0 0 0 0 0 VDD/256 × 254 1 1 1 1 1 1 1 1 0 0 0 0 VDD/256 × 255 × × × × × × × × 0 0 0 1 High impedance (I/O expander state)* × × × × × × × × 0 0 1 0 Don’t Care to to to to to to to to to to to to Don’t Care × × × × × × × × 1 1 1 1 Don’t Care ×: Don’t care *: Only AO5 through AO12 output is valid 6 Analog output voltage level MB40D001 • I/O Expander [Channel select = “1101”]: Serial → Parallel Conversion Performs parallel conversion of data bits D4 to DF for output on pins D0 to D11. Note that only those pins designated for output in the ESR (expander status register) are output. Shift register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ↓ ↓ D11 D10 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Parallel I/O pins (output state) • I/O Expander [Channel select = “1110”]: Parallel → Serial Conversion Writes data from D0 to D11 pins to bits D4 to DF in the shift register. Data is output to the SO pin on the shift clock (CLK) signal (The first 4 bits output data D0 to D3, so the converted output should be read as data bits 5 through 16.). Note that the data value is “0” for pins designated for output in the ESR (expander status register) as well as analog output pins. Shift register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ↑ ↑ D11 D10 ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Parallel I/O pins (output state) • Expander Status Register [Channel select = “1111”] Shift register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 ↓ ↓ D11 D10 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ESR This register sets the status of each pin. Setting Pin status “0” • Input standby status (Hi-Z output) • D11 to D4 pins used for analog output should be set to “0”. “1” • Output state 7 MB40D001 Note: After power VCCD is turned ON (or after a reset), the state of pins and registers is as follows. Pin State AO1 to AO4 “L” output D11/AO5 to D4/AO12 Hi-Z state (input state) D3 to D0 Hi-Z state (input state) Register State Shift register Bits DF to D8 are “0,” and D7 to D0 are not defined (retain prior state). D/A register All reset to “0”. Parallel output register Not defined (retain prior state). Expander status register (ESR) All reset to “0”. • ESR settings have priority in determining pin states. Switching between input standby state and analog output state is enabled even when the ESR value is “1”. When the ESR value returns to “0”, the pin returns to its previously defined state. In input standby state with AO set for Hi-Z output, the AO output setting can be used for transition to AO output state. 8 MB40D001 ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Conditions VCCA Power supply voltage VCCD Based on GND (Ta = +25°C) VDD Input voltage 1 Vin1 Output voltage 1 Vout1 Input voltage 2 Vin2 Output voltage 2 Vout2 SI, CLK, CS, SO, D0 to D3 D4 to D11 Unit Min. Max. –0.3 +7.0 V –0.3 +7.0 V –0.3 VCCA* V –0.3 VCCD + 0.3 V –0.3 VCCD + 0.3 V –0.3 VCCA + 0.3 V –0.3 VCCA + 0.3 V Power consumption PD — — 250 mW Operating temperature Ta — –20 +85 °C Storage temperature Tstg — –55 +150 °C * : VCCA ≥ VDD WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Conditions VCCA Value Unit Min. Typ. Max. — 2.7 3.0 3.6 V VCCD — 2.7 — 3.6 V VDD VCCA ≥ VDD 2.0 — VCCA V GND — — 0 — V IAL Source current — — 1.0 mA IAH Sink current — — 0.4 mA Oscillation limit output capacity COL — — — 1.0 µF Operation temperature Ta — –20 — +85 °C Power supply voltage Analog output current Note: Data in registers is retained in standby mode (digital supply: VccD voltage, analog supply: GND). WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 9 MB40D001 ■ ELECTRICAL CHARACTERISTIC 1. DC Characteristics (1) Digital section Parameter Symbol Pin name Power supply voltage VCCD Power supply current ICCD Input leak current IILK1 “H” level input voltage VIH1 “L” level input voltage Typ. Max. 2.7 3.0 3.6 V — 0.1 0.35 mA –10 — +10 µA CLK =1 MHz, (Unloaded) CLK, SI, CS Stop Vin = VCCD or GND ICCS Unit Min. — VCCD Standby current Value Conditions –10 — +10 µA — 0.5 × VCCD — — V — — — 0.2 × VCCD V Vin = 0 to VCCD –10 — +10 µA IOH = –0.4 mA VCCD − 0.4 — — V — — 0.4 V Vin = 0 to VCCD VIL1 CLK, SI, CS, D0 to D3 Output high-impedance leakage current IOLK SO “H” level output voltage VOH1 “L” level output voltage VOL1 SO, D0 to D3 IOL = 2.5 mA (2) D/A converter section Parameter Symbol Power supply voltage VDD Power supply current IDD Resolution Res Monotonic increase Rem Nonlinearity error LE Differential linearity error Nonlinearity error: Differential linearity error: Pin name VDD Value Conditions Typ. VDD ≤ VCCA 2.0 3.0 3.6 V VDD ≤ VCCA — 0.7 1.9 mA — 8 — bit — 8 — bit –1.5 — +1.5 LSB –1.0 — +1.0 LSB AO1 to AO12 Unloaded DLE Deviation (error) in input/output curves with respect to an ideal straight line connecting output voltage at “05” and output voltage at “FA”. Deviation (error) in amplification with respect to theoretical increase in amplification per 1-bit increase in digital value. Analog output Max. Ideal line VAOH Nonlinearity error VAOL #05 #FA Note:The value of VAOH and VDD, and the value of VAOL and GND are not necessarily equivalent. 10 Unit Min. Digital setting MB40D001 (3) Operational Amplifier/Analog output section Parameter Power supply voltage Symbol Pin name Value Conditions Typ. Max. 2.7 3.0 3.6 V — 1.0 4.8 mA –10 — +10 µA — 0.5 × VCCA — — V — — — 0.2 × VCCA V VCCA − 0.4 — — V — VCCA VCCA Unit Min. #80 setting (Unloaded) Power supply current ICCA Input leakage current IILK2 “H” level digital input voltage VIH2 “L” level digital input voltage VIL2 “H” level digital output voltage VOH2 IOH = –0.4 mA “L” level digital output voltage VOL2 IOL = 2.5 mA — — 0.4 V Analog output minimum voltage 1 VAOL1 IAL = 0 A #00 setting GND — 0.1 V Analog output minimum voltage 2 VAOL2 IAL = 0.5 mA #00 setting –0.2 GND 0.2 V Analog output minimum voltage 3 VAOL3 IAH = 0.4 mA #00 setting GND — 0.15 V Analog output minimum voltage 4 VAOL4 IAL = 1.0 mA #00 setting –0.3 GND 0.3 V Analog output maximum voltage 1 VAOH1 IAL = 0 A #FF setting VCCA − 0.1 — VCCA V Analog output maximum voltage 2 VAOH2 IAL = 0.5 mA #FF setting VCCA − 0.2 — VCCA V Analog output maximum voltage 3 VAOH3 IAH = 0.4 mA #FF setting VCCA − 0.15 VCCA VCCA + 0.15 V Analog output maximum voltage 4 VAOH4 IAL = 1.0 mA #FF setting VCCA − 0.3 — VCCA V Vin = 0 to VCCA D4 to D11 AO1 to AO12 AO1 to AO12 Note: IAH: Analog output sink current IAL: Analog output source current 11 MB40D001 2. AC Characteristics Parameter Symbol Conditions Clock “L” level pulse width tCKL Clock “H” level pulse width Clock rise time Clock fall time Value Typ. Max. — 200 — — ns tCKH — 200 — — ns tCr — — — 200 ns tCf — — — 200 ns Serial input setup time tSSU — 30 — — ns Serial input hold time tSHD — 60 — — ns Serial output delay time tSOD See “Load condition 1”* 0 120 300 ns CS input setup time tCSU — 100 — — ns CS hold time tCCH — 200 — — ns CS “H” level hold time tCSH — 100 — — ns Data output enable time tSO — — — 200 ns Data output float time tSOZ — — — 200 ns Parallel input setup time tPSU — 30 — — ns Parallel input hold time tPHD — 60 — — ns Parallel output delay time tPOD See “Load condition 1” — 120 300 ns Analog output delay time tAOD See “Load condition 2” — 30 100 µs tR — — — 50 ms ∆VR — –10 — 10 V/µs Power supply rise time Power-on reset non-startup power supply variation * : Cascade connection enabled at 1.5 MHz. Load Conditions • Load condition 1 • Load condition 2 Measurement point CL = 20 pF to 100 pF 12 Unit Min. Measurement point RAL = 10 kΩ CAL = 50 pF MB40D001 • Input/Output Timing (CS method) tCr tCKH tCf CLK tCKL SI tSSU tCSH tSHD tCCH tCSU CS tSO tSOD tSOD tSOZ SO tPSU tPHD D0 ∼ D11 (at input) tPOD D0 ∼ D11 (at output) tAOD AO1 ∼ AO12 90 % 10 % CLK, SI, CS, SO D0 to D3 decision level is 80% and 20% of VccD. D4 to D11 decision level is 80% and 20% of VccA. AO1 to AO12 decision level is 90% and 10% of VccA. 13 MB40D001 ■ DATA INPUT/OUTPUT TIMING (Serial Bus Format) • Timing of D/A Converter Operation, I/O Expander Operation (serial to parallel conversion), and ESR Write Operation. SI CLK D0 1 D1 2 D2 DE 3 DF 15 16 CS AO× D×× SO Data input is enabled at the fall of the CS signal. 16-bit data is input, and executed by shift register command at the rise of CS. In D/A converter operation, analog output selected at the rise of CS is converted. In serial to parallel conversion, digital output selected at the rise of CS is converted. In ESR write operation, data is set in the ESR at the rise of [CS] and used to change pin states. • I/O Expander Operation (parallel to serial conversion) SI CLK D0 1 DF 16 1 2 16 (Parallel to serial conversion command entered) CS D×× Parallel data loaded SO D0 DF (Parallel to serial conversion result output) Data input is enabled at the fall of the CS signal. 16-bit data (parallel to serial conversion command) is input, and commands received at the rise of CS. At the fall of CS the data from parallel input is loaded in the shift register from D4 to DF, and output from the SO pin timed to the fall of the CLK signal. 14 MB40D001 ■ USAGE PRECAUTIONS 1. Preventing Latch-Up A condition known as “latch-up” may occur when the input or output pins of a CMOS IC device are exposed to voltages higher then VCCD or VCCA or lower than GND voltage, or when voltages are applied to the device in excess of rated values for VCCD, VccA, or VDD to GND voltages. Latchup produces a rapid increase in power supply current, and may result in thermal destruction of elements. Users should take sufficient precautions to ensure that absolute maximum ratings are not exceeded at any time during use. 2. Power Supply Pins The power supply should be connected to the VCCD, VCCA, VDD, and GND terminals of the IC with as low an impedance as possible. In addition, it is recommended that ceramic capacitors of approximately 0.1 µF be connected as bypass capacitors between the VCCD, VCCA, and VDD terminals and the GND terminals. ■ ORDERING INFORMATION Part number MB40D001PFV Package Remarks 24-pin Plastic SSOP (FPT-24P-M03) 15 MB40D001 ■ PACKAGE DIMENSIONS 24-pi plastic SSOP (FPT-24P-M03) *: These dimensions do not include resin protrusion. +0.20 * 7.75±0.10(.305±.004) 1.25 –0.10 +.008 .049 –.004 (Mounting height) 0.10(.004) * 5.60±0.10 INDEX 0.65±0.12(.0256±.0047) (.220±.004) +0.10 C 16 1994 FUJITSU LIMITED F24018S-2C-2 6.60(.260) NOM "A" +0.05 0.22 –0.05 0.15 –0.02 +.004 –.002 .006 –.001 .009 7.15(.281)REF 7.60±0.20 (.299±.008) Details of "A" part +.002 0.10±0.10(.004±.004) (STAND OFF) 0 10° 0.50±0.20 (.020±.008) Dimension in mm (inches) MB40D001 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ F0001 FUJITSU LIMITED Printed in Japan All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. 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