Fairchild GTLP6C817MTC Low drive gtlp-to-lvttl 1:6 clock driver Datasheet

Revised August 1999
GTLP6C817
Low Drive GTLP-to-LVTTL 1:6 Clock Driver
General Description
Features
The GTLP6C817 is a low drive clock driver that provides
TTL to GTLP signal level translation (and vice versa). The
device provides a high speed interface between cards
operating at TTL logic levels and a backplane operating at
GTLP logic levels. High speed backplane operation is a
direct result of GTLP’s reduced output swing (<1V),
reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time.
GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver logic (GTL) JEDEC standard JESD8-3.
■ Interface between TTL and GTLP logic levels
Fairchild’s GTLP has internal edge-rate control and is process, voltage, and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output LOW level is
typically less than 0.5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.
■ Edge Rate Control to minimize noise on the GTLP port
■ Power up/down high impedance for live insertion
■ 1:6 fanout clock driver for LVTTL port
■ 1:2 fanout clock driver for GTLP port
■ LVTTL compatible driver and control inputs
■ 5V over voltage tolerance on LVTTL ports
■ Flow through pinout optimizes PCB layout
■ Open drain on GTLP to support wired-or connection
■ Recommended Operating Temperature −40°C to +85°C
Ordering Code:
Order Number
GTLP6C817MTC
Package Number
MTC24
Package Description
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Descriptions
Pin Names
Connection Diagram
Description
TTLIN, GTLPIN Clock Inputs (TTL and GTLP respectively)
OEB
Output Enable (Active LOW)
GTLP Port (TTL Levels)
OEA
Output Enable (Active LOW)
TTL Port (TTL Levels)
VCCT.GNDT
LVTTL Output Supplies (3V)
VCC
Internal Circuitry VCC (5V)
GNDG
OBn GTLP Output Grounds
VREF
Voltage Reference Input
OA0–OA5
TTL Buffered Clock Outputs
OB0–OB1
GTLP Buffered Clock Outputs
© 1999 Fairchild Semiconductor Corporation
DS500246
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GTLP6C817 Low Drive GTLP-to-LVTTL 1:6 Clock Driver
June 1999
GTLP6C817
Functional Description
The GTLP6C817 is a low drive clock driver providing LVTTL-to-GTLP clock translation, and GTLP-to-LVTTL clock translation in the same package. The LVTTL-to-GTLP direction is a 1:2 clock driver path with a single Enable pin (OEB). For the
GTLP-to-LVTTL direction the clock receiver path is a 1:6 buffer with a single Enable control (OEA). Data polarity is inverting
for both directions.
Truth Tables
Inputs
TTLIN
Outputs
OBn
OEB
H
L
L
L
L
H
X
H
High Z
Inputs
Outputs
GTLPIN
OEA
OAn
H
L
L
L
L
H
X
H
High Z
Logic Diagram
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2
Supply Voltage (VCC)
−0.5V to +7.0V
DC Input Voltage (VI)
−0.5V to +7.0V
Recommended Operating
Conditions (Note 3)
Supply Voltage
DC Output Voltage (VO)
Outputs 3-STATE
−0.5V to +7.0V
Outputs Active (Note 2)
−0.5V to +7.0V
24 mA
DC Output Source Current
from OA-Port IOH
80 mA
0.98V to 1.02V
0.0V to 5.5V
−12 mA
OA-Port
LOW Level Output Current (IOL)
−50 mA
+12 mA
OA-Port
+40 mA
OB-Port
−50 mA
VO > VCC
+50 mA
ESD Rating
> 2000V
Storage Temperature (TSTG)
1.47V to 1.53V
VREF
and Control Pins
DC Output Diode Current (IOK)
VO < 0V
GTLP
HIGH Level Output Current (IOH)
DC Input Diode Current (IIK)
VI < 0V
3.15V to 3.45V
Input Voltage (VI) on INA-Port
−24 mA
DC Output Sink Current into
OB-Port in the LOW State IOL
4.75V to 5.25V
Bus Termination Voltage (VTT)
DC Output Sink Current into
OA-Port IOL
VCC
VCCT
−40°C to +85°C
Operating Temperature (TA)
Note 1: Absolute Maximum continuous ratings are those values beyond
which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability.
Functional operation under absolute maximum rated conditions is not
implied.
−65°C to +150°C
Note 2: Io Absolute Maximum Rating must be observed.
Note 3: Unused input must be held HIGH or LOW.
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GTLP6C817
Absolute Maximum Ratings(Note 1)
GTLP6C817
DC Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (unless otherwise noted).
Symbol
VIH
VIL
Test Conditions
Min
Typ
(Note 4)
VREF + 0.05
GTLPIN
Others
2.0
GTLPIN
0.0
VTT
VREF − 0.05
Others
0.8
VREF
GTLP
1.0
(Note 5)
GTL
0.8
VTT
GTLP
1.5
(Note 5)
GTL
1.2
VCC = 4.75V
VIK
VCCT = 3.15V
VOH
VOL
VOL
II
IOFF
IOZH
IOZL
OAn-Port
OAn-Port
OBn-Port
Max
II = −18 mA
VCC = 4.75V
IOH = −100 µA
IOH = −6 mA
2.4
IOH = −12 mA
2.2
V
V
V
VCC− 0.2
V
VCC = 4.75V
IOL = 100 µA
0.2
VCCT = 3.15V
IOL = 6 mA
0.4
IOL = 12 mA
0.5
VCC = 4.75V
IOL = 100 µA
0.2
VCCT = 3.15V
IOL = 40 mA
0.5
TTLIN/
VCC = 5.25V
VI = 5.25V
5
Control Pins
VCCT = 3.45V
VI = 0V
−5
GTLPIN
VCC = 5.25V
VI = VTT
5
VCCT = 3.45V
VI = 0
−5
VI or VO = 0V to 5.25V
30
VI or VO = 0 to VTT
30
TTLIN, OAn-Port, Control Pins VCC = 0
V
V
−1.2
VCCT = 3.15V
Units
GTLPIN, OBn-Port
VCCT = 0
OAn-Port
VCC = 5.25V
VO = 5.25V
5
OBn-Port
VCCT = 3.45V
VO = 1.5V
5
OAn-Port
VCC = 5.25V
VO = 0
OBn-Port
VCCT = 3.45V
VO = 0
V
V
µA
µA
µA
µA
−5
µA
µA
IPU/PD
All Ports
VCC = VCCT = 0 to 1.5V OE = Don’t Care
30
ICC (5V)
OAn or
VCC = 5.25V
Outputs HIGH
10
OBn Ports
VCCT = 3.45V
Outputs LOW
10
Outputs Disabled
10
mA
VI = VCC or GND
ICC (3V)
OAn or
VCC = 5.25V
Outputs HIGH, LOW
45
OBn Ports
VCCT = 3.45V
Outputs Disabled
45
µA
1
mA
pF
VI = VCC or GND
∆ICC
TTLIN
VCC = 5.25V
VCCT = 3.45V
VI = VCC−2.1
CIN
Control Pins/GTLPIN/TTLIN
VI = VCC or 0
3
3.5
COUT
OAn-Port
VI = VCC or 0
3
4.5
OBn-Port
VI = VCC or 0
4
5
pF
Note 4: All typical values are at VCC = 5.0V VCCT = 3.3V and TA = 25°C.
Note 5: GTLP VREF and VTT are specified to 2% tolerance since signal integrity and noise margin can be significantly degraded if these supplies are noisy.
In addition, VTT and RTERM can be adjusted to accommodate backplane impedances other than 50Ω, within the boundaries of not exceeding the DC Absolute IOL ratings. Similarly VREF can be adjusted to compensate for changes in V TT.
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Over recommended range of supply voltage and operating free air temperature. VREF = 1.0V (unless otherwise noted).
CL = 30 pF for OBn-Port and CL = 50 pF for OAn-Port.
Typ
Symbol
From (Input)
To (Output)
Min
Max
Units
(Note 6)
tPLH
TTLIN
OBn
2.3
4.7
1.5
4.6
ns
tPHL
OEB
tPLH
OBn
2.4
4.8
1.6
4.7
ns
tPHL
tRISE
Transition Time, OB Outputs (20% to 80%)
1.7
ns
tFALL
Transition Time, OB outputs (20% to 80%)
2.1
ns
tRISE
Transition Time, OA outputs (10% to 90%)
2.7
ns
tFALL
Transition Time, OA outputs (10% to 90%)
2.2
tPZH, tPZL
OEA
OAn
ns
2.4
6.5
2.0
6.5
ns
tPLZ, tPHZ
tPLH
GTLPIN
OAn
3.1
6.6
2.8
6.0
ns
tPHL
Note 6: All typical values are at VCC = 5.0V and TA = 25°C.
Extended Electrical Characteristics
Over recommended ranges of supply voltage and operating free-air temperature VREF = 1.0V (unless otherwise noted).
CL = 30 pF for B Port and CL = 50 pF for A Port.
Symbol
From
To
(Input)
(Output)
Min
Typ
(Note 7)
Max
Unit
ns
tOSLH
(Note 8)
A
B
.05
.4
tOSHL
(Note 8)
A
B
.05
.4
tPS
(Note 9)
0.5
1.0
ns
tPV(HL)
(Note 10)
.7
ns
(Note 11)
A
B
A
B
tOSLH
(Note 8)
B
A
.12
.5
tOSHL
(Note 8)
B
A
.12
.5
tOST
(Note 8)
B
A
.6
1.0
ns
tPS
(Note 9)
B
A
0.5
1.0
ns
tPV
(Note 10)
B
A
1.2
ns
ns
Note 7: All typical values are at VCC = 5.0V and TA = 25°C.
Note 8: tOSHL/tOSLH and tOST - Output-to-Output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs
within the same packaged device. The specifications are given for specific worst case VCC and temperature and apply to any outputs switching in the same
direction either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH) or in opposite directions both HL and LH (tOST). This parameter is guaranteed by design and
statistical process distribution. Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the
device.
Note 9: tPS - Pin or Transition skew is defined as the difference between the LOW-to-HIGH transition and the HIGH-to-LOW transition on the same pin. The
parameter is measured across all the outputs of the same chip is specified for a specific worst case VCC and temperature. This parameter is guaranteed by
design and statistical process distribution. Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance
seen by the device.
Note 10: tPV - Part-to-Part skew is defined as the absolute value of the difference between the actual propagation design for all outputs from device-todevice. The parameter is specified for a specific worst case VCC and temperature. This parameter is guaranteed by design and statistical process distribution. Actual skew values between the GTLP output could vary on the backplane due to the loading and impedance seen by the device.
Note 11: Due to the open drain structure on GTLP outputs, tOST and tPV(LH) in the A-to-B direction are not specified. Skew on these paths is dependent on
the VTT and RT values in the actual application.
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GTLP6C817
AC Electrical Characteristics
GTLP6C817
Test Circuit and Timing Waveforms
Test Circuit for B Outputs
Test Circuit for A Outputs
Note A: CL includes probes and jig capacitance.
Note A: CL includes probes and jig capacitance.
Note B: For B Port CL = 30 pF is used for worst case.
Voltage Waveform - Propagation Delay Times
Voltage Waveform - Enable and Disable Times
Output Waveform 1 is for an output with internal conditions such that the
output is LOW except when disabled by the control output
Output Waveforms 2 is for an output with internal conditions such that the
output is HIGH except when disabled by the control output
Input and Measure Conditions
A or LVTTL
Pins
B or GTLP
Pins
VinHIGH
VCC
1.5
VinLOW
0.0
0.0
VCC/2
1.0
VM
VX
VOL + 0.3V
N/A
VY
VOH + 0.3V
N/A
All input pulses have the following characteristics: Frequency = 10MHz, tRISE = tFALL = 2 ns, ZO = 50Ω.
The outputs are measured one at a time with one transition per measurement.
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GTLP6C817 Low Drive GTLP-to-LVTTL 1:6 Clock Driver
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC24
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
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1. Life support devices or systems are devices or systems
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