Catalyst CAT24C0A1GWETE13 1k-bit serial eeprom Datasheet

CAT24C01B
1K-Bit Serial EEPROM
FEATURES
■ 2-Wire Serial Interface
■ 1,000,000 Program/Erase Cycles
■ 1.8 to 6.0Volt Operation
■ 100 Year Data Retention
■ Low Power CMOS Technology
■ 8-pin DIP, 8-pin SOIC, 8 pin TSSOP or 8-pin MSOP
■ 4-Byte Page Write Buffer
■ Commercial, Industrial and Automotive
Temperature Ranges
■ Self-Timed Write Cycle with Auto-Clear
DESCRIPTION
t
r
a
P
■ "Green" Package Options Available
The CAT24C01B is a 1K-bit Serial CMOS EEPROM
internally organized as 128 words of 8 bits each. Catalyst’s
advanced CMOS technology substantially reduces device power requirements. The CAT24C01B features a
4-byte page write buffer. The device operates via a 2wire serial interface and is available in 8-pin DIP, 8-pin
SOIC, 8-pin TSSOP or 8-pin MSOP.
PIN CONFIGURATION
BLOCK DIAGRAM
SOIC Package (J, W, GW)
DIP Package (P, L, GL)
1
2
3
4
NC
NC
NC
VSS
8
7
6
5
VCC
TEST
SCL
SDA
NC
NC
VSS
1
2
3
4
8
7
6
5
VCC NC
TEST NC
SCL
NC
SDA VSS
is
D
NC
VCC
TEST
SCL
SDA
it
n
u
n
VCC
VSS
SDA
TSSOP Package (U, Y, GY)
PIN FUNCTIONS
Pin Name
8
7
6
5
o
c
MSOP Package (R, Z, GZ)
NC
1
2
3
4
NC
NC
NC
VSS
1
2
3
4
d
e
EXTERNAL LOAD
8
7
6
5
WORD ADDRESS
BUFFERS
XDEC
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
No Connect
Serial Data/Address
SCL
Serial Clock
VCC
+1.8V to +6.0V Power Supply
VSS
Ground
TEST
Test Input (GND, VCC or
Floating)
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
E2PROM
EEPROM
CONTROL
LOGIC
Function
SDA
COLUMN
DECODERS
START/STOP
LOGIC
VCC
TEST
SCL
SDA
SENSE AMPS
SHIFT REGISTERS
DOUT
ACK
SCL
1
STATE COUNTERS
Doc. No. 1081, Rev. E
CAT24C01B
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) .................................. 1.0W
t
r
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Min
Max
Reference Test Method
1,000,000
Cycles/Byte
MIL-STD-883, Test Method 1033
NEND(3)
Endurance
TDR(3)
Data Retention
100
Years
VZAP(3)
ESD Susceptibility
2000
Volts
ILTH(3)(4)
Latch-up
100
mA
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
Symbol
ICC
ISB
Min
o
c
Input Leakage Current
ILO
Output Leakage Current
VIL
Input Low Voltage
s
i
D
Input High Voltage
d
e
Typ
MIL-STD-883, Test Method 3015
JEDEC Standard 17
u
n
Limits
MIL-STD-883, Test Method 1008
Max
Units
Test Conditions
3
mA
fSCL = 100 KHz
1
µA
VIN = GND or VCC
10
µA
VIN = GND to VCC
10
µA
VOUT = GND to VCC
–1
VCC x 0.3
V
VCC x 0.7
VCC + 0.5
V
Standby Current (VCC = 5.0V)
ILI
VIH
it
n
Parameter
Power Supply Current
(5)
a
P
Units
VOL1
Output Low Voltage (VCC = 3.0V)
0.4
V
IOL = 3 mA
VOL2
Output Low Voltage (VCC = 1.8V)
0.5
V
IOL = 1.5 mA
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol
Test
Max
Units
Conditions
CI/O(3)
Input/Output Capacitance (SDA)
8
pF
VI/O = 0V
CIN(3)
Input Capacitance (A0, A1, A2, SCL, WP)
6
pF
VIN = 0V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(5) Maximum standby current (ISB ) = 10µA for the Automotive and Extended Automotive temperature range.
Doc. No. 1081, Rev. E
2
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24C01B
A.C. CHARACTERISTICS
VCC = +1.8V to +6.0V, CL=1TTL Gate and 100pF (unless otherwise specified).
Read & Write Cycle Limits
Symbol
Parameter
1.8V, 2.5V
Min
Max
4.5V-5.5V
Min
Max
FSCL
Clock Frequency
100
400
TI(1)
Noise Suppression Time
Constant at SCL, SDA Inputs
100
100
tAA
SCL Low to SDA Data Out
and ACK Out
3.5
tBUF(1)
Time the Bus Must be Free Before
a New Transmission Can Start
tHD:STA
Start Condition Hold Time
tLOW
Clock Low Period
4.7
tHIGH
Clock High Period
4
tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
tHD:DAT
Data In Hold Time
tSU:DAT
Data In Setup Time
tR(1)
SDA and SCL Rise Time
tF
(1)
it
n
Stop Condition Setup Time
tDH
Data Out Hold Time
o
c
s
i
D
tPUR
tPUW
Write Cycle Limits
0.6
d
e
1.2
0.6
u
n
0
tSU:STO
Symbol
4
4.7
SDA and SCL Fall Time
Power-Up Timing(1)(2)
1.2
250
0.6
t
r
kHz
ns
a
P
1
4.7
Units
µs
µs
µs
µs
µs
µs
0
ns
100
ns
1
0.3
µs
300
300
ns
4.7
0.6
µs
100
100
ns
Parameter
Max
Units
Power-up to Read Operation
1
ms
Power-up to Write Operation
1
ms
Symbol
Parameter
tWR
Write Cycle Time
Min
Typ
Max
Units
10
ms
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its input.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. 1081, Rev. E
CAT24C01B
FUNCTIONAL DESCRIPTION
SDA: Serial Data/Address
The CAT24C01B bidirectional serial data/address pin is
used to transfer data into and out of the device. The SDA
pin is an open drain output and can be wired with other
open drain or open collector outputs.
The CAT24C01B uses a 2-wire data transmission protocol. The protocol defines any device that sends data to
the bus to be a transmitter and any device receiving data
to be a receiver. Data transfer is controlled by the Master
device which generates the serial clock and all START
and STOP conditions for bus access. The CAT24C01B
operates as a Slave device. Both the Master and Slave
devices can operate as either transmitter or receiver, but
the Master device controls which mode is activated.
2-WIRE BUS PROTOCOL
(1) Data transfer may be initiated only when the bus is
not busy.
PIN DESCRIPTIONS
Figure 1. Bus Timing tF
tHIGH
tLOW
tHD:STA
tLOW
tHD:DAT
it
n
SDA IN
tAA
SDA OUT
o
c
Figure 2. Write Cycle Timing
is
D
SDA
8TH BIT
BYTE n
d
e
tR
SCL
tSU:STA
a
P
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
SCL: Serial Clock
The CAT24C01B serial clock input pin is used to clock
all data transfers into or out of the device. This is an input
pin.
SCL
t
r
The following defines the features of the 2-wire bus
protocol:
u
n
tSU:DAT
tDH
tSU:STO
tBUF
5020 FHD F03
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
5020 FHD F04
Figure 3. Start/Stop Timing
SDA
SCL
5020 FHD F05
START BIT
Doc. No. 1081, Rev. E
STOP BIT
4
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24C01B
START Condition
(with the R/W bit set to zero) to the Slave device. After the
Slave generates an acknowledge, the Master sends the
byte address that is to be written into the address pointer
of the CAT24C01B. After receiving another acknowledge from the Slave, the Master device transmits the
data byte to be written into the addressed memory
location. The CAT24C01B acknowledge once more and
the Master generates the STOP condition, at which time
the device begins its internal programming cycle to
nonvolatile memory. While this internal cycle is in
progress, the device will not respond to any request from
the Master device.
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24C01B monitors the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
The CAT24C01B responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8bit byte.
When the CAT24C01B is in a READ mode it transmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this acknowledge, the CAT24C01B will continue to transmit data. If
no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
it
n
o
c
WRITE OPERATIONS
Byte Write
a
P
The CAT24C01B writes up to 4 bytes of data in a single
write cycle, using the Page Write operation. The Page
Write operation is initiated in the same manner as the
Byte Write operation, however instead of terminating
after the initial word is transmitted, the Master is allowed
to send up to 3 additional bytes. After each byte has been
transmitted the CAT24C01B will respond with an acknowledge, and internally increment the low order address bits by one. The high order bits remain unchanged.
d
e
u
n
If the Master transmits more than 4 bytes prior to sending
the STOP condition, the address counter ‘wraps around,’
and previously transmitted data will be overwritten.
Once all 4 bytes are received and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point all received data is written to
the CAT24C01B in a single write cycle.
Note: Catalyst Semiconductor does program all "1" data
into the entire memory array prior to shipping our
EEPROM products.
In the Byte Write mode, the Master device sends the
START condition and the slave address information
s
i
D
t
r
Page Write
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
5020 FHD F06
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. 1081, Rev. E
CAT24C01B
ing with an acknowledge and by issuing a stop condition.
Refer to Figure 7 for the start word address, read bit,
acknowledge and data transfer sequence.
Acknowledge Polling
The disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation, the CAT24C01B initiates the internal write
cycle. ACK polling can be initiated immediately. This
involves issuing the start condition followed by the byte
address for a write operation. If the CAT24C01B is still
busy with the write operation, no ACK will be returned.
If the CAT24C01B has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.
Sequential Read
The Sequential READ operation can be initiated after
the 24C01B sends the initial 8-bit byte requested, the
Master will respond with an acknowledge which tells the
device it requires more data. The CAT24C01B will
continue to output an 8-bit byte for each acknowledge
sent by the Master. The operation is terminated when
the Master fails to respond with an acknowledge, thus
sending the STOP condition.
READ OPERATIONS
The READ operation for the CAT24C01B is initiated in
the same manner as the write operation with the one
exception that the R/W bit is set to a one. Two different
READ operations are possible: Byte READ and Sequential READ.
It should be noted that the ninth clock cycle of the read
operation is not a "don't care." To terminate a read
operation, the master must either issure a stop condition
during the ninth cycle or hold SDA HIGH during the ninth
clock cycle and then issue a stop condition.
it
n
Byte Read
To initiate a read operation, the master sends a start
condition followed by a seven bit word address and a
read bit. The CAT24C01B responds with an acknowledge and then transmits the eight bits of data. The read
operation is terminated by the master; by not respond-
o
c
s
i
D
Figure5. Byte Write Timing
BUS ACTIVITY:
SDA LINE
d
e
u
n
S
T
A
WORD
R ADDRESS(n)
T
S
T
O
P
S
P
BUS ACTIVITY:
M
S
B
t
r
a
P
The data being transmitted from the CAT24C01B is
output sequentially with data from address N followed by
data from address N+1. The READ operation address
counter increments all of the CAT24C01B address bits
so that the entire memory array can be read during one
operation. If more than bytes are read out, the counter
will “wrap around” and continue to clock out data bytes.
LRA
S / C
BW K
DATA n
A
C
K
Figure 6. Page Write Timing
BUS ACTIVITY:
SDA LINE
BUS ACTIVITY:
Doc. No. 1081, Rev. E
S
T
A
R
T
WORD
ADDRESS(n)
DATA n
S
T
O
P
DATA n+3
DATA n+1
P
S
M
S
B
LRA
S / C
BW K
A
C
K
6
A
C
K
A
C
K
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24C01B
Figure 7. Byte Read Timing
S
T
A
WORD
R ADDRESS(n)
T
BUS ACTIVITY
MASTER
SDA LINE
S
T
O
P
DATA n
P
S
LRA
S / C
BW K
M
S
B
BUS ACTIVITY
CAT24C01B
Figure 8. Sequential Read Timing
A
C
K
A
C
K
BUS ACTIVITY
MASTER ADDRESS
R A
/ C
WK
DATA n
DATA n+1
ORDERING INFORMATION
Prefix
it
n
Device #
Suffix
24C01B
CAT
Optional
Company ID
o
c
Product Number
24C01B: 1K
s
i
D
J
A
C
K
d
e
SDA LINE
BUS ACTIVITY
CAT24C01B
t
r
A
C
K
u
n
DATA n+2
-1.8
I
Temperature Range
Blank = Commercial (0°C to 70°C)
I = Industrial (-40°C to 85°˚C)
A = Automotive (-40°C to 105°C)
E = Extended (-40°C to 125°C)
Package
P: PDIP
J: SOIC, JEDEC
U: TSSOP
R: MSOP
L: PDIP (Lead-free, Halogen-free)
W: SOIC (Lead-free, Halogen-free)
Y: TSSOP (Lead-free, Halogen-free)
Z: MSOP (Lead-free, Halogen-free)
GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating)
GW: SOIC (Lead-free, Halogen-free, NiPdAu lead plating)
GY: TSSOP (Lead-free, Halogen-free, NiPdAu lead plating)
GZ: MSOP (Lead-free, Halogen-free, NiPdAu lead plating)
a
P
S
T
O
P
P
DATA n+x
Rev A(2)
TE13
Tape & Reel
Operating Voltage
Blank: 2.5V - 6.0V
1.8: 1.8V - 6.0V
Die Revision
Notes:
(1) The device used in the above example is a 24C01BJI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating
Voltage, Tape & Reel)
(2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g. AYWWA). For additional
information, please contact your Catalyst sales office.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc. No. 1081, Rev. E
REVISION HISTORY
Date
04/17/2004
Revision Comments
B
Update Ordering Information
Update Rev. Number
7/7/2004
C
Added die revision to Ordering Information
08/03/05
E
Update Ordering Information
DPP ™
AE2 ™
it
n
MiniPot™
d
e
u
n
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
t
r
a
P
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
o
c
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
s
i
D
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.caalyst-semiconductor.com
Publication #:
Revison:
Issue date:
1081
E
08/03/05
Similar pages