Cypress CY7C1012DV33 12-mbit (512k x 24) static ram Datasheet

CY7C1012DV33
12-Mbit (512K X 24) Static RAM
Functional Description
Features
■
High speed
❐ tAA = 8 ns
■
Low active power
❐ ICC = 225 mA at 8 ns
■
Low CMOS standby power
❐ ISB2 = 25 mA
■
Operating voltages of 3.3 ± 0.3V
■
2.0V data retention
■
Automatic power down when deselected
■
TTL compatible inputs and outputs
■
Available in Pb-free standard 119-Ball PBGA
The CY7C1012DV33 is a high performance CMOS static RAM
organized as 512K words by 24 bits. Each data byte is separately
controlled by the individual chip selects (CE1, CE2, and CE3).
CE1 controls the data on the IO0 – IO7, while CE2 controls the
data on IO8 – IO15, and CE3 controls the data on the data pins
IO16 – IO23. This device has an automatic power down feature
that significantly reduces power consumption when deselected.
Writing the data bytes into the SRAM is accomplished when the
chip select controlling that byte is LOW and the write enable input
(WE) input is LOW. Data on the respective input and output (IO)
pins is then written into the location specified on the address pins
(A0 – A18). Asserting all of the chip selects LOW and write enable
LOW writes all 24 bits of data into the SRAM. Output enable (OE)
is ignored while in WRITE mode.
Data bytes are also individually read from the device. Reading a
byte is accomplished when the chip select controlling that byte
is LOW and write enable (WE) HIGH, while output enable (OE)
remains LOW. Under these conditions, the contents of the
memory location specified on the address pins appear on the
specified data input and output (IO) pins. Asserting all the chip
selects LOW reads all 24 bits of data from the SRAM.
The 24 IO pins (IO0 – IO23) are placed in a high impedance state
when all the chip selects are HIGH or when the output enable
(OE) is HIGH during a READ mode. For more information, see
the Truth Table on page 8.
Logic Block Diagram
512K x 24
ARRAY
COLUMN
DECODER
IO0 – IO7
SENSE AMPS
A(9:0)
ROW DECODER
INPUT BUFFER
IO8 – IO15
IO16 – IO23
CONTROL LOGIC
CE1, CE2, CE3
WE
OE
A(18:10)
Cypress Semiconductor Corporation
Document Number: 38-05610 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 10, 2007
CY7C1012DV33
Selection Guide
–8
Maximum Access Time
Unit
8
ns
Maximum Operating Current
225
mA
Maximum CMOS Standby Current
25
mA
Pin Configurations
Figure 1. 119-Ball PBGA (Top View) [1]
1
2
3
4
5
6
7
A
NC
A
A
A
A
A
NC
B
NC
A
A
CE1
A
A
NC
C
IO12
NC
CE2
NC
CE3
NC
IO0
D
IO13
VDD
VSS
VSS
VSS
VDD
IO1
E
IO14
VSS
VDD
VSS
VDD
VSS
IO2
F
IO15
VDD
VSS
VSS
VSS
VDD
IO3
G
IO16
VSS
VDD
VSS
VDD
VSS
IO4
H
IO17
VDD
VSS
VSS
VSS
VDD
IO5
J
NC
VSS
VDD
VSS
VDD
VSS
NC
K
IO18
VDD
VSS
VSS
VSS
VDD
IO6
L
IO19
VSS
VDD
VSS
VDD
VSS
IO7
M
IO20
VDD
VSS
VSS
VSS
VDD
IO8
N
IO21
VSS
VDD
VSS
VDD
VSS
IO9
P
IO22
VDD
VSS
VSS
VSS
VDD
IO10
R
IO23
A
NC
NC
NC
A
IO11
T
NC
A
A
WE
A
A
NC
U
NC
A
A
OE
A
A
NC
Note
1. NC pins are not connected on the die.
Document Number: 38-05610 Rev. *C
Page 2 of 10
CY7C1012DV33
Maximum Ratings
Current into Outputs (LOW) ........................................ 20 mA
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage............. ...............................>2001V
Storage Temperature ................................. –65°C to +150°C
Latch Up Current ..................................................... >200 mA
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Operating Range
(MIL-STD-883, Method 3015)
Supply Voltage on VCC Relative to GND [2] ....–0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State [2] .................................. –0.5V to VCC + 0.5V
DC Input Voltage
[2]
Range
Ambient
Temperature
VCC
Commercial
0°C to +70°C
3.3V ± 0.3V
............................... –0.5V to VCC + 0.5V
DC Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions [3]
–8
Min
VOH
Output HIGH Voltage
VCC = Min, IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min, IOL = 8.0 mA
Unit
Max
2.4
V
0.4
V
VIH
Input HIGH Voltage
2.0
VCC + 0.3
V
VIL[2]
Input LOW Voltage
–0.3
0.8
V
IIX
Input Leakage Current
GND < VI < VCC
–1
+1
µA
IOZ
Output Leakage Current
GND < VOUT < VCC, output disabled
–1
+1
µA
ICC
VCC Operating Supply
Current
VCC = Max, f = fMAX = 1/tRC
IOUT = 0 mA CMOS levels
225
mA
ISB1
Automatic CE Power Down Max VCC, CE > VIH
VIN > VIH or VIN < VIL, f = fMAX
Current —TTL Inputs
30
mA
ISB2
Automatic CE Power Down Max VCC, CE > VCC – 0.3V,
Current —CMOS Inputs
VIN > VCC – 0.3V, or VIN < 0.3V, f = 0
25
mA
Notes
2. VIL (min) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns.
3. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE1, CE2 , and CE3 LOW. When HIGH, CE indicates the CE1 ,CE2 , or CE3
is HIGH.
Document Number: 38-05610 Rev. *C
Page 3 of 10
CY7C1012DV33
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
CIN
Input Capacitance
COUT
IO Capacitance
Test Conditions
Max
Unit
TA = 25°C, f = 1 MHz, VCC = 3.3V
8
pF
10
pF
119-Ball
PBGA
Unit
20.31
°C/W
8.35
°C/W
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
ΘJA
Thermal Resistance
(junction to ambient)
ΘJC
Thermal Resistance
(junction to case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch,
four layer printed circuit board
AC Test Loads and Waveforms
The AC test loads and waveform diagram follows. [4]
50Ω
OUTPUT
Z0 = 50Ω
R1 317 Ω
3.3V
VTH = 1.5V
OUTPUT
30 pF*
R2
351Ω
5 pF*
*Including jig
and scope
(a)
*Capacitive Load consists of all
components of the test environment
3.0V
GND
(b)
All input pulses
90%
10%
90%
10%
Fall Time:> 1V/ns
Rise Time > 1V/ns
(c)
Note
4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). 100µs (tpower) after reaching the minimum operating
VDD, normal SRAM operation begins including reduction in VDD to the data retention (VCCDR, 2.0V) voltage.
Document Number: 38-05610 Rev. *C
Page 4 of 10
CY7C1012DV33
AC Switching Characteristics
Over the Operating Range [5]
Parameter
Description
–8
Min
Max
Unit
Read Cycle
tpower [6]
VCC(Typical) to the First Access
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
tDOE
tLZOE
ns
CE Active LOW to Data Valid [3]
8
ns
OE LOW to Data Valid
5
ns
OE LOW to Low Z
3
[7]
ns
1
[7]
OE HIGH to High Z
CE Active LOW to Low Z [3, 7]
tPD
8
ns
tLZCE
tPU
µs
8
tHZOE
tHZCE
100
ns
5
CE Deselect HIGH to High Z
[3, 7]
CE Active LOW to Power Up
[3, 8]
CE Deselect HIGH to Power Down
3
ns
5
0
[3, 8]
ns
ns
ns
8
ns
Write Cycle [9, 10]
tWC
Write Cycle Time
[3]
8
ns
6
ns
tSCE
CE Active LOW to Write End
tAW
Address Setup to Write End
6
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Setup to Write Start
0
ns
tPWE
WE Pulse Width
6
ns
tSD
Data Setup to Write End
5
ns
tHD
Data Hold from Write End
0
ns
3
ns
tLZWE
tHZWE
WE HIGH to Low Z
[7]
WE LOW to High Z
[7]
5
ns
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use
output loading as shown in part a) of AC Test Loads and Waveforms, unless specified otherwise.
6. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed.
7. tHZOE, tHZCE, tHZWE, tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±200
mV from steady state voltage.
8. These parameters are guaranteed by design and are not tested.
9. The internal write time of the memory is defined by the overlap of CE1 or CE2 or CE3 LOW and WE LOW. Chip enables must be active and WE must be LOW to initiate
a write. The transition of any of these signals terminate the write. The input data setup and hold timing are referenced to the leading edge of the signal that terminates
the write.
10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 38-05610 Rev. *C
Page 5 of 10
CY7C1012DV33
Data Retention Characteristics
Over the Operating Range
Parameter
Conditions [3]
Description
Min
Typ
Max
Unit
25
mA
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR [11]
Chip Deselect to Data Retention Time
0
ns
tR [12]
Operation Recovery Time
tRC
ns
2
V
VCC = 2V, CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
Data Retention Waveform
DATA RETENTION MODE
VCC
3.0V
3.0V
VDR > 2V
tCDR
tR
CE
Switching Waveforms
Figure 2. Read Cycle No. 1 [13, 14]
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 3. Read Cycle No. 2 (OE Controlled) [3, 14, 15]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
tHZCE
tLZOE
DATA OUT
HIGH IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
50%
50%
ICC
ISB
Notes
11. Tested initially and after any design or process changes that may affect these parameters.
12. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 µs or stable at VCC(min) > 50 µs.
13. Device is continuously selected. OE, CE = VIL.
14. WE is HIGH for read cycle.
15. Address valid before or similar to CE transition LOW.
Document Number: 38-05610 Rev. *C
Page 6 of 10
CY7C1012DV33
Switching Waveforms
(continued)
Figure 4. Write Cycle No. 1 (CE Controlled) [3, 16, 17]
tWC
ADDRESS
tSCE
CE
tSCE
tSA
tHA
tAW
tPWE
WE
tSD
DATA IO
tHD
DATA VALID
Figure 5. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [3, 16, 17]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
OE
tSD
tHZOE
DATA IO
tHD
DATAIN VALID
NOTE 18
Figure 6. Write Cycle No. 3 (WE Controlled, OE LOW) [3, 17]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
tSD
DATA IO
NOTE 18
tHD
DATA VALID
tHZWE
tLZWE
Notes
16. Data IO is high impedance if OE = VIH.
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
18. During this period, the IOs are in output state. Do not apply input signals.
Document Number: 38-05610 Rev. *C
Page 7 of 10
CY7C1012DV33
Truth Table
CE1
CE2
CE3
OE
WE
Mode
Power
H
H
H
X
X
High Z
High Z
High Z
Power Down
Standby (ISB)
L
H
H
L
H
Data Out
High Z
High Z
Read
Active (ICC)
H
L
H
L
H
High Z
Data Out
High Z
Read
Active (ICC)
H
H
L
L
H
High Z
High Z
Data Out
Read
Active (ICC)
L
L
L
L
H
Full Data Out
Full Data Out
Full Data Out
Read
Active (ICC)
L
H
H
X
L
Data In
High Z
High Z
Write
Active (ICC)
H
L
H
X
L
High Z
Data In
High Z
Write
Active (ICC)
H
H
L
X
L
High Z
High Z
Data In
Write
Active (ICC)
L
L
L
X
L
Full Data In
Full Data In
Full Data In
Write
Active (ICC)
L
L
L
H
H
High Z
High Z
High Z
Selected,
Active (ICC)
Outputs Disabled
Document Number: 38-05610 Rev. *C
IO0 – IO7
IO8 – IO15
IO16 – IO23
Page 8 of 10
CY7C1012DV33
Ordering Information
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
8
CY7C1012DV33-8BGXC
51-85115
119-Ball Plastic Ball Grid Array (14 x 22 x 2.4 mm) (Pb-Free)
Commercial
Package Diagram
Figure 7. 119-Ball PBGA (14 x 22 x 2.4 mm)
51-85115-*B
Document Number: 38-05610 Rev. *C
Page 9 of 10
CY7C1012DV33
Document History Page
Document Title: CY7C1012DV33 12-Mbit (512K X 24) Static RAM
Document Number: 38-05610
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
250650
See ECN
SYT
New datasheet
*A
469517
See ECN
NXR
Converted from Advance Information to Preliminary
Corrected typo in the Document Title
Removed –10 and –12 speed bins from product offering
Changed J7 Ball of BGA from DNU to NC
Removed Industrial Operating range from product offering
Included the Maximum ratings for Static Discharge Voltage and Latch Up Current on
page 3
Changed ICC(Max) from 220 mA to 150 mA
Changed ISB1(Max) from 70 mA to 30 mA
Changed ISB2(Max) from 40 mA to 25 mA
Specified the Overshoot specification in footnote 1
Updated the Truth Table
Updated the Ordering Information table
*B
499604
See ECN
NXR
Added note 1 for NC pins
Changed ICC specification from 150 mA to 185 mA
Updated Test Condition for ICC in DC Electrical Characteristics table
Added note for tACE, tLZCE, tHZCE, tPU, tPD, and tSCE in AC Switching Characteristics
Table on page 4
*C
1462585 See ECN
VKN
Converted from preliminary to final
Updated block diagram
Changed ICC specification from 185 mA to 225 mA
Updated thermal specs
Description of Change
© Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
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as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
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integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05610 Rev. *C
Revised September 10, 2007
All product and company names mentioned in this document are the trademarks of their respective holders.
Page 10 of 10
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