Fairchild MM74HC540WM Inverting octal 3-state buffer octal 3-state buffer Datasheet

Revised May 2005
MM74HC540 • MM74HC541
Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
General Description
Features
The MM74HC540 and MM74HC541 3-STATE buffers utilize advanced silicon-gate CMOS technology. They possess high drive current outputs which enable high speed
operation even when driving large bus capacitances.
These circuits achieve speeds comparable to low power
Schottky devices, while retaining the advantage of CMOS
circuitry, i.e., high noise immunity, and low power consumption. Both devices have a fanout of 15 LS-TTL equivalent
inputs.
■ Typical propagation delay: 12 ns
■ 3-STATE outputs for connection to system buses
■ Wide power supply range: 2–6V
■ Low quiescent current: 80 PA maximum (74HC Series)
■ Output current: 6 mA
The MM74HC540 is an inverting buffer and the
MM74HC541 is a non-inverting buffer. The 3-STATE control gate operates as a two-input NOR such that if either G1
or G2 are HIGH, all eight outputs are in the high-impedance state.
In order to enhance PC board layout, the MM74HC540 and
MM74HC541 offers a pinout having inputs and outputs on
opposite sides of the package. All inputs are protected from
damage due to static discharge by diodes to VCC and
ground.
Ordering Code:
Order Number
Package Number
MM74HC540WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC540SJ
MM74HC540MTC
MM74HC540N
MTC20
N20A
Package Description
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
MM74HC541WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74HC541SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC541MTC
MM74HC541N
MTC20
N20A
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
MM74HC541
Top View
MM74HC540
© 2005 Fairchild Semiconductor Corporation
DS005341
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MM74HC540 • MM74HC541 Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
September 1983
MM74HC540 • MM74HC541
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
(Note 2)
Supply Voltage (VCC)
DC Input Voltage (VIN )
DC Output Voltage (VOUT)
Clamp Diode Current (ICD)
DC Output Current, per pin (IOUT)
0.5 to 7.0V
1.5 to VCC 1.5V
0.5 to VCC 0.5V
r20 mA
r35 mA
Supply Voltage (VCC)
Storage Temperature Range (TSTG)
(VIN, VOUT)
Operating Temperature Range (TA)
r70 mA
65qC to 150qC
(Note 3)
600 mW
S.O. Package only
500 mW
V
85
qC
2.0V
1000
ns
VCC
4.5V
500
ns
VCC
6.0V
400
ns
Note 3: Power Dissipation temperature derating — plastic “N” package: 12 mW/qC from 65qC to 85qC.
260 qC
DC Electrical Characteristics
Parameter
(Note 4)
VCC
Conditions
TA
25qC
Typ
TA
40 to 85qC TA 55 to 125qC
Guaranteed Limits
Units
Minimum HIGH Level
2.0V
1.5
1.5
1.5
V
Input Voltage
4.5V
3.15
3.15
3.15
V
6.0V
4.2
4.2
4.2
V
Maximum LOW Level
2.0V
0.5
0.5
0.5
V
Input Voltage
4.5V
1.35
1.35
1.35
V
6.0V
1.8
1.8
1.8
V
Minimum HIGH Level
VIN
Output Voltage
|IOUT| d 20 PA
VIH or VIL
2.0V
2.0
1.9
1.9
1.9
V
4.5V
4.5
4.4
4.4
4.4
V
6.0V
6.0
5.9
5.9
5.9
V
|IOUT| d 6.0 mA
4.5V
4.2
3.98
3.84
3.7
V
|IOUT| d 7.8 mA
6.0V
5.7
5.48
5.34
5.2
V
VIN
VIH or VIL
Maximum LOW Level
VIN
Output Voltage
|IOUT| d 20 PA
VIH or VIL
2.0V
0
0.1
0.1
0.1
V
4.5V
0
0.1
0.1
0.1
V
6.0V
0
0.1
0.1
0.1
V
|IOUT| d 6.0 mA
4.5V
0.2
0.26
0.33
0.4
V
|IOUT| d 7.8 mA
6.0V
0.2
0.26
0.33
0.4
V
VIN
VCC or GND
6.0V
r0.1
r1.0
r1.0
PA
Maximum 3-STATE
VIN
VIH or VIL, G
6.0V
r0.5
r5
r10
PA
Output Leakage
VOUT
6.0V
8.0
80
160
PA
VIN
IIN
VCC
Note 2: Unless otherwise specified all voltages are referenced to ground.
(Soldering 10 seconds)
VOL
0
40
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Lead Temperature (TL)
VOH
V
(tr, tf) VCC
Power Dissipation (PD)
VIL
Units
6
Input Rise or Fall Times
per pin (ICC)
VIH
Max
2
DC Input or Output Voltage
DC VCC or GND Current,
Symbol
Min
Maximum Input
VIH or VIL
Current
IOZ
VIH
VCC or GND
Current
ICC
Maximum Quiescent
VIN
Supply Current
IOUT
VCC or GND
0 PA
Note 4: For a power supply of 5V r10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
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2
MM74HC540 • MM74HC541
AC Electrical Characteristics
VCC
5V, TA
25qC, tr
tf 6 ns
Symbol
tPHL, tPLH
Parameter
Conditions
Maximum Propagation
Guaranteed
Typ
Limit
Units
CL
45 pF
12
18
ns
CL
45 pF
14
20
ns
Maximum Output Enable
RL
1 k:
17
28
ns
Time
CL
45 pF
Maximum Output Disable
RL
1 k:
15
25
ns
Time
CL
5 pF
Delay (540)
tPHL, tPLH
Maximum Propagation
Delay (541)
tPZH, tPZL
tPHZ, tPLZ
AC Electrical Characteristics
VCC
2.0V to 6.0V, CL
Symbol
50 pF, tr
tf 6 ns (unless otherwise specified)
Parameter
Conditions
VCC
TA
25qC
Typ
TA
40 to 85qC TA 55 to 125qC
Units
Guaranteed Limits
tPHL, tPLH Maximum Propagation
CL
50 pF
2.0V
55
100
126
149
Delay (540)
CL
150 pF
2.0V
83
150
190
224
ns
CL
50 pF
4.5V
12
20
25
30
ns
CL
150 pF
4.5V
22
30
38
45
ns
CL
50 pF
6.0V
11
17
21
25
ns
tPHL, tPLH Maximum Propagation
Delay (541)
tPZH, tPZL Maximum Output Enable
Time
tPHZ, tPLZ Maximum Output Disable
Time
tTHL, tTLH Maximum Output Rise
CL
150 pF
6.0V
18
26
32
38
ns
CL
50 pF
2.0V
58
115
145
171
ns
CL
150 pF
2.0V
83
165
208
246
ns
CL
50 pF
4.5V
14
23
29
34
ns
CL
150 pF
4.5V
17
33
42
49
ns
CL
50 pF
6.0V
11
20
25
29
ns
6.0V
14
28
35
42
ns
ns
CL
150 pF
RL
1 k:
CL
50 pF
2.0V
75
150
189
224
CL
150 pF
2.0V
100
200
252
298
ns
CL
50 pF
4.5V
15
30
38
45
ns
CL
150 pF
4.5V
30
40
50
60
ns
CL
50 pF
6.0V
13
26
32
38
ns
CL
150 pF
6.0V
17
34
43
51
ns
RL
1 k:
2.0V
75
150
189
224
ns
CL
50 pF
4.5V
15
30
38
45
ns
6.0V
13
26
32
38
ns
CL
50 pF
2.0V
25
60
75
90
ns
and Fall Time
CPD
CIN
ns
4.5V
7
12
15
18
ns
6.0V
6
10
13
15
ns
Power Dissipation
G
VIH
10
Capacitance (Note 5)
G
VIL
50
Maximum Input
pF
pF
5
10
10
10
pF
15
20
20
20
pF
Capacitance
COUT
Maximum Output Capacitance
Note 5: CPD determines the no load dynamic power consumption, PD
IS CPD VCC f ICC.
CPD VCC2f ICC VCC, and the no load dynamic current consumption,
3
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MM74HC540 • MM74HC541
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
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4
MM74HC540 • MM74HC541
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
5
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MM74HC540 • MM74HC541
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
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6
MM74HC540 • MM74HC541 Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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