FUJITSU MB84VP24491HK

TM
SPANSION MCP
Data Sheet
September 2003
TM
This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and
Fujitsu. Although the document is marked with the name of the company that originally developed the specification,
these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION
revisions will occur when appropriate, and changes will be noted in a revision summary.
TM
product. Future routine
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION
solutions.
TM
memory
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50225-2E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM
CMOS
128M (×16) FLASH MEMORY &
32M (×16) Mobile FCRAMTM
MB84VP24491HK-70
■ FEATURES
• Power Supply Voltage of 2.7 V to 3.1 V
• High Performance
20 ns maximum page read access time, 70 ns maximum random access time (Flash)
20 ns maximum page read access time, 70 ns maximum random access time (FCRAM)
• Operating Temperature
–30 °C to +85 °C
• Package 73-ball FBGA
(Continued)
■ PRODUCT LINEUP
Flash
Supply Voltage (V)
VCCf* = 3.0 V
FCRAM
+0.1V
–0.3 V
VCCr* = 3.0 V +0.1V
–0.3 V
Max Random Address Access Time (ns)
70
70
Max Page Address Access Time (ns)
20
20
Max CE Access Time (ns)
70
70
Max OE Access Time (ns)
20
40
*: Both VCCf and VCCr must be the same level when either part is being accessed.
■ PACKAGE
73-ball plastic FBGA
(BGA-73P-M03)
MB84VP24491HK-70
(Continued)
— FLASH MEMORY
• 0.13 µm Process Technology
• Dual Chip Enable (CE0f, CE1f)
CE0f controls 64M bits (Bank A and Bank B) region and CE1f controls 64M bits (Bank C and Bank D) bits region.
• Single 3.0 V Read, Program and Ease
Minimized system level power requirements
• Simultaneous Read/Write Operations (Dual Bank)
• FlexBankTM *1
Bank A(CE0f): 16 Mbit (4 KW ×8 and 32 KW ×31)
Bank B(CE0f): 48 Mbit (32 KW ×96)
Bank C(CE1f): 48 Mbit (32 KW ×96)
Bank D(CE1f): 16 Mbit (4 KW ×8 and 32 KW ×31)
• High Performance Page Mode
20 ns maximum page access time (70 ns random access time)
• 8 words Page Access Capability
• Minimum 100,000 Program/Erase Cycles
• Sector Erase Architecture
Eight 4 Kwords, two hundred fifty-four 32 Kwords, eight 8 Kwords sectors.
Any combination of sectors can be concurrently erased. Also supports full chip erase
• Dual Boot Block
Sixteen 4Kwords boot block sectors, eight at the top of the address range and eight at the bottom of the address
range
• HiddenROM Region
256 byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC Input Pin
At VIL, allows protection of “outermost” 2×4 K words on both ends of boot sectors, regardless of sector protection/unprotection status
At VIH, allows removal of boot sector protection
At VACC, increases program performance
• Embedded EraseTM *2 Algorithms
Automatically preprograms and erases the chip or any sector
• Embedded ProgramTM *2 Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion
• Ready/Busy Output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic Sleep Mode
When addresses remain stable, the device automatically switches itself to low power mode
• Low VCC Write Inhibit ≤ 2.5 V
• Program Suspend/Resume
Suspends the program operation to allow a read in another byte
• Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Hardware Reset Pin (RESET)
Hardware method to reset the device for reading array data
(Continued)
2
MB84VP24491HK-70
(Continued)
• New Sector Protection
Persistent Sector Protection
Password Sector Protection
• Please refer to “MBM29RM12DH” Datasheet in detailed function
— FCRAMTM *3
• Power Dissipation
Operating : 30 mA Max
Standby : 100 µA Max
• Power Down Mode
Sleep
: 10 µA Max
4M Partial : 45 µA Max
8M Partial : 55 µA Max
16M Partial: 70 µA Max
• Power Down Control by CE2r
• Byte Write Control: LB(DQ7 to DQ0), UB(DQ15 to DQ8)
• 8 words Page Access Capability
*1: FlexBankTM is a trademark of Fujitsu Limited, Japan.
*2: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
*3: Mobile FCRAMTM is a trademark of Fujitsu Limited, Japan.
3
MB84VP24491HK-70
■ PIN ASSIGNMENT
(Top View)
Marking Side
A10
B10
F10
G10
L10
M10
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
D9
E9
F9
G9
H9
J9
A15
A21
CE1f
A16
N. C.
VSS
C8
D8
E8
F8
G8
H8
J8
K8
A11
A12
A13
A14
N.C.
DQ15
DQ7
DQ14
C7
D7
E7
F7
G7
H7
J7
K7
A8
A19
A9
A10
DQ6
DQ13
DQ12
DQ5
B6
C6
D6
E6
H6
J6
K6
L6
N.C.
WE
CE2r
A20
DQ4
VCCr
N.C.
N.C.
B5
C5
D5
E5
H5
J5
K5
L5
N.C.
WP/ACC
RESET
RY/BY
DQ3
VCCf
DQ11
N.C.
C4
D4
E4
F4
G4
H4
J4
K4
LB
UB
A18
A17
DQ1
DQ9
DQ10
DQ2
C3
D3
E3
F3
G3
H3
J3
K3
A7
A6
A5
A4
VSS
OE
DQ0
DQ8
D2
E2
F2
G2
H2
J2
A3
A2
A1
A0
CE0f
CE1r
A1
B1
C1
F1
G1
L1
M1
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
(BGA-73P-M03)
4
MB84VP24491HK-70
■ PIN DESCRIPTION
Pin name
Input/
Output
A20 to A0
I
Address Inputs (Common)
A21
I
Address Input (Flash)
DQ15 to DQ0
I/O
CE0f
I
Chip Enable (Flash)
CE1f
I
Chip Enable (Flash)
CE1r
I
Chip Enable (FCRAM)
CE2r
I
Chip Enable (FCRAM)
OE
I
Output Enable (Common)
WE
I
Write Enable (Common)
RY/BY
O
Ready/Busy Output (Flash) Open Drain Output
UB
I
Upper Byte Control (FCRAM)
LB
I
Lower Byte Control (FCRAM)
RESET
I
Hardware Reset Pin/Sector Protection Unlock (Flash)
WP/ACC
I
Write Protect / Acceleration (Flash)
N.C.
—
VSS
Power
Device Ground (Common)
VCCf
Power
Device Power Supply (Flash)
VCCr
Power
Device Power Supply (FCRAM)
Description
Data Inputs/Outputs (Common)
No Internal Connection
5
MB84VP24491HK-70
■ BLOCK DIAGRAM
VCCf
VSS
A21 to A0
RY/BY
A21 to A0
WP/ACC
128 M bit
Flash Memory
(Dual CE)
RESET
CE0f
CE1f
DQ15 to DQ0
DQ15 to DQ0
VCCr
VSS
A20 to A0
LB
UB
WE
OE
CE1r
CE2r
6
32 M bit
FCRAM
DQ15 to DQ0
MB84VP24491HK-70
■ DEVICE BUS OPERATIONS
Operation*1, *2
Full Standby
3
Output Disable*
Read from Flash*4
Write to Flash
Read from FCRAM
CE0f CE1f CE1r CE2r OE WE LB
H
H
H
H
H
L
L
H
H
H
L
H
L
H
H
L
L
H
H
H
X
X
X
UB
A21 to
A0
DQ7 to
DQ0
WP/
DQ15 to RESET ACC
DQ8
*9
X
X
High-Z
High-Z
H
X
High-Z
High-Z
H
X
8
X*
H
H
H
X
X
H
H
L
H
X
X
Valid
DOUT
DOUT
H
X
H
H
H
H
L
X
X
Valid
DIN
DIN
H
X
L
H
H
H
L
X
X
Valid
DIN
DIN
H
X
L
L
DIN
DIN
H
L
High-Z
DIN
H
X
L
H
DIN
High-Z
H
H
High-Z
High-Z
H
X
L
L
DIN
DIN
H
L
High-Z
DIN
H
X
L
H
DIN
High-Z
L
H
H
Valid
High-Z
High-Z
H
X
H
L
H
FCRAM No Read
H
H
L
H
Write to FCRAM
H
H
L
H
FCRAM No Write
H
H
L
Flash Temporary Sector
Group Unprotection*5
X
X
Flash Hardware Reset
X
Flash Boot Block Sector Write
Protection
FCRAM Power Down*6
L
H
L
H
L
X
Valid
Valid
Valid
H*
7
H
H*
7
X
X
X
X
X
X
X
X
X
VID
X
X
H
H
X
X
X
X
X
High-Z
High-Z
L
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
L
X
X
X
X
X
X
X
X
X
Legend: L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance.
See ■DC CHARACTERISTICS for voltage levels.
*1 : Other operations except for indicated this column are inhibited.
*2 : Do not apply for two or more states of the following conditions at the same time;
• CE0f = VIL
• CE1f = VIL
• CE1r = VIL and CE2r = VIH
*3 : Should not be kept FCRAM Output Disable condition longer than 1µs.
*4 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*5 : It is also used for the extended sector group protections.
*6 : FCRAM Power Down mode can be entered from Standby state and all DQ pins are in High-Z state.
Data retention depends on the selection of Power Down Program. Please refer to “Power Down Program”
in FCRAM Characteristics part.
*7 : OE can be VIL during Write operation if the following conditions are satisfied;
1) Write pulse is initiated by CE1r (refer to CE1r Controlled Write timing), or cycle time of the previous
operation cycle is satisfied.
2) OE stays VIL during Write cycle.
*8 : Can be either VIL or VIH but must be valid before Read or Write.
*9 : Protect “outer most” 2x8K bytes (4 words) on both ends of the boot block sectors.
7
MB84VP24491HK-70
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Min
Max
Tstg
–55
+125
°C
TA
–30
+85
°C
Voltage with Respect to Ground All pins
except RESET, WP/ACC *1
VIN, VOUT
–0.3
VCCf +0.3
V
VCCr +0.3
V
VCCf/VCCr Supply *1
VCCf, VCCr
–0.3
+3.3
V
RESET *2
VIN
–0.5
+ 13.0
V
WP/ACC *3
VIN
–0.5
+10.5
V
Storage Temperature
Ambient Temperature with Power Applied
*1 Minimum DC voltage on input or I/O pins is –0.3 V. During voltage transitions, input or I/O pins may undershoot
VSS to –1.0 V for periods of up to 5 ns. Maximum DC voltage on input or I/O pins is VCCf + 0.3 V or VCCr + 0.3V.
During voltage transitions, input or I/O pins may overshoot to VCCf + 2.0 V or VCCr + 1.0 V for periods of up to 5 ns.
*2: Minimum DC input voltage on RESET pin is –0.5 V. During voltage transitions RESET pins may undershoot VSS
to –2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN – VCCf) does not
exceed +9.0 V. Maximum DC input voltage on RESET pins is +13.0 V which may overshoot to +14.0 V for periods
of up to 20 ns.
*3: Minimum DC input voltage on WP/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may undershoot
Vss to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may
overshoot to +12.0 V for periods of up to 20 ns, when VCCf is applied.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Ambient Temperature
VCCf/VCCr Supply Voltages
Symbol
Value
Unit
Min
Max
TA
–30
+85
°C
VCCf, VCCr
+2.7
+3.1
V
Note: Operating ranges define those limits between which the functionality of the device is guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
8
MB84VP24491HK-70
■ DC CHARACTERISTICS
Parameter
Symbol
Value
Conditions
Min
Typ
Max
Unit
Input Leakage Current
ILI
VIN = VSS to VCCf, VCCr
–1.0
—
+1.0
µA
Output Leakage Current
ILO
VOUT = VSS to VCCf, VCCr, Output Disable
–1.0
—
+1.0
µA
RESET Inputs Leakage
Current (Flash)
ILIT
VCCf = VCCf Max, RESET = 12.5 V
—
—
35
µA
WP/ACC Acceleration
Program Current (Flash)
ILIA
VCCf = VCCf Max, WP/ACC = VACC Max
—
—
20
mA
CE (CE0f or CE1f) = VIL,
OE= VIH
f = 10 MHz
—
—
45
mA
CE (CE0f or CE1f) = VIL,
OE= VIH
f = 5 MHz
—
—
25
mA
Flash VCC Active Current
(Read) *1
ICC1f
Flash VCC Active Current *2
ICC2f
CE (CE0f or CE1f) = VIL, OEf= VIH
—
—
25
mA
Flash VCC Current (Standby)
ISB1f
VCCf = VCCf Max,CE0f, CE1f = VCCf ±0.3 V
RESET= VCCf ±0.3 V, WP/ACC =VCCf ±0.3 V
—
1
5
µA
Flash VCC Current
(Standby, Reset)
ISB2f
VCCf = VCCf Max, RESET= VSS ±0.3 V
—
1
5
µA
Flash VCC Current
(Automatic Sleep Mode) *3
ISB3f
VCCf = VCCf Max, CE0f, CE1f= VSS ±0.3 V,
RESET= VCCf ±0.3 V,
VIN = VCCf ±0.3 V or VSSf±0.3 V
—
1
5
µA
Flash VCC Active Current
(Read-while-Program) *5
ICC3f
CE (CE0f or CE1f) = VIL, OE= VIH
—
—
45
mA
Flash VCC Active Current
(Read-while-Erase) *5
ICC4f
CE (CE0f or CE1f) = VIL, OE= VIH
—
—
45
Flash VCC Active Current
(Erase Suspend Program)
ICC5f
CE (CE0f or CE1f) = VIL, OE= VIH
—
—
25
mA
Flash VCC Active Current
(Page Mode Read)
ICC6f
CE (CE0f or CE1f) = VIL, OE = VIH,
8 Word Read
—
—
10
mA
—
—
30
—
—
3
ICC1r
FCRAM VCC Active Current *8
ICC2r
VCCr = VCCr Max,
tRC / tWC =Min
CE1r = VIL, CE2r = VIH,
VIN = VIH or VIL, IOUT = 0mA*7 tRC / tWC =1 µs
mA
mA
FCRAM VCC Page Read
Current *8
ICC3r
VCCr = VCCr Max, VIN = VIH or VIL,
CE1r = VIL, CE2r = VIH, IOUT = 0 mA *7,
tPRC=Min
—
—
10
mA
FCRAM VCC Standby
Current *8
ISB1r
VCCr = VCCr Max, VIN < 0.2V or > VCCr – 0.2V
CE1r > VCCr – 0.2V, CE2r > VCCr– 0.2V
—
—
100
µA
Sleep
—
—
10
µA
IDDP4r VCCr = VCCr Max,
CE2r < 0.2V,
IDDP8r VIN = VIH or VIL
4M Partial
—
—
45
µA
8M Partial
—
—
55
µA
IDDP16r
16M Partial
—
—
70
µA
IDDPSr
FCRAM VCC Power Down
Current *8
(Continued)
9
MB84VP24491HK-70
(Continued)
Parameter
Input Low Level
Symbol
Conditions
VIL
Value
Unit
Min
Typ
Max
—
–0.3
—
VCC × 0.2 *6
V
6
Input High Level
VIH
—
VCC × 0.8
—
VCC+ 0.2 *
V
Voltage for Sector Protection, and
Temporary Sector Unprotection
(RESET) *4
VID
—
11.5
12
12.5
V
VACC
—
8.5
9.0
9.5
V
Voltage for WP/ACC Sector
Protection/Unprotection and
Program Acceleration *4
VOLf
VCCf = VCCf Min,
IOL = 0.1 mA
Flash
—
—
VCCf × 0.15
V
VOLr
VCCr = VCCr Min,
IOL = 1.0 mA
FCRAM
—
—
0.4
V
VOHf
VCCf = VCCf Min,
IOH = –0.1 mA
Flash
VCCf × 0.85
—
—
V
VOHr
VCCr = VCCr Min,
IOH = –0.5 mA
FCRAM
2.4
—
—
V
2.3
2.4
2.5
V
Output Low Voltage Level
Output High Voltage Level
Flash Low VCCf Lock-Out Voltage
VLKO
—
*1: The ICC current listed includes both the DC operating current and the frequency dependent component.
*2: ICC active while Embedded Algorithm (program or erase) is in progress.
*3: Automatic sleep mode enables the low power mode when address remains stable for 150 ns.
*4: Applicable for only VCCf applying.
*5: Embedded Algorithm (program or erase) is in progress. (@5 MHz)
*6: VCC indicates lower of VCCf or VCCr.
*7: FCRAM Characteristics are measured after following POWER-UP timing.
*8: IOUT depends on the output load conditions.
10
MB84VP24491HK-70
■ AC CHARACTERISTICS
• CE Timing
Parameter
Symbol
JEDEC
Standard
CE Recover Time
—
tCCR
CE Hold Time
—
CE1r High to WE Invalid time for
Standby Entry
—
Condition
Value
Unit
Min
Max
—
0
—
ns
tCHOLD
—
3
—
ns
tCHWX
—
10
—
ns
• Timing Diagram for alternating RAM to Flash
CE0f or
CE1f
tCCR
tCCR
CE1r
WE
tCHWX
tCCR
tCHOLD
tCCR
CE2r
• Flash Characteristics
Please refer to “■128 M PAEG FLASH MEMORY CHARACTERISTICS for MCP”.
• FCRAM Characteristics
Please refer to “■32 M FCRAM CHARACTERISTICS for MCP”.
11
MB84VP24491HK-70
■ 128 M PAGE FLASH MEMORY CHARACTERISTICS for MCP
1. Flexible Sector-erase Architecture on FLASH MEMORY (128M Page Flash)
• Sixteen 4K words, and two hundred fifty-four 32K words.
• Individual-sector, multiple-sector, or bulk-erase capability.
12
SA71 : 64KB
SA72 : 64KB
SA73 : 64KB
SA74 : 64KB
SA75 : 64KB
SA76 : 64KB
SA77 : 64KB
SA78 : 64KB
SA79 : 64KB
SA80 : 64KB
SA81 : 64KB
SA82 : 64KB
SA83 : 64KB
SA84 : 64KB
SA85 : 64KB
SA86 : 64KB
SA87 : 64KB
SA88 : 64KB
SA89 : 64KB
SA90 : 64KB
SA91 : 64KB
SA92 : 64KB
SA93 : 64KB
SA94 : 64KB
SA95 : 64KB
SA96 : 64KB
SA97 : 64KB
SA98 : 64KB
SA99 : 64KB
SA100: 64KB
SA101: 64KB
SA102: 64KB
SA103: 64KB
SA104: 64KB
SA105: 64KB
SA106: 64KB
SA107: 64KB
SA108: 64KB
SA109: 64KB
SA110: 64KB
SA111: 64KB
SA112: 64KB
SA113: 64KB
SA114: 64KB
SA115: 64KB
SA116: 64KB
SA117: 64KB
SA118: 64KB
SA119: 64KB
SA120: 64KB
SA121: 64KB
SA122: 64KB
SA123: 64KB
SA124: 64KB
SA125: 64KB
SA126: 64KB
SA127: 64KB
SA128: 64KB
SA129: 64KB
SA130: 64KB
SA131: 64KB
SA132: 64KB
SA133: 64KB
SA134: 64KB
200000h
208000h
210000h
218000h
220000h
228000h
230000h
238000h
240000h
248000h
250000h
258000h
260000h
268000h
270000h
278000h
280000h
288000h
290000h
298000h
2A0000h
2A8000h
2B0000h
2B8000h
2C0000h
2C8000h
2D0000h
2D8000h
2E0000h
2E8000h
2F0000h
2F8000h
300000h
308000h
310000h
318000h
320000h
328000h
330000h
338000h
340000h
348000h
350000h
358000h
360000h
368000h
370000h
378000h
380000h
388000h
390000h
398000h
3A0000h
3A8000h
3B0000h
3B8000h
3C0000h
3C8000h
3D0000h
3D8000h
3E0000h
3E8000h
3F0000h
3F8000h
3FFFFFh
SA135: 64KB
SA136: 64KB
SA137: 64KB
SA138: 64KB
SA139: 64KB
SA140: 64KB
SA141: 64KB
SA142: 64KB
SA143: 64KB
SA144: 64KB
SA145: 64KB
SA146: 64KB
SA147: 64KB
SA148: 64KB
SA149: 64KB
SA150: 64KB
SA151: 64KB
SA152: 64KB
SA153: 64KB
SA154: 64KB
SA155: 64KB
SA156: 64KB
SA157: 64KB
SA158: 64KB
SA159: 64KB
SA160: 64KB
SA161: 64KB
SA162: 64KB
SA163: 64KB
SA164: 64KB
SA165: 64KB
SA166: 64KB
SA167: 64KB
SA168: 64KB
SA169: 64KB
SA170: 64KB
SA171: 64KB
SA172: 64KB
SA173: 64KB
SA174: 64KB
SA175: 64KB
SA176: 64KB
SA177: 64KB
SA178: 64KB
SA179: 64KB
SA170: 64KB
SA181: 64KB
SA182: 64KB
SA183: 64KB
SA184: 64KB
SA185: 64KB
SA186: 64KB
SA187: 64KB
SA188: 64KB
SA189: 64KB
SA190: 64KB
SA191: 64KB
SA192: 64KB
SA193: 64KB
SA194: 64KB
SA195: 64KB
SA196: 64KB
SA197: 64KB
SA198: 64KB
400000h
408000h
410000h
418000h
420000h
428000h
430000h
438000h
440000h
448000h
450000h
458000h
460000h
468000h
470000h
478000h
480000h
488000h
490000h
498000h
4A0000h
4A8000h
4B0000h
4B8000h
4C0000h
4C8000h
4D0000h
4D8000h
4E0000h
4E8000h
4F0000h
4F8000h
500000h
508000h
510000h
518000h
520000h
528000h
530000h
538000h
540000h
548000h
550000h
558000h
560000h
568000h
570000h
578000h
580000h
588000h
590000h
598000h
5A0000h
5A8000h
5B0000h
5B8000h
5C0000h
5C8000h
5D0000h
5D8000h
5E0000h
5E8000h
5F0000h
5F8000h
5FFFFFh
BANK C
000000h
001000h
002000h
003000h
004000h
005000h
006000h
007000h
008000h
010000h
018000h
020000h
028000h
030000h
038000h
040000h
048000h
050000h
058000h
060000h
068000h
070000h
078000h
080000h
088000h
090000h
098000h
0A0000h
0A8000h
0B0000h
0B8000h
0C0000h
0C8000h
0D0000h
0D8000h
0E0000h
0E8000h
0F0000h
0F8000h
100000h
108000h
110000h
118000h
120000h
128000h
130000h
138000h
140000h
148000h
150000h
158000h
160000h
168000h
170000h
178000h
180000h
188000h
190000h
198000h
1A0000h
1A8000h
1B0000h
1B8000h
1C0000h
1C8000h
1D0000h
1D8000h
1E0000h
1E8000h
1F0000h
1F8000h
1FFFFFh
BANK C
: 8KB
: 8KB
: 8KB
: 8KB
: 8KB
: 8KB
: 8KB
: 8KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
BANK B
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
CE1f
BANK D
BANK B
BANK A
CE0f
SA199: 64KB
SA200: 64KB
SA201: 64KB
SA202: 64KB
SA203: 64KB
SA204: 64KB
SA205: 64KB
SA206: 64KB
SA207: 64KB
SA208: 64KB
SA209: 64KB
SA210: 64KB
SA211: 64KB
SA212: 64KB
SA213: 64KB
SA214: 64KB
SA215: 64KB
SA216: 64KB
SA217: 64KB
SA218: 64KB
SA219: 64KB
SA220: 64KB
SA221: 64KB
SA222: 64KB
SA223: 64KB
SA224: 64KB
SA225: 64KB
SA226: 64KB
SA227: 64KB
SA228: 64KB
SA229: 64KB
SA230: 64KB
SA231: 64KB
SA232: 64KB
SA233: 64KB
SA234: 64KB
SA235: 64KB
SA236: 64KB
SA237: 64KB
SA238: 64KB
SA239: 64KB
SA240: 64KB
SA241: 64KB
SA242: 64KB
SA243: 64KB
SA244: 64KB
SA245: 64KB
SA246: 64KB
SA247: 64KB
SA248: 64KB
SA249: 64KB
SA250: 64KB
SA251: 64KB
SA252: 64KB
SA253: 64KB
SA254: 64KB
SA255: 64KB
SA256: 64KB
SA257: 64KB
SA258: 64KB
SA259: 64KB
SA260: 64KB
SA261: 64KB
SA262: 8KB
SA263: 8KB
SA264: 8KB
SA265: 8KB
SA266: 8KB
SA267: 8KB
SA268: 8KB
SA269: 8KB
600000h
608000h
610000h
618000h
620000h
628000h
630000h
638000h
640000h
648000h
650000h
658000h
660000h
668000h
670000h
678000h
680000h
688000h
690000h
698000h
6A0000h
6A8000h
6B0000h
6B8000h
6C0000h
6C8000h
6D0000h
6D8000h
6E0000h
6E8000h
6F0000h
6F8000h
700000h
708000h
710000h
718000h
720000h
728000h
730000h
738000h
740000h
748000h
750000h
758000h
760000h
768000h
770000h
778000h
780000h
788000h
790000h
798000h
7A0000h
7A8000h
7B0000h
7B8000h
7C0000h
7C8000h
7D0000h
7D8000h
7E0000h
7E8000h
7F0000h
7F8000h
7F9000h
7FA000h
7FB000h
7FC000h
7FD000h
7FE000h
7FF000h
7FFFFFh
MB84VP24491HK-70
• FlexBankTM Architecture (128M Page Flash)
Bank 1
Bank 2
Bank
Splits
Volume
Combination
Volume
Combination
1
16 Mbit
Bank A
112 Mbit
Remainder (Bank B, C, D)
2
48 Mbit
Bank B
80 Mbit
Remainder (Bank A, C, D)
3
48 Mbit
Bank C
80 Mbit
Remainder (Bank A, B, D)
4
16 Mbit
Bank D
112 Mbit
Remainder (Bank A, B, C)
• Example of Virtual Banks Combination (128M Page Flash)
Bank
Splits
Bank 1
Volume
Bank 2
Combination
Sector Size
1
16 Mbit
Bank A
8 × 4 Kword
+
31 x 32 Kword
2
32 Mbit
Bank A
+
Bank D
16 x 4 Kword
+
62 x 32 Kword
Volume
Combination
Sector Size
112 Mbit
Bank B
+
Bank C
+
Bank D
8 x 4 Kword
+
223 x 32 Kword
96 Mbit
Bank B
+
Bank C
192 x 32 Kword
16 x 4 Kword
+
158 x 32 Kword
8 x 4 Kword
+
127 x 32 Kword
3
48 Mbit
Bank B
96 x 32 Kword
80 Mbit
Bank A
+
Bank C
+
Bank D
4
64 Mbit
Bank A
+
Bank B
8 x 4 Kword
+
127 x 32 Kword
64 Mbit
Bank C
+
Bank D
Note : When multiple sector erase over several banks is operated, the system cannot read out of the bank to which
a sector being erased belongs. For example, suppose that erasing is taking place at both Bank A and Bank B,
neither Bank A nor Bank B is read out (they would output the sequence flag once they were selected.)
Meanwhile the system would get to read from either Bank C or Bank D.
13
MB84VP24491HK-70
• Simultaneous Operation (Dual CE) (128M Page Flash)
The device features functions that enable reading of data from one memory bank while a program or erase
operation is in progress in the other memory bank (simultaneous operation) , in addition to conventional features
(read, program, erase, erase-suspend read, and erase-suspend program) . The bank can be selected by bank
address (A21, A20) with zero latency. The device consists of the following four banks :
CE0f control: Bank A : 8 x 4 KW and 31 x 32 KW; Bank B : 96 x 32 KW
CE1f control: Bank C : 96 x 32 KW; Bank D : 8 x 4 KW and 31 x 32 KW.
The possible combinations for simultaneous operation is show as following table. ( (Refer to Figure 11 Bank-toBank Read/Write Timing Diagram.)
• Simultaneous Operation for Dual CE (128M Page Flash)
Bank 1 (CE0f) Status
Bank 2 (CE0f) Status Bank 1 (CE1f) Status
Case
16 Mbit
48 Mbit
48 Mbit
Bank 2 (CE1f) Status
16 Mbit
1
Read mode
Read mode
Read mode
Read mode
2
Autoselect mode
Read mode
Read mode
Read mode
3
Read mode
Autoselect mode
Read mode
Read mode
4
Read mode
Read mode
Autoselect mode
Read mode
5
Read mode
Read mode
Read mode
Autoselect mode
6
Program mode
Read mode
Read mode
Read mode
7
Read mode
Program mode
Read mode
Read mode
8
Read mode
Read mode
Program mode
Read mode
9
Read mode
Read mode
Read mode
Program mode
10
Erase Mode
Read mode
Read mode
Read mode
11
Read mode
Erase Mode
Read mode
Read mode
12
Read mode
Read mode
Erase Mode
Read mode
13
Read mode
Read mode
Read mode
Erase Mode
14*
Multiple Erase Mode
Multiple Erase Mode
Read mode
Read mode
15*
Multiple Erase Mode
Read mode
Multiple Erase Mode
Read mode
16*
Multiple Erase Mode
Read mode
Read mode
Multiple Erase Mode
17*
Read mode
Multiple Erase Mode
Multiple Erase Mode
Read mode
18*
Read mode
Multiple Erase Mode
Read mode
Multiple Erase Mode
19*
Read mode
Read mode
Multiple Erase Mode
Multiple Erase Mode
20*
Multiple Erase Mode
Multiple Erase Mode
Multiple Erase Mode
Read mode
21*
Multiple Erase Mode
Multiple Erase Mode
Read mode
Multiple Erase Mode
22*
Multiple Erase Mode
Read mode
Multiple Erase Mode
Multiple Erase Mode
23*
Read mode
Multiple Erase Mode
Multiple Erase Mode
Multiple Erase Mode
* : Multiple Erase Mode requires multiple sector erase sequence which is followed by writes of the Sector Erase
command to addresses in other sectors desired to be concurrently erased. The time between writes must be
less than “tTOW”.
14
MB84VP24491HK-70
2. Flexible Sector-erase Architecture
• Sector Address Tables (Bank A) (128M Page Flash)
Bank
Sector
Bank A
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
Chip
Enable
Sector Address
Bank
Address
CE0f CE1f A21
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
A20 A19 A18 A17 A16 A15 A14 A13 A12
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 1 0
0 0 0 0 0 0 0 1 1
0 0 0 0 0 0 1 0 0
0 0 0 0 0 0 1 0 1
0 0 0 0 0 0 1 1 0
0 0 0 0 0 0 1 1 1
0 0 0 0 0 1 X X X
0 0 0 0 1 0 X X X
0 0 0 0 1 1 X X X
0 0 0 1 0 0 X X X
0 0 0 1 0 1 X X X
0 0 0 1 1 0 X X X
0 0 0 1 1 1 X X X
0 0 1 0 0 0 X X X
0 0 1 0 0 1 X X X
0 0 1 0 1 0 X X X
0 0 1 0 1 1 X X X
0 0 1 1 0 0 X X X
0 0 1 1 0 1 X X X
0 0 1 1 1 0 X X X
0 0 1 1 1 1 X X X
0 1 0 0 0 0 X X X
0 1 0 0 0 1 X X X
0 1 0 0 1 0 X X X
0 1 0 0 1 1 X X X
0 1 0 1 0 0 X X X
0 1 0 1 0 1 X X X
0 1 0 1 1 0 X X X
0 1 0 1 1 1 X X X
0 1 1 0 0 0 X X X
0 1 1 0 0 1 X X X
0 1 1 0 1 0 X X X
0 1 1 0 1 1 X X X
0 1 1 1 0 0 X X X
0 1 1 1 0 1 X X X
0 1 1 1 1 0 X X X
0 1 1 1 1 1 X X X
Sector
Size
(Kword)
(× 16)
Address Range
4
4
4
4
4
4
4
4
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
000000h to 000FFFh
001000h to 001FFFh
002000h to 002FFFh
003000h to 003FFFh
004000h to 004FFFh
005000h to 005FFFh
006000h to 006FFFh
007000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 06FFFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0FFFFFh
15
MB84VP24491HK-70
• Sector Address Tables (Bank B) (128M Page Flash)
Sector Address
Chip
Bank
Enable
Bank
Sector
Address
CE0f CE1f A21 A20 A19 A18 A17 A16 A15
SA39
0
1
0
1 0 0 0 0 0
SA40
0
1
0
1 0 0 0 0 1
SA41
0
1
0
1 0 0 0 1 0
SA42
0
1
0
1 0 0 0 1 1
SA43
0
1
0
1 0 0 1 0 0
SA44
0
1
0
1 0 0 1 0 1
SA45
0
1
0
1 0 0 1 1 0
SA46
0
1
0
1 0 0 1 1 1
SA47
0
1
0
1 0 1 0 0 0
SA48
0
1
0
1 0 1 0 0 1
SA49
0
1
0
1 0 1 0 1 0
SA50
0
1
0
1 0 1 0 1 1
SA51
0
1
0
1 0 1 1 0 0
SA52
0
1
0
1 0 1 1 0 1
SA53
0
1
0
1 0 1 1 1 0
SA54
0
1
0
1 0 1 1 1 1
SA55
0
1
0
1 1 0 0 0 0
SA56
0
1
0
1 1 0 0 0 1
SA57
0
1
0
1 1 0 0 1 0
SA58
0
1
0
1 1 0 0 1 1
Bank B
SA59
0
1
0
1 1 0 1 0 0
SA60
0
1
0
1 1 0 1 0 1
SA61
0
1
0
1 1 0 1 1 0
SA62
0
1
0
1 1 0 1 1 1
SA63
0
1
0
1 1 1 0 0 0
SA64
0
1
0
1 1 1 0 0 1
SA65
0
1
0
1 1 1 0 1 0
SA66
0
1
0
1 1 1 0 1 1
SA67
0
1
0
1 1 1 1 0 0
SA68
0
1
0
1 1 1 1 0 1
SA69
0
1
0
1 1 1 1 1 0
SA70
0
1
0
1 1 1 1 1 1
SA71
0
1
1
0 0 0 0 0 0
SA72
0
1
1
0 0 0 0 0 1
SA73
0
1
1
0 0 0 0 1 0
SA74
0
1
1
0 0 0 0 1 1
SA75
0
1
1
0 0 0 1 0 0
SA76
0
1
1
0 0 0 1 0 1
SA77
0
1
1
0 0 0 1 1 0
16
A14 A13 A12
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
Sector
Size
(Kword)
(× 16)
Address Range
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
100000h to 107FFFh
108000h to 10FFFFh
110000h to 117FFFh
118000h to 11FFFFh
120000h to 127FFFh
128000h to 12FFFFh
130000h to 137FFFh
138000h to 13FFFFh
140000h to 147FFFh
148000h to 14FFFFh
150000h to 157FFFh
158000h to 15FFFFh
160000h to 167FFFh
168000h to 16FFFFh
170000h to 177FFFh
178000h to 17FFFFh
180000h to 187FFFh
188000h to 18FFFFh
190000h to 197FFFh
198000h to 19FFFFh
1A0000h to 1A7FFFh
1A8000h to 1AFFFFh
1B0000h to 1B7FFFh
1B8000h to 1BFFFFh
1C0000h to 1C7FFFh
1C8000h to 1CFFFFh
1D0000h to 1D7FFFh
1D8000h to 1DFFFFh
1E0000h to 1E7FFFh
1E8000h to 1EFFFFh
1F0000h to 1F7FFFh
1F8000h to 1FFFFFh
200000h to 207FFFh
208000h to 20FFFFh
210000h to 217FFFh
218000h to 21FFFFh
220000h to 227FFFh
228000h to 22FFFFh
230000h to 237FFFh
(Continued)
MB84VP24491HK-70
Bank
Sector
Bank B
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
Chip
Enable
Bank
Address
CE0f CE1f A21 A20
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
Sector Address
A19 A18 A17 A16 A15 A14 A13 A12
0 0 1 1 1 X X X
0 1 0 0 0 X X X
0 1 0 0 1 X X X
0 1 0 1 0 X X X
0 1 0 1 1 X X X
0 1 1 0 0 X X X
0 1 1 0 1 X X X
0 1 1 1 0 X X X
0 1 1 1 1 X X X
1 0 0 0 0 X X X
1 0 0 0 1 X X X
1 0 0 1 0 X X X
1 0 0 1 1 X X X
1 0 1 0 0 X X X
1 0 1 0 1 X X X
1 0 1 1 0 X X X
1 0 1 1 1 X X X
1 1 0 0 0 X X X
1 1 0 0 1 X X X
1 1 0 1 0 X X X
1 1 0 1 1 X X X
1 1 1 0 0 X X X
1 1 1 0 1 X X X
1 1 1 1 0 X X X
1 1 1 1 1 X X X
0 0 0 0 0 X X X
0 0 0 0 1 X X X
0 0 0 1 0 X X X
0 0 0 1 1 X X X
0 0 1 0 0 X X X
0 0 1 0 1 X X X
0 0 1 1 0 X X X
0 0 1 1 1 X X X
0 1 0 0 0 X X X
0 1 0 0 1 X X X
0 1 0 1 0 X X X
0 1 0 1 1 X X X
0 1 1 0 0 X X X
0 1 1 0 1 X X X
Sector
Size
(Kword)
(× 16)
Address Range
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
238000h to 23FFFFh
240000h to 247FFFh
248000h to 24FFFFh
250000h to 257FFFh
258000h to 25FFFFh
260000h to 267FFFh
268000h to 26FFFFh
270000h to 277FFFh
278000h to 27FFFFh
280000h to 287FFFh
288000h to 28FFFFh
290000h to 297FFFh
298000h to 29FFFFh
2A0000h to 2A7FFFh
2A8000h to 2AFFFFh
2B0000h to 2B7FFFh
2B8000h to 2BFFFFh
2C0000h to 2C7FFFh
2C8000h to 2CFFFFh
2D0000h to 2D7FFFh
2D8000h to 2DFFFFh
2E0000h to 2E7FFFh
2E8000h to 2EFFFFh
2F0000h to 2F7FFFh
2F8000h to 2FFFFFh
300000h to 307FFFh
308000h to 30FFFFh
310000h to 317FFFh
318000h to 31FFFFh
320000h to 327FFFh
328000h to 32FFFFh
330000h to 337FFFh
338000h to 33FFFFh
340000h to 347FFFh
348000h to 34FFFFh
350000h to 357FFFh
358000h to 35FFFFh
360000h to 367FFFh
368000h to 36FFFFh
(Continued)
17
MB84VP24491HK-70
(Continued)
Bank
Bank B
18
Sector
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
Chip
Enable
Sector Address
Bank
Address
CE0f CE1f A21
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
A20 A19 A18 A17 A16 A15 A14 A13 A12
1 0 1 1 1 0 X X X
1 0 1 1 1 1 X X X
1 1 0 0 0 0 X X X
1 1 0 0 0 1 X X X
1 1 0 0 1 0 X X X
1 1 0 0 1 1 X X X
1 1 0 1 0 0 X X X
1 1 0 1 0 1 X X X
1 1 0 1 1 0 X X X
1 1 0 1 1 1 X X X
1 1 1 0 0 0 X X X
1 1 1 0 0 1 X X X
1 1 1 0 1 0 X X X
1 1 1 0 1 1 X X X
1 1 1 1 0 0 X X X
1 1 1 1 0 1 X X X
1 1 1 1 1 0 X X X
1 1 1 1 1 1 X X X
Sector
Size
(Kword)
(× 16)
Address Range
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
370000h to 377FFFh
378000h to 37FFFFh
380000h to 387FFFh
388000h to 38FFFFh
390000h to 397FFFh
398000h to 39FFFFh
3A0000h to 3A7FFFh
3A8000h to 3AFFFFh
3B0000h to 3B7FFFh
3B8000h to 3BFFFFh
3C0000h to 3C7FFFh
3C8000h to 3CFFFFh
3D0000h to 3D7FFFh
3D8000h to 3DFFFFh
3E0000h to 3E7FFFh
3E8000h to 3EFFFFh
3F0000h to 3F7FFFh
3F8000h to 3FFFFFh
MB84VP24491HK-70
• Sector Address Tables (Bank C) (128M Page Flash)
Bank
Bank C
Sector
SA135
SA136
SA137
SA138
SA139
SA140
SA141
SA142
SA143
SA144
SA145
SA146
SA147
SA148
SA149
SA150
SA151
SA152
SA153
SA154
SA155
SA156
SA157
SA158
SA159
SA160
SA161
SA162
SA163
SA164
SA165
SA166
SA167
SA168
SA169
SA170
SA171
SA172
SA173
Chip
Enable
Sector Address
Bank
Address
CE0f CE1f A21
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
A20 A19 A18 A17 A16 A15 A14 A13 A12
0 0 0 0 0 0 X X X
0 0 0 0 0 1 X X X
0 0 0 0 1 0 X X X
0 0 0 0 1 1 X X X
0 0 0 1 0 0 X X X
0 0 0 1 0 1 X X X
0 0 0 1 1 0 X X X
0 0 0 1 1 1 X X X
0 0 1 0 0 0 X X X
0 0 1 0 0 1 X X X
0 0 1 0 1 0 X X X
0 0 1 0 1 1 X X X
0 0 1 1 0 0 X X X
0 0 1 1 0 1 X X X
0 0 1 1 1 0 X X X
0 0 1 1 1 1 X X X
0 1 0 0 0 0 X X X
0 1 0 0 0 1 X X X
0 1 0 0 1 0 X X X
0 1 0 0 1 1 X X X
0 1 0 1 0 0 X X X
0 1 0 1 0 1 X X X
0 1 0 1 1 0 X X X
0 1 0 1 1 1 X X X
0 1 1 0 0 0 X X X
0 1 1 0 0 1 X X X
0 1 1 0 1 0 X X X
0 1 1 0 1 1 X X X
0 1 1 1 0 0 X X X
0 1 1 1 0 1 X X X
0 1 1 1 1 0 X X X
0 1 1 1 1 1 X X X
1 0 0 0 0 0 X X X
1 0 0 0 0 1 X X X
1 0 0 0 1 0 X X X
1 0 0 0 1 1 X X X
1 0 0 1 0 0 X X X
1 0 0 1 0 1 X X X
1 0 0 1 1 0 X X X
Sector
Size
(Kword)
(× 16)
Address Range
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
400000h to 407FFFh
408000h to 40FFFFh
410000h to 417FFFh
418000h to 41FFFFh
420000h to 427FFFh
428000h to 42FFFFh
430000h to 437FFFh
438000h to 43FFFFh
440000h to 447FFFh
448000h to 44FFFFh
450000h to 457FFFh
458000h to 45FFFFh
460000h to 467FFFh
468000h to 46FFFFh
470000h to 477FFFh
478000h to 47FFFFh
480000h to 487FFFh
488000h to 48FFFFh
490000h to 497FFFh
498000h to 49FFFFh
4A0000h to 4A7FFFh
4A8000h to 4AFFFFh
4B0000h to 4B7FFFh
4B8000h to 4BFFFFh
4C0000h to 4C7FFFh
4C8000h to 4CFFFFh
4D0000h to 4D7FFFh
4D8000h to 4DFFFFh
4E0000h to 4E7FFFh
4E8000h to 4EFFFFh
4F0000h to 4F7FFFh
4F8000h to 4FFFFFh
500000h to 507FFFh
508000h to 50FFFFh
510000h to 517FFFh
518000h to 51FFFFh
520000h to 527FFFh
528000h to 52FFFFh
530000h to 537FFFh
(Continued)
19
MB84VP24491HK-70
Bank
Sector
Bank C
SA174
SA175
SA176
SA177
SA178
SA179
SA180
SA181
SA182
SA183
SA184
SA185
SA186
SA187
SA188
SA189
SA190
SA191
SA192
SA193
SA194
SA195
SA196
SA197
SA198
SA199
SA200
SA201
SA202
SA203
SA204
SA205
SA206
SA207
SA208
SA209
SA210
SA211
SA212
Chip
Enable
Bank
Address
CE0f CE1f A21 A20
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Sector Address
A19 A18 A17 A16 A15 A14 A13 A12
0 0 1 1 1 X X X
0 1 0 0 0 X X X
0 1 0 0 1 X X X
0 1 0 1 0 X X X
0 1 0 1 1 X X X
0 1 1 0 0 X X X
0 1 1 0 1 X X X
0 1 1 1 0 X X X
0 1 1 1 1 X X X
1 0 0 0 0 X X X
1 0 0 0 1 X X X
1 0 0 1 0 X X X
1 0 0 1 1 X X X
1 0 1 0 0 X X X
1 0 1 0 1 X X X
1 0 1 1 0 X X X
1 0 1 1 1 X X X
1 1 0 0 0 X X X
1 1 0 0 1 X X X
1 1 0 1 0 X X X
1 1 0 1 1 X X X
1 1 1 0 0 X X X
1 1 1 0 1 X X X
1 1 1 1 0 X X X
1 1 1 1 1 X X X
0 0 0 0 0 X X X
0 0 0 0 1 X X X
0 0 0 1 0 X X X
0 0 0 1 1 X X X
0 0 1 0 0 X X X
0 0 1 0 1 X X X
0 0 1 1 0 X X X
0 0 1 1 1 X X X
0 1 0 0 0 X X X
0 1 0 0 1 X X X
0 1 0 1 0 X X X
0 1 0 1 1 X X X
0 1 1 0 0 X X X
0 1 1 0 1 X X X
Sector
Size
(Kword)
(× 16)
Address Range
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
538000h to 53FFFFh
540000h to 547FFFh
548000h to 54FFFFh
550000h to 557FFFh
558000h to 55FFFFh
560000h to 567FFFh
568000h to 56FFFFh
570000h to 577FFFh
578000h to 57FFFFh
580000h to 587FFFh
588000h to 58FFFFh
590000h to 597FFFh
598000h to 59FFFFh
5A0000h to 5A7FFFh
5A8000h to 5AFFFFh
5B0000h to 5B7FFFh
5B8000h to 5BFFFFh
5C0000h to 5C7FFFh
5C8000h to 5CFFFFh
6D0000h to 5D7FFFh
6D8000h to 5DFFFFh
5E0000h to 5E7FFFh
5E8000h to 5EFFFFh
5F0000h to 5F7FFFh
5F8000h to 5FFFFFh
600000h to 607FFFh
608000h to 60FFFFh
610000h to 617FFFh
618000h to 61FFFFh
620000h to 627FFFh
628000h to 62FFFFh
630000h to 637FFFh
638000h to 63FFFFh
640000h to 647FFFh
648000h to 64FFFFh
650000h to 657FFFh
658000h to 65FFFFh
660000h to 667FFFh
668000h to 66FFFFh
(Continued)
20
MB84VP24491HK-70
(Continued)
Bank
Bank C
Sector
SA213
SA214
SA215
SA216
SA217
SA218
SA219
SA220
SA221
SA222
SA223
SA224
SA225
SA226
SA227
SA228
SA229
SA230
Chip
Enable
Sector Address
Bank
Address
CE0f CE1f A21
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
A20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A19 A18 A17 A16 A15 A14 A13 A12
0 1 1 1 0 X X X
0 1 1 1 1 X X X
1 0 0 0 0 X X X
1 0 0 0 1 X X X
1 0 0 1 0 X X X
1 0 0 1 1 X X X
1 0 1 0 0 X X X
1 0 1 0 1 X X X
1 0 1 1 0 X X X
1 0 1 1 1 X X X
1 1 0 0 0 X X X
1 1 0 0 1 X X X
1 1 0 1 0 X X X
1 1 0 1 1 X X X
1 1 1 0 0 X X X
1 1 1 0 1 X X X
1 1 1 1 0 X X X
1 1 1 1 1 X X X
Sector
Size
(Kword)
(× 16)
Address Range
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
670000h to 677FFFh
678000h to 67FFFFh
680000h to 687FFFh
688000h to 68FFFFh
690000h to 697FFFh
698000h to 69FFFFh
6A0000h to 6A7FFFh
6A8000h to 6AFFFFh
6B0000h to 6B7FFFh
8B8000h to 6BFFFFh
6C0000h to 6C7FFFh
6C8000h to 6CFFFFh
6D0000h to 6D7FFFh
6D8000h to 6DFFFFh
6E0000h to 6E7FFFh
6E8000h to 6EFFFFh
6F0000h to 6F7FFFh
6F8000h to 6FFFFFh
21
MB84VP24491HK-70
• Sector Address Tables (Bank D) (128M Page Flash)
Bank
Bank D
22
Sector
SA231
SA232
SA233
SA234
SA235
SA236
SA237
SA238
SA239
SA240
SA241
SA242
SA243
SA244
SA245
SA246
SA247
SA248
SA249
SA250
SA251
SA252
SA253
SA254
SA255
SA256
SA257
SA258
SA259
SA260
SA261
SA262
SA263
SA264
SA265
SA266
SA267
SA268
SA269
Chip
Enable
Bank
Address
CE0f CE1f A21 A20
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
Sector Address
A19 A18 A17 A16 A15 A14 A13 A12
0 0 0 0 0 X X X
0 0 0 0 1 X X X
0 0 0 1 0 X X X
0 0 0 1 1 X X X
0 0 1 0 0 X X X
0 0 1 0 1 X X X
0 0 1 1 0 X X X
0 0 1 1 1 X X X
0 1 0 0 0 X X X
0 1 0 0 1 X X X
0 1 0 1 0 X X X
0 1 0 1 1 X X X
0 1 1 0 0 X X X
0 1 1 0 1 X X X
0 1 1 1 0 X X X
0 1 1 1 1 X X X
1 0 0 0 0 X X X
1 0 0 0 1 X X X
1 0 0 1 0 X X X
1 0 0 1 1 X X X
1 0 1 0 0 X X X
1 0 1 0 1 X X X
1 0 1 1 0 X X X
1 0 1 1 1 X X X
1 1 0 0 0 X X X
1 1 0 0 1 X X X
1 1 0 1 0 X X X
1 1 0 1 1 X X X
1 1 1 0 0 X X X
1 1 1 0 1 X X X
1 1 1 1 0 X X X
1 1 1 1 1 0 0 0
1 1 1 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 1 1 0 1 1
1 1 1 1 1 1 0 0
1 1 1 1 1 1 0 1
1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1
Sector
Size
(Kword)
(× 16)
Address Range
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
4
4
4
4
4
4
4
700000h to 707FFFh
708000h to 70FFFFh
710000h to 717FFFh
718000h to 71FFFFh
720000h to 727FFFh
728000h to 72FFFFh
730000h to 737FFFh
738000h to 73FFFFh
740000h to 747FFFh
748000h to 74FFFFh
750000h to 757FFFh
758000h to 75FFFFh
760000h to 767FFFh
768000h to 76FFFFh
770000h to 777FFFh
778000h to 77FFFFh
780000h to 787FFFh
788000h to 78FFFFh
790000h to 797FFFh
798000h to 79FFFFh
7A0000h to 7A7FFFh
7A8000h to 7AFFFFh
7B0000h to 7B7FFFh
7B8000h to 7BFFFFh
7C0000h to 7C7FFFh
7C8000h to 7CFFFFh
7D0000h to 7D7FFFh
7D8000h to 7DFFFFh
7E0000h to 7E7FFFh
7E8000h to 7EFFFFh
7F0000h to 7F7FFFh
7F8000h to 7F8FFFh
7F9000h to 7F9FFFh
7FA000h to 7FAFFFh
7FB000h to 7FBFFFh
7FC000h to 7FCFFFh
7FD000h to 7FDFFFh
7FE000h to 7FEFFFh
7FF000h to 7FFFFFh
MB84VP24491HK-70
• Sector Group Address Table (128M Page Flash)
Sector Group CE0f CE1f
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
Sectors
SGA0
0
1
0
0
0
0
0
0
0
0
0
0
SA0
SGA1
0
1
0
0
0
0
0
0
0
0
0
1
SA1
SGA2
0
1
0
0
0
0
0
0
0
0
1
0
SA2
SGA3
0
1
0
0
0
0
0
0
0
0
1
1
SA3
SGA4
0
1
0
0
0
0
0
0
0
1
0
0
SA4
SGA5
0
1
0
0
0
0
0
0
0
1
0
1
SA5
SGA6
0
1
0
0
0
0
0
0
0
1
1
0
SA6
SGA7
0
1
0
0
0
0
0
0
0
1
1
1
SA7
SGA8
0
1
0
0
0
0
0
0
1
X
X
X
SA8
SGA9
0
1
0
0
0
0
0
1
0
X
X
X
SA9
SGA10
0
1
0
0
0
0
0
1
1
X
X
X
SA10
SGA11
0
1
0
0
0
0
1
X
X
X
X
X
SA11 to SA14
SGA12
0
1
0
0
0
1
0
X
X
X
X
X
SA15 to SA18
SGA13
0
1
0
0
0
1
1
X
X
X
X
X
SA19 to SA22
SGA14
0
1
0
0
1
0
0
X
X
X
X
X
SA23 to SA26
SGA15
0
1
0
0
1
0
1
X
X
X
X
X
SA27 to SA30
SGA16
0
1
0
0
1
1
0
X
X
X
X
X
SA31 to SA34
SGA17
0
1
0
0
1
1
1
X
X
X
X
X
SA35 to SA38
SGA18
0
1
0
1
0
0
0
X
X
X
X
X
SA39 to SA42
SGA19
0
1
0
1
0
0
1
X
X
X
X
X
SA43 to SA46
SGA20
0
1
0
1
0
1
0
X
X
X
X
X
SA47 to SA50
SGA21
0
1
0
1
0
1
1
X
X
X
X
X
SA51 to SA54
SGA22
0
1
0
1
1
0
0
X
X
X
X
X
SA55 to SA58
SGA23
0
1
0
1
1
0
1
X
X
X
X
X
SA59 to SA62
SGA24
0
1
0
1
1
1
0
X
X
X
X
X
SA63 to SA66
SGA25
0
1
0
1
1
1
1
X
X
X
X
X
SA67 to SA70
SGA26
0
1
1
0
0
0
0
X
X
X
X
X
SA71 to SA74
SGA27
0
1
1
0
0
0
1
X
X
X
X
X
SA75 to SA78
SGA28
0
1
1
0
0
1
0
X
X
X
X
X
SA79 to SA82
SGA29
0
1
1
0
0
1
1
X
X
X
X
X
SA83 to SA86
SGA30
0
1
1
0
1
0
0
X
X
X
X
X
SA87 to SA90
SGA31
0
1
1
0
1
0
1
X
X
X
X
X
SA91 to SA94
SGA32
0
1
1
0
1
1
0
X
X
X
X
X
SA95 to SA98
SGA33
0
1
1
0
1
1
1
X
X
X
X
X
SA99 to SA102
SGA34
0
1
1
1
0
0
0
X
X
X
X
X
SA103 to SA106
SGA35
0
1
1
1
0
0
1
X
X
X
X
X
SA107 to SA110
SGA36
0
1
1
1
0
1
0
X
X
X
X
X
SA111 to SA114
SGA37
0
1
1
1
0
1
1
X
X
X
X
X
SA115 to SA118
SGA38
0
1
1
1
1
0
0
X
X
X
X
X
SA119 to SA122
SGA39
0
1
1
1
1
0
1
X
X
X
X
X
SA123 to SA126
SGA40
0
1
1
1
1
1
0
X
X
X
X
X
SA127 to SA130
SGA41
0
1
1
1
1
1
1
X
X
X
X
X
SA131 to SA134
(Continued)
23
MB84VP24491HK-70
(Continued)
Sector Group CE0f CE1f
24
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
Sectors
SGA42
1
0
0
0
0
0
0
X
X
X
X
X
SA135 to SA138
SGA43
1
0
0
0
0
0
1
X
X
X
X
X
SA139 to SA142
SGA44
1
0
0
0
0
1
0
X
X
X
X
X
SA143 to SA146
SGA45
1
0
0
0
0
1
1
X
X
X
X
X
SA147 to SA150
SGA46
1
0
0
0
1
0
0
X
X
X
X
X
SA151 to SA154
SGA47
1
0
0
0
1
0
1
X
X
X
X
X
SA155 to SA158
SGA48
1
0
0
0
1
1
0
X
X
X
X
X
SA159 to SA162
SGA49
1
0
0
0
1
1
1
X
X
X
X
X
SA163 to SA166
SGA50
1
0
0
1
0
0
0
X
X
X
X
X
SA167 to SA170
SGA51
1
0
0
1
0
0
1
X
X
X
X
X
SA171 to SA174
SGA52
1
0
0
1
0
1
0
X
X
X
X
X
SA175 to SA178
SGA53
1
0
0
1
0
1
1
X
X
X
X
X
SA179 to SA182
SGA54
1
0
0
1
1
0
0
X
X
X
X
X
SA183 to SA186
SGA55
1
0
0
1
1
0
1
X
X
X
X
X
SA187 to SA190
SGA56
1
0
0
1
1
1
0
X
X
X
X
X
SA191 to SA194
SGA57
1
0
0
1
1
1
1
X
X
X
X
X
SA195 to SA198
SGA58
1
0
1
0
0
0
0
X
X
X
X
X
SA199 to SA202
SGA59
1
0
1
0
0
0
1
X
X
X
X
X
SA203 to SA206
SGA60
1
0
1
0
0
1
0
X
X
X
X
X
SA207 to SA210
SGA61
1
0
1
0
0
1
1
X
X
X
X
X
SA211 to SA214
SGA62
1
0
1
0
1
0
0
X
X
X
X
X
SA215 to SA218
SGA63
1
0
1
0
1
0
1
X
X
X
X
X
SA219 to SA222
SGA64
1
0
1
0
1
1
0
X
X
X
X
X
SA223 to SA226
SGA65
1
0
1
0
1
1
1
X
X
X
X
X
SA227 to SA230
SGA66
1
0
1
1
0
0
0
X
X
X
X
X
SA231 to SA234
SGA67
1
0
1
1
0
0
1
X
X
X
X
X
SA235 to SA238
SGA68
1
0
1
1
0
1
0
X
X
X
X
X
SA239 to SA242
SGA69
1
0
1
1
0
1
1
X
X
X
X
X
SA243 to SA246
SGA70
1
0
1
1
1
0
0
X
X
X
X
X
SA247 to SA250
SGA71
1
0
1
1
1
0
1
X
X
X
X
X
SA251 to SA254
SGA72
1
0
1
1
1
1
0
X
X
X
X
X
SA255 to SA258
SGA73
1
0
1
1
1
1
1
0
0
X
X
X
SA259
SGA74
1
0
1
1
1
1
1
0
1
X
X
X
SA260
SGA75
1
0
1
1
1
1
1
1
0
X
X
X
SA261
SGA76
1
0
1
1
1
1
1
1
1
0
0
0
SA262
SGA77
1
0
1
1
1
1
1
1
1
0
0
1
SA263
SGA78
1
0
1
1
1
1
1
1
1
0
1
0
SA264
SGA79
1
0
1
1
1
1
1
1
1
0
1
1
SA265
SGA80
1
0
1
1
1
1
1
1
1
1
0
0
SA266
SGA81
1
0
1
1
1
1
1
1
1
1
0
1
SA267
SGA82
1
0
1
1
1
1
1
1
1
1
1
0
SA268
SGA83
1
0
1
1
1
1
1
1
1
1
1
1
SA269
MB84VP24491HK-70
• Sector Group Protection Verify Autoselect Codes (128M Page Flash)
A7 A6 A5 A4 A3 A2 A1 A0
Type
A22 to A12
Code (HEX)
Manufacture’s Code
BA
L
L
X
X
L
L
L
L
04h
Device Code
BA
L
L
X
X
L
L
L
H
227Eh
Extended Device Code*2
BA
L
L
X
X
H
H
H
L
2221h
L
L
X
X
H
H
H
H
2200h
Sector Group Protection
Sector
Group
Addresses
L
L
L
L
L
L
H
L
01h*1
Legend: L = VIL, H = VIH, X= VIL or VIH
*1 : Sector Group can be protected by “Extended Sector Group Protection”, and “New Sector Protection (PPB
Protection)”. Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group
addresses.
*2 : A read cycle at address (BA) 01h outputs device code. When 227Eh is output, it indicates that two additional
codes, called Extended Device Codes, will be required. Therefore the system may continue reading out these
Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh.
25
MB84VP24491HK-70
• Command Definitions (128M Page Flash)
Bus
Write
Cycles
Req’d
1
3
Autoselect
3
Program
Chip Erase
Sector Erase
Program/Erase
Suspend
Program/Erase
Resume
Set to Fast
Mode
Fast Program
Reset from Fast
Mode *1
Extended
Sector Group
Protection *2
Command
Sequence
Read/Reset
Read/Reset
Query
HiddenROM
Entry
HiddenROM
Program *3
HiddenROM
Exit *3
HiddenROM
Protect *3
Password
Program
Password
Unlock
Password Verify
Password Mode
Locking Bit
Program
Persistent
Protection Mode
Locking Bit
Program
PPB Program
First Bus
Write Cycle
Second Bus
Write Cycle
Third Bus
Write Cycle
Fourth Bus
Read/Write
Cycle
Fifth Bus
Write Cycle
Sixth Bus
Write Cycle
Seventh Bus
Write Cycle
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Data
XXXh
555h
F0h
AAh
RA
2AAh
RD
55h
—
F0h
—
RA
—
RD
—
—
—
—
—
—
—
—
—
—
—
—
555h
AAh
2AAh
55h
90h
—
—
—
—
—
—
—
—
4
6
6
555h
555h
555h
AAh
AAh
AAh
2AAh
2AAh
2AAh
55h
55h
55h
—
555h
(BA)
555h
555h
555h
555h
A0h
80h
80h
PA
555h
555h
PD
AAh
AAh
—
2AAh
2AAh
—
55h
55h
—
555h
SA
—
10h
30h
—
—
—
—
—
—
1
BA
B0h
—
—
—
—
—
—
—
—
—
—
—
—
1
BA
30h
—
—
—
—
—
—
—
—
—
—
—
—
3
555h
AAh
2AAh
55h
555h
20h
—
—
—
—
—
—
—
—
PD
*4
F0h
2
XXXh
A0h
PA
2
BA
90h
XXXh
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
XXXh
60h
SGA+
WPH
60h
SGA+
WPH
40h
SGA+
WPH
SD
—
—
—
—
—
—
1
(BA)
55h
98h
—
—
—
—
—
—
—
—
—
—
—
—
3
555h
AAh
2AAh
55h
555h
88h
—
—
—
—
—
—
—
—
4
555h
AAh
2AAh
55h
555h
A0h
(HRA)
PA
PD
—
—
—
—
—
—
4
555h
AAh
2AAh
55h
90h
XXXh
00h
—
—
—
—
—
—
6
555h
AAh
2AAh
55h
555h
60h
OPBP
68h
OPBP
48h
—
—
4
555h
555h
555h
555h
AAh
AAh
AAh
AAh
2AAh
2AAh
2AAh
2AAh
55h
55h
55h
55h
555h
555h
555h
555h
38h
38h
38h
38h
XX0h
XX1h
XX2h
XX3h
PD0
PD1
PD2
PD3
—
—
—
—
—
—
7
555h
AAh
2AAh
55h
555h
28h
XX0h
PD0
XX1h
PD1
XX2h
PD2
XX3h
PD3
4
555h
AAh
2AAh
55h
555h
C8h
PWA
PWD
—
—
—
—
—
—
6
555h
AAh
2AAh
55h
555h
60h
PL
68h
PL
48h
XXXh
RD(0)
—
—
6
555h
AAh
2AAh
55h
555h
60h
SPML
68h
SPML
48h
XXXh
RD(0)
—
—
60h
SGA+WP
68h
SGA+WP
48h
XXXh
RD(0)
—
—
90h
SGA+WP
RD(0)
—
—
—
—
—
—
60h
WP
60h
SGA+WP
40h
XXXh
RD(0)
—
—
78h
—
—
—
—
—
—
—
—
58h
SA
RD(1)
—
—
—
—
—
—
48h
48h
SA
SA
X1h
X0h
—
—
—
—
—
—
—
—
—
—
—
—
58h
SA
RD(0)
—
—
—
—
—
—
(HRBA)
555h
6
555h
AAh
2AAh
55h
PPB Verify
4
555h
AAh
2AAh
55h
All PPB Erase
PPB Lock Bit
Set
PPB Lock Bit
Verify
DPB Write
DPB Erase
4
555h
AAh
2AAh
55h
555h
(BA)
555h
555h
3
555h
AAh
2AAh
55h
555h
4
555h
AAh
2AAh
55h
4
4
555h
555h
AAh
AAh
2AAh
2AAh
55h
55h
4
555h
AAh
2AAh
55h
DPB Verify
(BA)
555h
555h
555h
(BA)
555h
OPBP RD(0)
(Continued)
26
MB84VP24491HK-70
(Continued)
Legend:
RA = Address of the memory location to be read
PA = Address of the memory location to be programmed
Addresses are latched on the falling edge of the write pulse.
SA = Address of the sector to be erased. The combination of A22, A21, A20, A19, A18, A17, A16, A15, A14, A13 and
A12 will uniquely select any sector.
BA = Bank Address. Address settled by A22, A21, A20, A19 will select Bank A, Bank B, Bank C and Bank D.
RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse.
SGA = Sector group address to be protected.
WPH = (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 0, 0, 0, 1, 0)
SD = Sector group protection verify data. Output 01h at protected sector group addresses and output
00h at unprotected sector group addresses.
HRA = Address of the HiddenROM area Word Mode : 000000h to 00007Fh
HRBA = Bank Address of the HiddenROM area (A22 = A21 = A20 = VIL)
RD (0) = Read Data bit. If protected, DQ0 = 1, if unprotected, DQ0 = 0
RD (1) = Read Data bit. If protected, DQ1 = 1, if unprotected, DQ1 = 0
OPBP = (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 1, 1, 0, 1, 0)
PWA/PWD = Password Address/Password Data
PL = (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 0, 1, 0, 1, 0)
SPML = (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 1, 0, 0, 1, 0)
WP = (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 0, 0, 0, 1, 0)
*1: This command is valid during Fast Mode.
*2: This command is valid while RESET = VID.
*3: This command is valid during HiddenROM mode.
*4: The data “00h” is also acceptable.
Notes : • Address bits A22 to A11 = X = “H” or “L” for all address commands except for
PA, SA, BA, SGA, OPBP, PWA, PL, SPML, WP, WPH.
• Bus operations are defined in this document.
• The system should generate the following address patterns:
Word Mode : 555h or 2AAh to addresses A10 to A0
• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
27
MB84VP24491HK-70
3. AC Characteristics
• Read Only Operations Characteristics (Flash) (128M Page Flash)
Symbol
Parameter
JEDEC
Standard
Read Cycle Time
tAVAV
tRC
Address to Output Delay
tAVQV
tACC
Page Read Cycle Time
—
tPRC
Page Address to Output Delay
—
tPACC
Chip Enable to Output Delay
tELQV
tCE
Output Enable to Output Delay
tGLQV
tOE
Chip Enable to Output High-Z
tEHQZ
Output Enable to Output High-Z
Output Hold Time From Address,
CEf or OE, Whichever Occurs First
Value*
Unit
Min
Max
70

ns

70
ns
20

ns
CEf = VIL
OE = VIL

20
ns
OE = VIL

70
ns
—

20
ns
tDF
—

20
ns
tGHQZ
tDF
—

20
ns
tAXQX
tOH
—
5

ns
* : Test Conditions– Output Load : 1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to VCCf
Timing measurement reference level
Input: 0.5×VCCf
Output: 0.5×VCCf
28
Test
Setup
—
CEf = VIL
OE = VIL
—
MB84VP24491HK-70
• Write/Erase/Program Operations (Flash) (128M Page Flash)
Parameter
Write Cycle Time
Address Setup Time
Address Setup Time to OE Low During
Toggle Bit Polling
Address Hold Time
Address Hold Time from CEf or OE High
During Toggle Bit Polling
Data Setup Time
Data Hold Time
Output Enable Setup Time
Read
Output Enable Hold Time
Toggle and Data Polling
Read Recover Time Before Write
Read Recover Time Before Write
(OE High to CEf Low)
CEf Setup Time
WE Setup Time
CEf Hold Time
WE Hold Time
Write Pulse Width
CEf Pulse Width
Write Pulse Width High
CEf Pulse Width High
Programming Operation
Sector Erase Operation *2
VCCf Setup Time
Rise Time to VID *3
Rise Time to VACC *4
Voltage Transition Time *3
Write Pulse Width*3
Recover Time from RY/BY
RESET Pulse Width
RESET High Level Period Before Read
Program/Erase Valid to RY/BY Delay
Delay Time from Embedded Output Enable
Erase Time-out Time
Erase Suspend Transition Time
Symbol
JEDEC Standard
tAVAV
tWC
tAS
tAVWL
Min
70
0
Value*1
Typ


Max


Unit
ns
ns
—
tASO
15


ns
tWLAX
tAH
35


ns
—
tAHT
0


ns
tDVWH
tWHDX
—
tDS
tDH
tOES
—
tOEH
tGHWL
tGHWL
30
0
0
0
10
0












ns
ns
ns
ns
ns
ns
tGHEL
tGHEL
0


ns
tELWL
tWLEL
tWHEH
tEHWH
tWLWH
tELEH
tWHWL
tEHEL
tWHWH1
tWHWH2
—
—
—
—
—
—
—
—
—
—
—
—
tCS
tWS
tCH
tWH
tWP
tCP
tWPH
tCPH
0
0
0
0
40
40
25
25


50
500
500
4
100
0
500
50


50









6
0.5






























90
70

20
ns
ns
ns
ns
ns
ns
ns
ns
µs
s
µs
ns
ns
µs
µs
ns
ns
ns
ns
ns
µs
µs
tWHWH1
tWHWH2
tVCS
tVIDR
tVACCR
tVLHT
tWPP
tRB
tRP
tRH
tBUSY
tEOE
tTOW
tSPD
*1 : Test Conditions– Output Load : 1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to VCCf
Timing measurement reference level
Input: 0.5×VCCf
Output: 0.5×VCCf
*2 : This does not include the preprogramming time.
*3 : This timing is for Sector Group Protection / Unprotection.
*4 : This timing is for Accelerated Program operation.
29
MB84VP24491HK-70
• Read Operation Timing Diagram (128M Page Flash)
tRC
Address
Address Stable
tACC
CEf
tOE
tDF
OE
tOEH
WE
tCE
Outputs
CEf : CE0f or CE1f
30
High-Z
tOH
Output Valid
High-Z
MB84VP24491HK-70
• Page Read Operation Timing Diagram (128M Page Flash)
A22 to A2
Same page Addresses
A2 to A0
Aa
Ab
Ac
tRC
tPRC
tPRC
Ad
tACC
tCE
CEf
OE
tOEH
tDF
WE
Output
tOE
High-Z
tPACC
tPACC
tPACC
tOH
tOH
tOH
Da
Db
Dc
tOH
Dd
CEf : CE0f or CE1f
31
MB84VP24491HK-70
• Hardware Reset/Read Operation Timing Diagram (128M Page Flash)
tRC
Address
Address Stable
tACC
CEf
tRH
tRP
tRH
tCE
RESET
tOH
Outputs
CEf : CE0f or CE1f
32
High-Z
Outputs Valid
MB84VP24491HK-70
• Alternate WE Controlled Program Operation Timing Diagram (128M Page Flash)
3rd Bus Cycle
Data Polling
555h
Address
tWC
PA
tAS
PA
tRC
tAH
CEf
tCS
tCH
tCE
OE
tGHWL
tWP
tOE
tWPH
tWHWH1
WE
A0h
Data
tOH
tDF
tDS tDH
PD
DQ7
DOUT
DOUT
CEf : CE0f or CE1f
Notes : •
•
•
•
•
PA is address of the memory location to be programmed.
PD is data to be programmed at word address.
DQ7 is the output of the complement of the data written to the device.
DOUT is the output of the data written to the device.
Figure indicates last two bus cycles out of four bus cycle sequence.
33
MB84VP24491HK-70
• Alternate CEf Controlled Program Operation Timing Diagram (128M Page Flash)
3rd Bus Cycle
Data Polling
555h
Address
tWC
PA
tAS
PA
tAH
WE
tWS
tWH
OE
tGHEL
tCP
tCPH
tWHWH1
CEf
tDS
Data
A0h
tDH
PD
DQ7
DOUT
CEf : CE0f or CE1f
Notes : •
•
•
•
•
34
PA is address of the memory location to be programmed.
PD is data to be programmed at word address.
DQ7 is the output of the complement of the data written to the device.
DOUT is the output of the data written to the device.
Figure indicates last two bus cycles out of four bus cycle sequence.
MB84VP24491HK-70
• Chip/Sector Erase Operation Timing Diagram (128M Page Flash)
555h
Address
tWC
2AAh
tAS
555h
555h
2AAh
SA*
tAH
CEf
tCS
tCH
OE
tGHWL
tWP
tWPH
tDS
tDH
WE
AAh
30h for Sector Erase
55h
80h
AAh
55h
10h/30h
Data
tVCS
VCCf
CEf : CE0f or CE1f
* : SA is the sector address for Sector Erase. Addresses = 555h (Word) for Chip Erase.
35
MB84VP24491HK-70
• Data Polling during Embedded Algorithm Operation Timing Diagram (128M Page Flash)
CEf
tCH
tDF
tOE
OE
tOEH
WE
tCE
*
DQ7
Data
DQ7
DQ7 =
Valid Data
High-Z
tWHWH1 or 2
DQ6 to DQ0
DQ6 to DQ0 =
Output Flag
Data
tBUSY
DQ6 to DQ0
Valid Data
tEOE
RY/BY
CEf : CE0f or CE1f
* : DQ7 = Valid Data (The device has completed the Embedded operation) .
36
High-Z
MB84VP24491HK-70
• AC Waveforms for Toggle Bit I during Embedded Algorithm Operations (128M Page Flash)
Address
tAHT tASO
tAHT tAS
CEf
tCEPH
WE
tOEPH
tOEH
tOEH
OE
tDH
DQ 6/DQ2
tOE
Toggle
Data
Data
tCE
Toggle
Data
Toggle
Data
*
Stop
Toggling
Output
Valid
tBUSY
RY/BY
CEf : CE0f or CE1f
* : DQ6 stops toggling (The device has completed the Embedded operation).
37
MB84VP24491HK-70
• Bank-to-Bank Read/Write Timing Diagram (128M Page Flash)
Address
Read
Command
Read
Command
Read
Read
tRC
tWC
tRC
tWC
tRC
tRC
BA1
BA2
(555h)
BA1
BA2
(PA)
BA1
BA2
(PA)
tAS
tACC
tAH
tAS
tAHT
tCE
CEf
tOE
tCEPH
OE
tGHWL
tDF
tOEH
tWP
WE
tDS
DQ
Valid
Output
tDH
Valid
Intput
(A0h)
tDF
Valid
Output
Valid
Intput
(PD)
Valid
Output
Status
CEf : CE0f or CE1f
Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.
BA1 : Address corresponding to Bank 1
BA2 : Address corresponding to Bank 2
38
MB84VP24491HK-70
• RY/BY Timing Diagram during Program/Erase Operation Timing Diagram (128M Page Flash)
CEf
Rising edge of the last WE signal
WE
Entire programming
or erase operations
RY/BY
tBUSY
CEf : CE0f or CE1f
• RESET, RY/BY Timing Diagram (128M Page Flash)
WE
RESET
tRP
tRB
RY/BY
tREADY
39
MB84VP24491HK-70
• Temporary Sector Group Unprotection Timing Diagram (128M Page Flash)
VCCf
tVIDR
tVCS
tVLHT
VID
VIH
RESET
CEf
WE
tVLHT
Program or Erase Command Sequence
RY/BY
Unprotection period
CEf : CE0f or CE1f
40
tVLHT
MB84VP24491HK-70
• Extended Sector Group Protection Timing Diagram (128M Page Flash)
VCCf
tVCS
RESET
tVLHT
tVIDR
tWC
Address
tWC
SGAX
SGAX
SGAY
A7, A6, A5
A4, A3, A2
A0
A1
CEf
OE
TIME-OUT
tWP
WE
Data
60h
60h
40h
01h
60h
tOE
CEf : CE0f or CE1f
SGAX : Sector Group Address to be protected
SGAY : Next Sector Group Address to be protected
TIME-OUT : Time-Out window = 250 µs (Min)
41
MB84VP24491HK-70
• Accelerated Program Timing Diagram (128M Page Flash)
VCCf
tVACCR
tVCS
tVLHT
VACC
VIH
WP/ACC
CEf
WE
tVLHT
Program Sequence
RY/BY
Acceleration period
CEf : CE0f or CE1f
42
tVLHT
MB84VP24491HK-70
4. Erase and Programing Performance (128M Page Flash)
Value
Parameter
Unit
Comments
2
s
Excludes programming time
prior to erasure
6.0
100
µs
Excludes system-level
overhead
—
50.3
200
s
Excludes system-level
overhead
100,000
—
—
cycle
Min
Typ
Max
Sector Erase Time
—
0.5
Word Programming Time
—
Chip Programming Time
Erase/Program Cycle
—
Note: Typical Erase conditions TA = + 25°C, VCC = 2.9 V
Typical Program conditions TA = + 25°C, VCC = 2.9 V, Data = checker
43
MB84VP24491HK-70
■ 32 M FCRAM CHARACTERISTICS for MCP
1. Power Down (32M Page Mode FCRAM)
• Power Down (32M Page mode FCRAM)
The Power Down is to enter low power idle state when CE2r stays Low.
The 32M page mode FCRAM has four power down mode, Sleep, 4M Partial, 8M Partial, and 16M Partial.
These can be programmed by series of read/write operation. Each mode has follwoing features.
Mode
Data Retention
Retention Address
Sleep (default)
No
N/A
4M Partial
4M bit
00000h to 3FFFFh
8M Partial
8M bit
00000h to 7FFFFh
16M Partial
16M bit
00000h to FFFFFh
The default state is Sleep and it is the lowest power consumption but all data will be lost once CE2r is brought
to Low for Power Down. It is not required to program to Sleep mode after power-up.
• Power Down Program Sequence (32M Page mode FCRAM)
The program requires total 6 read/write operation with unique address and data. Between each read/write
operation requires that device be in standby mode. Following table shows the detail sequence.
Cycle #
Operation
Address
Data
1st
Read
1FFFFFh (MSB)
Read Data (RDa)
2nd
Write
1FFFFFh
RDa
3rd
Write
1FFFFFh
RDa
4th
Write
1FFFFFh
0000h
5th
Write
1FFFFFh
Data Key
6th
Read
Address Key
Read Data (RDb)
The first cycle is to read from most significient address (MSB).
The second and third cycle are to write back the data (RDa) read by first cycle. If the third cycle is written into
the different address, the program is cancelled and the data written by the second or third cycle is valid as a
normal write operation.
The forth and fifth cycle is to write the data key for program. The data of forth cycle must be all 0’s and data of
fifth cycle is a data key for mode selection. If the forth cycle is written into different address, the program is also
cancelled.
The last cycle is to read from specific address key for mode selection. The both data key written by fifth cycle
and address key must be the same mode for proper programming.
Once this program sequence is performed from a Partial mode to other Partial mode, the write data may be lost.
So, it should perform this program prior to regular read/write operation if Partial mode is used.
44
MB84VP24491HK-70
• Address Key (32M Page mode FCRAM)
The address key has following format.
Address
Mode
A20
A19
A18 to A0
Binary
Sleep (default)
1
1
1
1FFFFFh
4M Partial
0
1
1
0FFFFFh
8M Partial
1
0
1
17FFFFh
16M Partial
0
0
1
07FFFFh
• Data Key (32M Page mode FCRAM)
The data key has following format.
Mode
Data
DQ15 to DQ8
DQ7 to DQ2
DQ1
DQ0
Sleep (default)
0
0
1
1
4M Partial
0
0
1
0
8M Partial
0
0
0
1
16M Partial
0
0
0
0
The upper byte of data code may be ignored and it is just for recommendation to write 0’s to upper byte for future
compatibility.
45
MB84VP24491HK-70
2. AC Characteristics
• READ OPERATION (32M Page mode FCRAM)
Value
Parameter
Symbol
Min
Max
Unit
Remarks
Read Cycle Time
tRC
70
1000
ns
*1, *2
CE1r Access Time
tCE
—
70
ns
*3
OE Access Time
tOE
—
40
ns
*3
Address Access Time
tAA
—
70
ns
*3, *5
LB / UB Access Time
tBA
—
30
ns
*3
Page Address Access Time
tPAA
—
18
ns
*3, *6
Page Read Cycle Time
tPRC
25
1000
ns
*1, *6, *7
Output Data Hold Time
tOH
5
—
ns
*3
CE1r Low to Output Low-Z
tCLZ
3
—
ns
*4
OE Low to Output Low-Z
tOLZ
0
—
ns
*4
LB / UB Low to Output Low-Z
tBLZ
0
—
ns
*4
CE1r High to Output High-Z
tCHZ
—
20
ns
*4
OE High to Output High-Z
tOHZ
—
20
ns
*4
LB / UB High to Output High-Z
tBHZ
—
20
ns
*4
Address Setup Time to CE1r Low
tASC
–5
—
ns
Address Setup Time to OE Low
tASO
10
—
ns
Address Invalid Time
tAX
—
10
ns
*5, *8
Page Address Invalid Time
tAXP
—
10
ns
*6, *8
Address Hold Time from CE1r High
tCHAH
–5
—
ns
*9
Address Hold Time from OE High
tOHAH
–5
—
ns
tCP
15
—
ns
CE1r High Pulse Width
*1 : Maximum value is applicable if CE1r is kept at Low without change of address input of A20 to A3.
If needed by system operation, please contact local FUJITSU representative for the relaxation of 1 µs limitation.
*2 : Address should not be changed within minimum tRC.
*3 : The output load 30 pF.
*4 : The output load 5 pF without any other load.
*5 : Applicable to A20 to A3 when CE1r is kept at Low.
*6 : Applicable only to A2, A1 and A0 when CE1r is kept at Low for the page address access.
*7 : In case Page Read Cycle is continued with keeping CE1r stays Low, CE1r must be brought to High within 4 µs.
In other words, Page Read Cycle must be closed within 4 µs.
*8 : Applicable when at least two of address inputs among applicable are switched from previous state.
*9 : tRC(Min) and tPRC(Min) must be satisfied.
46
MB84VP24491HK-70
• WRITE OPERATION (32M Page mode FCRAM)
Value
Parameter
Symbol
Min
Max
Unit
Remarks
Write Cycle Time
tWC
70
1000
ns
*1, *2
Address Setup Time
tAS
0
—
ns
*2
CE1r Write Pulse Width
tCW
45
—
ns
*3
WE Write Pulse Width
tWP
45
—
ns
*3
LB / UB Write Pulse Width
tBW
45
—
ns
*3
CE1r Write Recovery Time
tWRC
15
—
ns
*4
WE Write Recovery Time
tWR
15
1000
ns
*4
LB / UB Write Recovery Time
tBR
15
1000
ns
*4
Data Setup Time
tDS
20
—
ns
Data Hold Time
tDH
0
—
ns
Address Invalid Time after Write
tAXW
—
10
ns
*5
OE High to CE1r Low Setup Time for
Write
tOHCL
–5
—
ns
*6
OE High to Address Setup Time
for Write
tOES
0
—
ns
*7
LB and UB Write Pulse Overlap
tBWO
20
—
ns
CE1r High Pulse Width
tCP
15
—
ns
*1 : Maximum value is applicable if CE1r is kept at Low without any address change. If the relaxation is needed by
system operation, please contact local FUJITSU representative for the relaxation of 1 µs limitation.
*2 : Minimum value must be equal or greater than the sum of write pulse (tCW, tWP or tBW) and write recovery time
(tWRC, tWR or tBR).
*3 : Write pulse is defined from High to Low transition of CE1r, WE, or LB / UB, whichever occurs last.
*4 : Write recovery is defined from Low to High transition of CE1r, WE, or LB / UB, whichever occurs first.
*5 : Applicable to any address change when CE1r stays Low.
*6 : If OE is Low after minimum tOHCL, read cycle is initiated. In other word, OE must be brought to High within 5ns
after CE1r is brought to Low. Once read cycle is initiated, new write pulse should be input after minimum tRC
is met.
*7 : If OE is Low after new address input, read cycle is initiated. In other word, OE must be brought to High at the
same time or before new address valid. Once read cycle is initiated, new write pulse should be input after
minimum tRC is met.
47
MB84VP24491HK-70
• POWER DOWN PARAMETERS (32M Page mode FCRAM)
Value
Parameter
Symbol
Unit
Min
Max
Remarks
CE2r Low Setup Time for Power Down Entry
tCSP
10
—
ns
CE2r Low Hold Time after Power Down Entry
tC2LP
70
—
ns
CE1r High Hold Time following CE2r High
after Power Down Exit [SLEEP mode only]
tCHH
300
—
µs
*1
CE1r High Hold Time following CE2r High
after Power Down Exit [not in SLEEP mode]
tCHHP
1
—
µs
*2
CE1r High Setup Time following CE2r High
after Power Down Exit
tCHS
0
—
ns
*1 : Applicable also to power-up.
*2 : Applicable when 4M, 8M, and 16M Partial mode is programmed.
• OTHER TIMING PARAMETERS (32M Page mode FCRAM)
Value
Parameter
Symbol
Unit
Min
Max
CE1r High to OE Invalid Time for Standby Entry
tCHOX
10
—
ns
CE1r High to WE Invalid Time for Standby Entry
tCHWX
10
—
ns
CE1r High Hold Time following CE2r High after Power-up
tCHH
300
—
µs
tT
1
25
ns
Input Transition Time
Remarks
*1
*2
*1 : Some data might be written into any address location if tCHWX(Min) is not satisfied.
*2 : The Input Transition Time (tT) at AC testing is 5 ns as shown in below. If actual tT is longer than 5ns,
it may violate AC specification of some timing parameters.
• AC TEST CONDITIONS (32M Page mode FCRAM)
Description
Symbol
Test Setup
Value
Unit
Input High Level
VIH
—
VCCr
V
Input Low Level
VIL
—
VSS
V
VREF
—
VCCr × 0.5
V
tT
Between VIL and VIH
5
ns
Input Timing Measurement Level
Input Transition Time
48
Remarks
MB84VP24491HK-70
• READ Timing #1 (Basic Timing) (32M Page FCRAM)
tRC
Address Valid
Address
tASC
tCHAH
tCE
CE1r
tASC
tCP
tCHZ
tOE
OE
tOHZ
tBA
LB / UB
tBHZ
tBLZ
tOLZ
DQ
(Output)
tOH
tCLZ
Valid Data Output
Note : CE2r and WE must be High for entire read cycle.
49
MB84VP24491HK-70
• READ Timing #2 (OE & Address Access) (32M Page FCRAM)
tAx
tRC
Address
Address Valid
Address Valid
tAA
CE1r
tRC
tAA
tOHAH
Low
tASO
tOE
OE
LB / UB
tOHZ
tOLZ
tOH
tOH
DQ
(Output)
Valid Data Output
Note : CE2r and WE must be High for entire read cycle.
50
Valid Data Output
MB84VP24491HK-70
• READ Timing #3 (LB / UB Byte Access) (32M Page FCRAM)
tAX
tRC
Address
tAx
Address Valid
tAA
CE1r, OE
Low
tBA
tBA
LB
tBA
UB
tBHZ
tBHZ
tOH
tBLZ
tBLZ
tOH
DQ7 to DA0
(Output)
Valid Data
Output
Valid Data
Output
tBLZ
tBHZ
tOH
DQ15 to DQ8
(Output)
Valid Data Output
Note : CE2r and WE must be High for entire read cycle.
51
MB84VP24491HK-70
• READ Timing #4 (Page Address Access after CE1r Control Access) (32M Page FCRAM)
tRC
Address
(A20 to A3)
Address Valid
tRC
Address
(A2 to A0)
Address Valid
tPRC
tPRC
Address
Valid
Address
Valid
tPAA
tPAA
tASC
tPRC
Address
Valid
tPAA
tCHAH
CE1r
tCE
tCHZ
OE
LB / UB
tCLZ
tOH
tOH
tOH
DQ
(Output)
Valid Data Output
(Normal Access)
Note : CE2r and WE must be High for entire read cycle.
52
Valid Data Output
(Page Access)
tOH
MB84VP24491HK-70
• READ Timing #5 (Random and Page Address Access) (32M Page FCRAM)
tRC
Address
(A20 to A3)
tAX
Address
(A2 to A0)
tPRC
tPAA
tAA
tPRC
tRC
Address
Valid
Address
Valid
tAx
Address Valid
Address Valid
tRC
CE1r
tRC
Address
Valid
Address
Valid
tAA
tPAA
Low
tASO
tOE
OE
tBA
LB / UB
DQ
(Output)
tOLZ
tBLZ
tOH
Valid Data Output
(Normal Access)
tOH
tOH
tOH
Valid Data Output
(Page Access)
Note : CE2r and WE must be High for entire read cycle.
Either or both LB and UB must be Low when both CE1r and OE are Low.
53
MB84VP24491HK-70
• WRITE Timing #1 (Basic Timing) (32M Page FCRAM)
tWC
Address
Address Valid
tAS
tWRC
tCW
tAS
CE1r
tAS
tWR
tWP
tAS
WE
tAS
tBR
tBW
LB, UB
tOHCL
OE
tDS
tDH
DQ
(Input)
Valid Data Input
Note : CE2r must be High for write cycle.
54
tAS
MB84VP24491HK-70
• WRITE Timing #2 (WE Control) (32M Page FCRAM)
tWC
tWC
Address Valid
Address
Address Valid
tOHAH
CE1r
Low
tAS
tWP
tWR
tAS
tWP
tWR
WE
LB, UB
tOES
OE
tOHZ
tDS
tDH
tDS
tDH
DQ
(Input)
Valid Data Input
Valid Data Input
Note : CE2r must be High for write cycle.
55
MB84VP24491HK-70
• WRITE Timing #3-1 (WE / LB / UB Byte Write Control) (32M Page FCRAM)
tWC
Address Valid
Address
CE1r
tWC
Address Valid
Low
tAS
tWP
tAS
tWP
WE
tBR
LB
tBR
UB
tDS
tDH
DQ7 to DQ0
(Input)
Valid Data Input
tDS
tDH
DQ15 to DQ8
(Input)
Valid Data Input
Note : CE2r must be High for write cycle.
56
MB84VP24491HK-70
• WRITE Timing #3-2 (WE / LB / UB Byte Write Control) (32M Page FCRAM)
tWC
Address Valid
Address
CE1r
tWC
Address Valid
Low
tWR
tWR
WE
tAS
tBW
LB
tAS
tBW
UB
tDS
tDH
DQ7 to DQ0
(Input)
Valid Data Input
tDS
tDH
DQ15 to DQ8
(Input)
Valid Data Input
Note : CE2r must be High for write cycle.
57
MB84VP24491HK-70
• WRITE Timing #3-3 (WE / LB / UB Byte Write Control) (32M Page FCRAM)
tWC
Address Valid
Address
CE1r
tWC
Address Valid
Low
WE
tAS
tBW
tBR
LB
tAS
tBW
tBR
UB
tDS
tDH
DQ7 to DQ0
(Input)
Valid Data Input
tDS
tDH
DQ15 to DQ8
(Input)
Valid Data Input
Note : CE2r must be High for write cycle.
58
MB84VP24491HK-70
• WRITE Timing #3-4 (WE / LB / UB Byte Write Control) (32M Page FCRAM)
tWC
Address Valid
Address
CE1r
tWC
Address Valid
Low
WE
tAS
tBW
tBR
tAS
tBW
tBR
LB
tBWO
tDS
DQ7 to DQ0
(Input)
tDH
tDS
Valid
Data Input
tAS
tBW
tDH
Valid
Data Input
tBR
tAS
tBWO
tBW
tBR
UB
tDS
DQ15 to DQ8
(Input)
Valid
Data Input
tDH
tDS
tDH
Valid
Data Input
Note : CE2r must be High for write cycle.
59
MB84VP24491HK-70
• READ / WRITE Timing #1-1 (CE1r Control) (32M Page FCRAM)
tWC
Address
tRC
Write Address
tCHAH
tAS
Read Address
tWRC
tASC
tCW
tCE
tCHAH
CE1r
tCP
tCP
WE
UB, LB
tOHCL
OE
tCHZ
tOH
tDS
tDH
DQ
Read Data Output
Write Data Input
Note : Write address is valid from either CE1r or WE of last falling edge.
60
tCLZ
tOH
MB84VP24491HK-70
• READ / WRITE Timing #1-2 (CE1r / WE / OE Control) (32M Page FCRAM)
tWC
Address
tRC
Write Address
tCHAH
tAS
Read Address
tWR
tASC
tCHAH
tCE
CE1r
tCP
tCP
tWP
WE
UB, LB
tOHCL
tOE
OE
tCHZ
tOH
tDS
tDH
tOLZ
tOH
DQ
Read Data Output
Write Data Input
Read Data Output
Note : OE can be Low fixed in write operation under CE1r control RD-WR-RD operation.
61
MB84VP24491HK-70
• READ / WRITE Timing #2 (OE, WE Control) (32M Page FCRAM)
tWC
Address
tRC
Write Address
Read Address
tAA
tOHAH
CE1r
tOHAH
Low
tAS
tWR
tWP
WE
tOES
UB, LB
tASO
tOE
OE
tOHZ
tOH
tOHZ
tDS
tDH
tOLZ
tOH
DQ
Read Data Output
Write Data Input
Note : CE1r can be tied to Low for WE and OE controlled operation.
When CE1r is tied to Low, output is exclusively controlled by OE.
62
Read Data Output
MB84VP24491HK-70
• READ / WRITE Timing #3 (OE, WE, LB, UB Control) (32M Page FCRAM)
tWC
Address
tRC
Write Address
Read Address
tAA
tOHAH
CE1r
tOHAH
Low
WE
tOES
tAS
tBW
tBR
tBA
UB, LB
tASO
tBHZ
OE
tBHZ
tOH
tDS
tDH
tBLZ
tOH
DQ
Read Data Output
Write Data Input
Read Data Output
Note : CE1r can be tied to Low for WE and OE controlled operation.
When CE1r is tied to Low, output is exclusively controlled by OE.
63
MB84VP24491HK-70
• POWER-UP Timing (32M Page FCRAM)
CE1r
tCHH
CE2r
VCCr
VCCr Min
0V
Note : The tCHH specifies after VCCr reaches specified minimum level and applicable both CE1r and CE2r.
• POWER DOWN Entry and Exit Timing
CE1r
tCHS
CE2r
tCSP
tC2LP
tCHH (tCHHP)
High-Z
DQ
Power Down Entry
Power Down Mode
Power Down Exit
Note : This Power Down mode can be also used as a reset timing if POWER-UP timing above could not be satisfied
and Power-Down program was not performed prior to this reset.
• Standby Entry Timing after Read or Write (32M Page FCRAM)
CE1r
tCHOX
tCHWX
OE
WE
Active (Read)
Standby
Active (Write)
Standby
Note : Both tCHOX and tCHWX define the earliest entry timing for Standby mode.
If either of timing is not satisfied, it takes tRC (Min) period for Standby mode from CE1r Low to High transition.
64
MB84VP24491HK-70
• POWER DOWN PROGRAM Timing (32M Page FCRAM)
Address
tRC
tWC
tWC
MSB*1
MSB*1
MSB*1
tCP
tCP
tWC
tWC
MSB*1
tCP
tRC
MSB*1
tCP
Key*2
tCP
tCP*4
CE1r
OE
WE
LB, UB
DQ*3
RDa
Cycle #1
RDa
Cycle #2
RDa
Cycle #3
00
Cycle #4
Key*3
Cycle #5
RDb
Cycle #6
*1 : The all address inputs must be High from Cycle #1 to #5.
*2 : The address key must confirm the format specified in “■ 32 M FCRAM CHARACTERISTICS for MCP 1. Power
Down Program Timing (32 M Page FCRAM) ”. If not, the operation and data are not guaranteed.
*3 : The data key must confirm the format specified in “■ 32 M FCRAM CHARACTERISTICS for MCP 1. Power
Down Program Timing (32 M Page FCRAM) ”. If not, the operation and data are not guaranteed.
*4 : After tCP following Cycle #6, the Power Down Program is completed and returned to the normal operation.
65
MB84VP24491HK-70
■ PIN CAPACITANCE
Parameter
Symbol
Condition
Value
Min
Typ
Max
Unit
Input Capacitance
CIN
VIN = 0

11.0
14.0
pF
Output Capacitance
COUT
VOUT = 0

12.0
16.0
pF
Control Pin Capacitance
CIN2
VIN = 0

14.0
16.0
pF
WP/ACC Pin Capacitance
CIN3
VIN = 0

21.5
26.0
pF
Note: Test conditions TA = + 25°C, f = 1.0 MHz
■ HANDLING OF PACKAGE
Please handle this package carefully since the sides of package create acute angles.
■ CAUTION
• The high voltage (VID) cannot apply to address pins and control pins except RESET. Exception is when
autoselect and sector group protect function are used, then the high voltage (VID) can be applied to RESET.
• Without the high voltage (VID) , sector group protection can be achieved by using “Extended Sector Group
Protection” command.
66
MB84VP24491HK-70
■ ORDERING INFORMATION
MB84VP24491
HK
-70
PBS
Package Type
PBS = 73-ball FBGA
Speed Option
Device Revision
Device Number/Description
128Mega-bit (4M × 16-bit + 4M × 16-bit) Dual Operation Flash Memory
Dual Chip Enable
3.0V-only Read, Program, and Erase
32Mega-bit(2M × 16-bit) Mobile FCRAM
67
MB84VP24491HK-70
■ PACKAGE DIMENSION
73-ball plastic FBGA
(BGA-73P-M03)
11.60±0.10(.457±.004)
0.20(.008) S B
B
+0.15
+.006
1.19 –0.10 .047 –.004
(Seated height)
0.80(.031)
REF
0.40(.016)
REF
10
9
0.80(.031)
REF
8
7
A
6
8.00±0.10
(.315±.004)
5
0.40(.016)
REF
4
3
0.10(.004) S
2
1
INDEX-MARK AREA
0.39±0.10
(Stand off)
(.015±.004)
M
L
K
J
H
G
F
E
D
S
C
B
A
INDEX BALL
0.20(.008) S A
73-ø0.45
73-ø0.18
+0.10
–.005
+.004
–.002
ø0.08(.003)
M
S AB
0.10(.004) S
C
2003 FUJITSU LIMITED B73003S-c-1-1
Dimensions in mm (inches) .
Note : The values in parentheses are reference values.
68
MB84VP24491HK-70
FUJITSU LIMITED
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 FUJITSU LIMITED Printed in Japan