FUJITSU SEMICONDUCTOR DATA SHEET DS04-22002-1E ASSP Communication Control IEEE 1394 Bus Controller (for DVC) MB86615 ■ DESCRIPTION The MB86615 is 1394 serial bus controller compatible with the IEEE 1394 “FireWire” standard (IEEE Standard 1394-1995). One built-in port plus a differential transceiver and comparator are provided to enable formation of networks in a 1394 cable environment. The MB86615 supports s100 data transfer speeds. By integrating the physical layer and link layer on one chip, The MB86615 is designed to reduce mounting area as well as power consumption. The MB86615 has an exclusive data port for isochronous transfer, provides automatic packetizing for sending and separation of header and data units at receiving, and is optimized for continuity of transfer processing. The MB86615 supports DVC AV/C protocols, and includes the necessary built-in automatic operations and CSR’s for providing the necessary operations for DVC data transfer. ■ FEATURES • • • • • • • Compatible with IEEE 1394 high-performance serial bus standards Physical layer and link layer integrated on one chip 1 cable ports Supports s100 transfer speed (98.304 Mbit/sec) 3.3V single power supply operation Built-in PLL (for crystal oscillator) for internal clock signal generation Power saving modes 1) Forced sleep mode at instruction from MPU 2) Automatic sleep mode for non-connected ports • Header and data units automatically separated at receiving and automatic packetizing for sending • Supports cycle master functions (Continued) ■ PACKAGES 100-pin plastic LQFP 120-pin plastic FBGA (FPT-100P-M05) (BGA-120P-M01) MB86615 (Continued) • Built-in CSR’s to provide isochronous resource manager functions • 32-bit CRC generation and check functions • General purpose port for asynchronous transfer and control (16-bit MPU/DMA common bus) • Exclusive built-in ports for isochronous transfer (8-bit bus) • Built-in CRS’s and automatic processes to support DVC 1) Automatic separation of CIP headers at receiving, and automatic packetizing at sending. 2) Automatic generation and match detection of time stamp by FP signal. 3) DBC area automatic increment function 4) No-data packet sending and receiving 5) On-chip PCR (input/output 1 channel each) 6) Each CSR with automatic C&S lock processing and read processing • Compatible with 4-core cable • Packages: LQFP-100, FBGA-120 2 MB86615 ■ PIN ASSIGNMENTS MODE0 TEST5 FP ICRCE IV ILWRE IDIR ICLK VDD VSS ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 TEST4 TEST3 VSS VDD TEST2 TEST1 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 100 MODE1 1. LQFP-100 74 AVSS VDD 3 73 N.C. VSS 4 72 N.C. ALE 5 71 N.C. D15 6 70 N.C. D14 7 69 AVDD D13 8 68 AVSS D12 9 67 N.C. D11 10 66 AVDD D10 11 65 AVSS D9 12 64 N.C. D8 13 63 AVSS VDD 14 62 AVDD VSS 15 61 TPA D7 16 60 TPB D6 17 59 TPA AD5 18 58 TPB AD4 19 57 AVSS AD3 20 56 AVDD AD2 21 55 TPBIAS AD1 22 54 AVSS D0 23 53 AVDD VDD 24 52 ROI VSS 25 51 N.C. N.C. DREQ DACK VDD VSS X0 X1 TESTP AVSS AVDD VCOIN CHPO ROP AVSS AVDD RD (R/W) VDD VSS CS A5 A4 A3 A2 A1 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 2 27 28 29 30 31 32 33 34 35 75 AVDD INT WR (DS) 26 RESET 1 (FPT-100P-M05) 3 MB86615 2. FBGA-120 13 12 11 10 9 8 7 6 5 4 3 2 1 N.C. AVDD AVSS VCOIN TESTP XO DACK N.C. A3 A5 VDD N.C. WR (DS) N N.C. ROI N.C. CHPO AVSS X1 VDD DREQ A2 A4 VSS RD (R/W) VSS M AVDD AVSS TPBIAS ROP AVDD N.C. VSS N.C. A1 N.C. CS N.C. VDD L AVDD AVSS TPB D0 AD1 AD2 K TPA TPB N.C. AD3 AD4 AD5 J TPA AVDD AVSS D6 N.C. D7 I N.C. N.C. AVSS VSS VDD D8 H AVDD N.C. N.C. N.C. D9 D10 G AVSS AVDD N.C. D11 D12 N.C. E N.C. N.C. N.C. D13 D14 D15 D N.C. AVSS TEST3 ID7 ID4 ID1 VSS IDIR IV TEST5 ALE VSS VDD C AVDD TEST2 VSS N.C. ID5 ID2 ID0 ICLK N.C. FP N.C. INT N.C. B TEST1 N.C. VDD TEST4 ID6 ID3 N.C. VDD ILWRE ICRCE MODE 0 MODE 1 RESET A TOP VIEW 1 pin 4 MB86615 ■ PIN LIST 1. LQFP-100 NO. I/O Pin Name NO. I/O Pin Name 1 ID I RESET 34 36 ID — N.C. A2 2 O INT 35 37 ID O DREQ A1 3 — VDD 36 38 IU I PMODE DACK 4 — VSS 37 39 — O CTR VDD 5 ID I ALE 38 40 — O OCLK VSS 6 ID/O IU/O D15 39 41 I/O — V X0 DD 7 ID/O IU/O D14 40 42 — I V X1 SS 8 ID/O IU/O D13 41 43 I/O O TESTP X0 9 ID/O IU/O D12 42 44 — I AV X1SS 10 ID/O IU/O D11 43 45 — TESTP AVDD 11 ID/O IU/O D10 44 46 — I VCOIN AVSS 12 ID/O IU/O D9 45 47 — O CHPO AVDD 13 ID/O IU/O D8 46 48 O I VCOIN ROP 14 — VDD 47 49 — O CHPO AVSS 15 — VSS 48 50 — O AV ROP DD 16 ID/O IU/O D7 49 51 — AV N.C. SS 17 ID/O IU/O D6 50 52 — O AV ROI DD 18 ID/O IU/O AD5 51 53 — AV N.C. DD 19 ID/O IU/O AD4 52 54 — O AV RO1 SS 20 ID/O IU/O AD3 53 55 — O TPBIAS AVDD 21 ID/O IU/O AD2 54 56 — AVDD SS 22 ID/O IU/O AD1 55 57 — O TAPBIAS1 AVSS 23 ID/O IU/O D0 56 58 I/O — AV TPB DD 24 — VDD 57 59 I/O — AV TPA SS 25 — VSS 58 60 I/O TPB1 TPB 26 ID I WR WR(XDS) (DS) 59 61 I/O TPA1 TPA 27 ID I RD (R/W) 60 62 I/O — TPB1 AVDD 28 — VDD 61 63 I/O — TPA1 AVSS 29 — VSS 62 64 — RO0 N.C. 30 ID I CS 63 65 — AVDD SS 31 ID I A5 64 66 — O AVDD SS 32 ID I A4 65 67 — RO0 N.C. 33 ID I A3 66 68 — AVDD SS 34 — I V A2 DD 57 69 — AVDD 35 — I V A1 SS 58 70 I/O — TPB1 N.C. (Continued) 5 MB86615 (Continued) 6 NO. I/O Pin Name NO. I/O Pin Name 71 — N.C. 86 I/O ID3 72 — N.C. 87 I/O ID2 73 — N.C. 88 I/O ID1 74 — AVSS 89 I/O ID0 75 — AVDD 90 — VSS 76 IU/O TEST1 91 — VDD 77 IU/O TEST2 92 I ICLK 78 — VDD 93 I IDIR 79 — VSS 94 O ILWRE 80 IU/O TEST3 95 I IV 81 IU/O TEST4 96 O ICRCE 82 I/O ID7 97 I/O FP 83 I/O ID6 98 O TEST5 84 I/O ID5 99 I MODE0 85 I/O ID4 100 I MODE1 MB86615 2. FBGA-120 Pin No. Ball No. I/O Pin Name Pin No. Ball No. I/O Pin Name Pin No. Ball No. I/O Pin Name 1 A1 I RESET 37 N4 I A5 73 H13 I/O TPA 2 B1 — N.C. 38 M4 I A4 74 H12 — AVDD 3 B2 O INT 39 L4 — N.C. 75 H11 — AVSS 4 C1 — VDD 40 N5 I A3 76 G13 — N.C. 5 C2 — VSS 41 M5 I A2 77 G12 — N.C. 6 C3 I ALE 42 L5 I A1 78 G11 — AVSS 7 D1 IU/O D15 43 N6 — N.C. 79 F13 — AVDD 8 D2 IU/O D14 44 M6 O DREQ 80 F12 — N.C. 9 D3 IU/O D13 45 L6 — N.C. 81 F11 — N.C. 10 E1 — N.C. 46 N7 I DACK 82 E13 — AVSS 11 E2 IU/O D12 47 M7 — VDD 83 E12 — AVDD 12 E3 IU/O D11 48 L7 — VSS 84 E11 — N.C. 13 F1 IU/O D10 49 N8 I/O X0 85 D13 — N.C. 14 F2 IU/O D9 50 M8 I X1 86 D12 — N.C. 15 F3 — N.C. 51 L8 — N.C. 87 D11 — N.C. 16 G1 IU/O D8 52 N9 O TESTP 88 C13 — N.C. 17 G2 — VDD 53 M9 — AVSS 89 C12 — AVSS 18 G3 — VSS 54 L9 — AVDD 90 B13 — AVDD 19 H1 IU/O D7 55 N10 I VCOIN 91 A13 IU/O TEST1 20 H2 — N.C. 56 M10 O CHPO 92 A12 — N.C. 21 H3 IU/O D6 57 L10 O ROP 93 B12 IU/O TEST2 22 J1 IU/O AD5 58 N11 — AVSS 94 A11 — VDD 23 J2 IU/O AD4 59 M11 — N.C. 95 B11 — VSS 24 J3 IU/O AD3 60 N12 — AVDD 96 C11 IU/O TEST3 25 K1 IU/O AD2 61 N13 — N.C. 97 A10 IU/O TEST4 26 K2 IU/O AD1 62 M13 — N.C. 98 B10 — N.C. 27 K3 IU/O D0 63 M12 O ROI 99 C10 I/O ID7 28 L1 — VDD 64 L13 — AVDD 100 A9 I/O ID6 29 L2 — N.C. 65 L12 — AVSS 101 B9 I/O ID5 30 M1 — VSS 66 L11 O TPBIAS 102 C9 I/O ID4 31 N1 I WR (DS) 67 K13 — AVDD 103 A8 I/O ID3 32 N2 — N.C. 68 K12 — AVSS 104 B8 I/O ID2 33 M2 I RD (R/W) 69 K11 I/O TPB 105 C8 I/O ID1 34 N3 — VDD 70 J13 I/O TPA 106 A7 — N.C. 35 M3 — VSS 71 J12 I/O TPB 107 B7 I/O ID0 36 L3 I CS 72 J11 — N.C. 108 C7 — VSS (Continued) 7 MB86615 (Continued) 8 Pin No. Ball No. I/O Pin Name Pin No. Ball No. I/O Pin Name Pin No. Ball No. I/O Pin Name 109 A6 — VDD 113 B5 — N.C. 117 C4 O TEST5 110 B6 I ICLK 114 C5 I IV 118 A3 I MODE0 111 C6 I IDIR 115 A4 O ICRCE 119 B3 — N.C. 112 A5 O ILWRE 116 B4 I/O FP 120 A2 I MODE1 MB86615 ■ PIN DESCRIPTION 1. 1394 Interface Pin name I/O Function TPA I/O 1394 Cable port TPA positive signal I/O pin TPA I/O 1394 Cable port TPA negative signal I/O pin TPB I/O 1394 Cable port TPB positive signal I/O pin TPB I/O 1394 Cable port TPB negative signal I/O pin TPBIAS O 1394 Cable port common voltage reference voltage output pin ROI O Connect to GND through 4.7 kΩ resistance 2. Isochronous-data Interface Pin name I/O ICLK I IDIR I Function Isochronous data interface CLK signal input pin (4 MHz to 16 MHz). Isochronous transfer transmission/reception switching signal input pin. 0 input: The device clears the ISO-FIFO buffer and enters the transmission mode. The device asserts the ILWRE signal and starts transmission after receiving one packet of data according to the “data-length” setting (bank 0: 10h). 1 input: The device clears the ISO-FIFO buffer and enters the reception mode. If any packet being transmitted exists, the device enters the reception mode after completing transmission of the packet. The ILWRE signal is asserted upon reception of one packet. Note: The IDIR signal should normally be left at “1” and switched to “0” only for transmission. ILWRE O ISO-FIFO access enable signal output pin. Transmission mode: The signal is asserted when the FIFO buffer is not full. The signal is negated when the FIFO buffer becomes full. When it is negated, data is accepted only up to the rising edge of the next ICLK signal. When a bus reset is detected, the signal is negated after accepting data of up to the packet boundary. After the bus reset, the signal is asserted again upon completion of transmission of one source packet remaining in the FIFO buffer. Reception mode: The signal is asserted upon completion of one packet of data. The signal is negated once when one packet of data is read from the FIFO buffer and asserted back if the FIFO buffer still contains any packet of data which has been received completely. ID7 to ID0 I/O Isochronous transfer data input/output bits. (MSB is ID7, LSB is ID0) IV I ID7 to ID0 enable signal input pin Transmission mode: While the IV signal is active, data from the ID7 to ID0 pins is loaded into the ISO-FIFO buffer at the rising edge of the ICLK signal. Reception mode: While the signal becomes active, the device starts sending data from the ISO-FIFO buffer to the ID7 to ID0 pins. Data is then switched at the rising edge of the ICLK signal. (Continued) 9 MB86615 (Continued) Pin name I/O Function ICREC O This pin outputs a signal indicating that data sent in the reception mode is data in a packet from which a data-CRC error has been detected. I/O Time stamp trigger signal I/O pin. Transmission mode: This pin inputs the time stamp trigger signal. The value in the internal cycle timer register is fetched upon detection of the falling edge of the FP signal. Reception mode: Time stamp match detection signal output pin. FP 3. System Interface 10 Pin name I/O Function CS I Input pin for signals used by the MPU to select the MB86615 as an I/O device. A5 to A1 I Address input pins for internal register selection. Valid only in non-multiplexed mode. If multiplexed mode is selected these pins should be fixed at ‘0’. D15 to D6, D0 I/O 16-bit data bus input/output pins (MSB is D15, LSB is D0). AD5 to AD1 I/O 16-bit data bus input/output pins (MSB is AD5, LSB is AD1). Used for address input signals when multiplexed mode is selected. RD (R/W) I 80-series mode: Read strobe signal input pin, used to output data from the MB86615 to the data bus. 68-series mode: Control signal input pin, used for data input/output operations to the MB86615. WR (DS) I 80-series mode: Write strobe signal input pin, used to input data from the data bus to the MB86615. 68-series mode: DS signal input pin, output when data bus is enabled. ALE I ALE signal input pin, for signal output when addresses are enabled in multiplexed mode. In non-multiplexed mode, this signal should be fixed at ‘0’. DREQ O This pin outputs the DMA transfer request signal to the DMAC for asynchronous transfer in DMA mode. The signal requests DMA transfer between the device and memory. DACK I This pin inputs the DMA enable signal from the DMAC for asynchronous transfer in DMA mode. INT O Interrupt output pin. MB86615 4. Other Pin name I/O Function X0 I/O X1 I VCOIN I VCO input pin for internal PLL. CHPO O Charge pump output pin for internal PLL. ROP O Connect to GND through 4.7 kΩ resistance. RESET I Reset signal input pin. The device enters the forced sleep mode automatically upon detection of the RESET signal asserted. MODE0 I Input ‘0’ for 80-series mode. Input ‘1’ for 68-series mode. MODE1 I Input ‘0’ for non-multiplexed mode. Input ‘1’ for multiplexed mode. TESTP O Test pin. Do not connect. TEST1 to TEST4 IU/O Test pin. Do not connect. TEST5 O Test pin. Do not connect. AVDD — Analog power supply AVSS — Analog ground VDD — Digital power supply VSS — Digital ground N.C. — Unused pin. Do not connect. External crystal connection pins for oscillator circuits. 11 MB86615 ■ BLOCK DIAGRAM IDIR ISO sending packet processing ICLK ICRCE ISO receiving packet processing ASYNC send-only FIFO (128 byte) ASYNC sending packet processing ASYNC receive-only FIFO (128 byte) ASYNC receiving packet processing LINK layer control circuit PHY layer control circuit A5 to A1 AD5 to AD1 RD (R/W) WR (DS) ALE System & asynchronous interface D15 to D6, D0 Transaction control circuit block Cycle master Dedicated transaction control circuit block INT DREQ DACK 12 TPA TPB TPB TPBIAS FP CS 1394 interface IV Isochronous interface ID7 to ID0 ISO sending/receiving FIFO (1kB) ILWRE TPA Register block CSR PLL circuit MB86615 ■ BLOCK DESCRIPTIONS • PHY Layer Control Circuit This block contains the IEEE 1394 physical layer control circuits. Both asynchronous transfer and isochronous transfer in a cable environment are supported. The transfer speed is 100 Mbit/sec. One analog transceiver/receiver ports are built-in. This block provides bus status monitoring initialization operation after a bus reset is applied, as well as arbitration and encoding/decoding functions for data sending and receiving. • LINK Layer Control Circuit This block controls the generation and transfer of IEEE 1394 standard packets. 32-bit CRC generation and checking is performed for packet headers and data. A 32-bit cycle timer register is built-in to provide cycle master functions. • Sending/Receiving FIFO Contains built-in 1-byte FIFO areas, used for isochronous transfer for both sending and receiving. Contains independent sending and receiving 128-byte FIFO areas for asynchronous transfer. • Packet Processing Sending: Performs packetizing of headers, data and CRC. Automatically generates and attaches CRC. Receiving: Separates 1394 packet headers and data, strips CRC. • Transaction Control Circuit Block This block controls the 1394 bus protocol based on a variety of instructions. • Dedicated Transaction Circuit Block This block packetizes data from the isochronous interface for DVC and rebuilds received data for the isochronous interface in conjunction with the packet processing block. • Register Block This block contains various device control registers, as well as registers for setting parameters required for transfer, DVC registers and CSR. The built-in CSR provides isochronous resource manager functions. • PLL Circuit This block uses the reference clock signal generated by the crystal oscillator circuit to create internal operating clock and transfer clock signals. Reference oscillator frequency: 8.192 MHz. 13 MB86615 ■ ABSOLUTE MAXIMUM RATINGS Parameter Rating Symbol Unit Min. Max. VDD VSS – 0.5 4.0 V Input voltage*1 VI VSS – 0.5 VDD + 0.5 V Output voltage*1 VO VSS – 0.5 VDD + 0.5 V Tst –55 +125 °C Top –40 +85 °C IO –14 +14 mA — — VDD + 1.0 V — — VSS – 1.0 V Power supply voltage*1 Strage temperature Operating temperature* Output current* Overshoot* 3 4 Undershoot* *1: *2: *3: *4: 2 4 Voltage values are based on Vss = 0 V. Not warranted for continuous operation. Normal output current flow (Minimum at Vo = 0 V, maximum at Vo = VDD). 50 ns or less. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Power supply voltage* Value Unit Min. Max. VDD 3.0 3.6 V “H” level input voltage CMOS input VIH VDD × 0.65 VDD V “L” level input voltage CMOS input VIL VSS VDD × 0.25 V Differential input voltage (for data transfer) Cable input VID 142 260 mV Differential input voltage (for arbitration) Cable input VIDA 173 260 mV Common mode input voltage Cable input VCM 1.165 2.515 V Receiving input jitter Cable input — — 1.08 ns Receiving input skew Cable input — — 0.8 ns CMOS output IOH/IOL –4 +4 mA TPBIAS Iot –2 +10 mA Ta 0 +70 °C Output current Operating temperature * : Voltage values are based on Vss = 0 V. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 14 MB86615 ■ ELECTRICAL CHARACTERISTICS 1. DC Characteristics 1.1 1394 Interface Driver Parameter Symbol (VDD = 3 to 3.6 V , VSS = 0 V, Ta = 0 to +70°C) Value Conditions Unit Min. Max. Differential output voltage VOD R1 = 56 Ω 172 265 mV Common phase current ICM Driver enabled –0.81 0.44 mA VOFF Driver disabled — 20 mV VO — 1.665 2.015 V Off state voltage TPBIAS output voltage 1.2 1394 Interface - Comparator Parameter Symbol (VDD = 3 to 3.6 V , VSS = 0 V, Ta = 0 to +70°C) Value Conditions Unit Min. Max. IIC Driver disabled –20 20 µA Arbitration comparator “H” level detection offset VSCH Driver disabled 168 — mV Arbitration comparator “Z” level detection offset VSCZ Driver disabled –30 30 mV Arbitration comparator “L” level detection offset VSCL Driver disabled — –168 mV Port status comparator disconnection detect voltage VSD Driver disabled — 0.6 V Port status comparator connection detect voltage VSC Driver disabled 1.0 — V Common phase input current 15 MB86615 1.3 System Interface, etc Parameter Symbol Conditions “H” level input voltage VIH CMOS VDD × 0.65 — VDD V “L” level input voltage VIL CMOS VSS — VDD × 0.25 V “H” level output voltage VOH IOH = –4 mA VDD – 0.5 — VDD V “L” level output voltage VOL IOL = +4 mA VSS — 0.4 V –5 — 5 µA –5 — 5 µA Input pins Input leak current Input pull-up resistance Power supply current 16 (VDD = 3 to 3.6 V , VSS = 0 V, Ta = 0 to +70°C) Value Unit Min. Typ. Max. 3-state pin input ILI ILZ VI = 0V to VDD Rp VIH = 0 25 50 200 kΩ IDD1 1394 port connected — — 200 mA IDD0 1394 port non connected — — 180 mA IDDS Forced sleep — — 30 mA MB86615 2. AC Characteristics 2.1 1394 Driver Parameter Value Symbol Min. Max. Unit Sending jitter tJT — ±0.8 ns Sending skew tSK — ±0.8 ns Sending rise time* Conditions Sending fall time* CL = 10 pF. RL = 56 Ω tDR — 3.2 ns tDF — 3.2 ns * : 10 to 90% value. 2.2 System Clock Parameter Value Symbol Min. Typ. Max. Unit Clock frequency fC 8.191992 8.192 8.192008 MHz Clock cycle time tCLF — 1/fc — ns High tCLCH 50 — — ns Low tCLCL 50 — — ns Clock rise time tCR — — 5 ns Clock fall time tCF — — 5 ns Clock pulse width tCLCH tCLF tCF tCR 0. 65 VDD 0. 25 VDD CLK tCLCL 17 MB86615 2.3 System Reset Parameter Symbol Reset (RESET) “L” level pulse width tWRSL Value tWRSL RESET 18 Min. Max. 4 tclf — Unit ns MB86615 2.4 MPU Interface (1) 68-Series Register Write Operation (multiplexed) Parameter Symbol Value Min. Max. Unit Address setup time tAWSM 10 — ns Address hold time tAWHM 10 — ns CS setup time tCWSM 20 — ns CS hold time tCWHM 10 — ns R/W setup time tRWSM 20 — ns R/W hold time tRWHM 10 — ns ALE “H” level pulse width tALE 15 — ns ALE fall to DS fall time tDWD 15 — ns DS “L” level pulse width tDSM 40 — ns Data setup time tDWSM 10 — ns Data hold time tDWHM 0 — ns DS rise to ALE rise time tLWD 20 — ns tCWSM tCWHM CS tRWHM tRWSM R/W tALE tLWD tDWD ALE tDSM DS tAWSM D15 to D6, D0 AD5 to AD1 Address tAWHM tDWSM tDWHM Data 19 MB86615 (2) 68-System Register Read Operation (multiplexed) Parameter Symbol Value Min. Max. Unit Address setup time tARSM 10 — ns Address hold time tARHM 10 — ns CS setup time tCRSM 20 — ns CS hold time tCRHM 10 — ns R/W setup time tRWSM 20 — ns R/W hold time tRWH 10 — ns ALE “H” level pulse width tALE 15 — ns ALE fall to DS fall time tDRD 15 — ns DS “L” level pulse width tDSM 40 — ns Data output definition time tRLDM — 40 ns Data output disabled time tRHDM 5 — ns tLRD 20 — ns DS rise to ALE rise time tCRSM tCRHM tRWSM tRWH CS R/W tALE tLRD tDRD ALE tDSM DS tARSM D15 to D6, D0 AD5 to AD1 20 Address tARHM tRLDM tRHDM Defined data MB86615 (3) 68-Series Register Write Operation (non-multiplexed) Parameter Value Symbol Min. Max. Unit Address setup time tAWS 10 — ns Address hold time tAWH 20 — ns CS setup time tCWS 20 — ns CS hold time tCWH 10 — ns R/W setup time tRWS 20 — ns R/W hold time tRWH 10 — ns DS “L” level pulse width tDS 40 — ns Data setup time tDWS 40 — ns Data hold time tDWH 0 — ns tAWS tAWH A5 to A0 tCWS tCWH tRWS tRWH CS R/W tDS DS tDWS D15 to D6, D0 AD5 to AD1 tDWH Data 21 MB86615 (4) 68-Series Register Read Operation (non-multiplexed) Parameter Value Symbol Min. Max. Unit Address setup time tARS 10 — ns Address hold time tARH 20 — ns CS setup time tCRS 20 — ns CS hold time tCRH 10 — ns R/W setup time tRWS 20 — ns R/W hold time tRWH 10 — ns DS “L” level pulse width tDS 40 — ns Data output definition time tRLD — 40 ns Data output disabled time tRHD 5 — ns tARS tARH A5 to A0 Address tCRS tCRH tRWS tRWH CS R/W tDS DS tRLD D15 to D6, D0 AD5 to AD1 22 tRHD Defined data MB86615 (5) 80-Series Register Write Operation (multiplexed) Parameter Symbol Value Min. Max. Unit Address setup time tAWSM 10 — ns Address hold time tAWHM 10 — ns CS setup time tCWSM 20 — ns CS hold time tCWHM 10 — ns ALE “H” level pulse width tALE 15 — ns ALE fall to WR fall time tDWD 15 — ns WR “L” level pulse width tWRM 40 — ns Data setup time tDWSM 40 — ns Data hold time tDWHM 0 — ns tLWD 20 — ns WR rise to ALE rise time tCWSM tCWHM CS tALE tDWD tLWD ALE tWRM WR tAWSM D15 to D6, D0 AD5 to AD1 Address tAWHM tDWSM tDWHM Data 23 MB86615 (6) 80-Series Register Read Operation (multiplexed) Parameter Symbol Value Min. Max. Unit Address setup time tARSM 10 — ns Address hold time tARAHM 10 — ns CS setup time tCRSM 20 — ns CS hold time tCRHM 10 — ns ALE “H” level pulse width tALE 15 — ns ALE fall to RD fall time tDRD 15 — ns RD “L” level pulse width tRDM 40 — ns Data output definition time tRLDM — 40 ns Data output disabled time tRHDM 5 — ns tLRD 20 — ns RD rise to ALE rise time tCRSM tCRHM CS tALE tDRD tLRD ALE tRDM RD tARSM D15 to D6, D0 AD5 to AD1 24 Address tARAHM tRLDM tRHDM Defined data MB86615 (7) 80-Series Register Write Operation (non-multiplexed) Parameter Value Symbol Min. Max. Unit Address setup time tAWS 10 — ns Address hold time tAWH 20 — ns CS setup time tCWS 20 — ns CS hold time tCWH 10 — ns WR “L” level pulse width tWR 40 — ns Data setup time tDWS 40 — ns Data hold time tDWH 0 — ns tAWS tAWH Address A5 to A0 tCWS tCWH CS tWR WR tDWS D15 to D6, D0 AD5 to AD1 tDWH Data 25 MB86615 (8) 80-Series Register Read Operation (non-multiplexed) Parameter Value Symbol Min. Max. Unit Address setup time tARS 10 — ns Address hold time tARH 20 — ns CS setup time tCRS 20 — ns CS hold time tCRH 10 — ns RD “L” level pulse width tRD 40 — ns Data output definition time tRLD — 40 ns Data output disabled time tRHD 5 — ns tARS tARH Address A5 to 0 tCRS tCRH CS tRD RD tRLD tRHD D15 to D6, D0 AD5 to AD1 Defined data (9) INT Signal Operation Parameter Interrupt read operation to INT signal negate Symbol tINTD Value Min. Max. 100 — Unit ns RD, DS tINTD INT Note: This specification applies only to reading of the last data from the interrupt holding register. For other read-related specifications, conform to the respective specifications for individual modes. 26 MB86615 2.5 DMA Access (1) 68-Series DMA Write Operation Parameter Value Symbol Min. Max. Unit DREQ “H” to DACK “L” tDHAL 0 — ns DS “H” to DREQ “L” tDHDL — 30 ns DACK setup time tDAWS 20 — ns DACK hold time tDAWH 0 — ns R/W setup time tDRWS 20 — ns R/W hold time tDRWH 10 — ns DS “L” level pulse width tDDS 40 — ns DS “H” level pulse width tDDSH 30 — ns Input data setup time tDDWS 30 — ns Input data hold time tDDWH 0 — ns tDHAL tDHDL DREQ tDAWS tDAWH tDRWS tDRWH DACK R/W tDDS tDDSH DS tDDWS D15 to D6, D0 AD5 to AD1 Data tDDWH Data 27 MB86615 (2) 68-Series DMA Read Operation Parameter Value Symbol Min. Max. Unit DREQ “H” to DACK “L” tDHAL 0 — ns DS “H” to DREQ “L” tDHDL — 30 ns DACK setup time tDARS 20 — ns DACK hold time tDARH 0 — ns R/W setup time tDRWS 20 — ns R/W hold time tDRWH 10 — ns DS “L” level pulse width tDDS 40 — ns DS “H” level pulse width tDDSH 30 — ns Data output definition time tDRLD — 40 ns Data output disabled time tDRHD 5 — ns tDHAL tDHDL DREQ tDARS tDARH tDRWS tDRWH DACK R/W tDDS tDDSH DS tDRLD D15 to D6, D0 AD5 to AD1 28 tDRHD Defined data Defined data MB86615 (3) 80-Series DMA Write Operation Parameter Value Symbol Min. Max. Unit DREQ “H” to DACK “L” tDHAL 0 — ns WR “H” to DREQ “L” tDHDL — 30 ns DACK setup time tDAWS 20 — ns DACK hold time tDAWH 0 — ns WR “L” level pulse width tDWR 40 — ns WR “H” level pulse width tDWRH 30 — ns Input data setup time tDDWS 30 — ns Input data hold time tDDWH 0 — ns tDHAL tDHDL DREQ tDAWS tDAWH DACK tDWR tDWRH WR tDDWS D15 to D6, D0 AD5 to AD1 Data tDDWH Data 29 MB86615 (4) 80-Series DMA Read Operation Parameter Value Symbol Min. Max. Unit DREQ “H” to DACK “L” tDHAL 0 — ns RD “H” to DREQ “L” tDHDL — 30 ns DACK setup time tDARS 20 — ns DACK hold time tDARH 0 — ns RD “L” level pulse width tDRD 40 — ns RD “H” level pulse width tDRDH 30 — ns Data output definition time tDRLD — 40 ns Data output disabled time tDRHD 5 — ns tDHAL tDHDL DREQ tDARS tDARH DACK tDRD tDRDH RD tDRLD D15 to D6, D0 AD5 to AD1 30 tDRHD Defined data Defined data MB86615 2.6 Isochronous Interface 2.6.1 ICLK Parameter Symbol Value Min. Max. Unit Clock frequency — 4 16 MHz Clock cycle time tICLK 62.5 250 ns Clock “H” level pulse width tICLH 20 — ns Clock “L” level pulse width tICLL 20 — ns Clock rise time tICR — 7 ns Clock fall time tICF — 7 ns tICLK tICLH tICF tICR 0. 65 VDD 0. 25 VDD ICLK tICLL 31 MB86615 2.6.2 Sending Operation (1) Start Sending Operation Parameter Value Symbol Min. Max. Unit IDIR fall to ILWRE fall time tSDIR — tICLK + 125 ns ICLK rise to ILWRE fall time tSIDIR — 40 ns ILWRE fall to IV fall time tILIV 0 — ns IV setup time tSIV 40 — ns Data setup time tSD 20 — ns Data hold time tHD 0 — ns ICLK IDIR tSIDIR tSDIR tILIV ILWRE tSIV IV tHD tSD ID7 to ID0 32 1 2 3 MB86615 (2) End Sending Operation Parameter Value Symbol Min. Max. Unit IV rise to IDIR rise time tHDIR 0 — ns IDIR rise to ILWRE rise time tDWR — 1 tICLK + 40 ns ICLK rise to ILWRE rise time tSWDIR — 40 ns IDIR rise to IDIR fall time tDIRH 250 — µs ICLK IDIR tSWDIR tDWR ILWRE tHDIR tDIRH IV ID7 to ID0 N−1 N N+1 33 MB86615 (3) IV Temporary Negation in Sending Operation Parameter Symbol Value Min. Max. IV hold time tHIV 0 tICLK – 40 ns Date setup time tSD 20 — ns Data hold time tHD 0 — ns ICLK IDIR ILWRE tHIV IV tSD ID7 to ID0 34 Unit N−1 tHD N N+1 MB86615 (4) Negating ILWRE during Transmission (with a bus reset detected or the FIFO buffer full) Parameter Symbol Value Min. Max. Unit ICLK rise to ILWRE rise time tHWRL — 40 ns ILWRE rise to IV rise time tREMIV tICLK 2 tICLK – 40 ns ICLK rise to ILWRE fall time tHWRH — 40 ns ICLK IDIR tHWRL tHWRH ILWRE tREMIV IV ID7 to ID0 valid valid valid ignore Note: The ILWRE signal is negated to stop writing data to be transmitted in either of the following cases in the transmission mode (1) When the ISO transmission/reception FIFO buffer becomes full (The ILWRE signal is negated in synchronization with the last ICLK signal generated before the FIFO buffer becomes full. Note, however, that this condition does not negate the ILWRE signal if the point-rcc bit (bit 7) in the ISO-FIFO control register (address 0Eh) has been set to “1.” (2) When a bus reset is detected (The ILWRE signal is negated in synchronization with the last ICLK signal generated before the FIFO buffer loads one packet of data after detection of the bus reset.) The ILWRE signal is asserted back when transmission of one packet of data to the 1394 bus is completed. 35 MB86615 (5) Switch to Transmission from Reception in Process Parameter Value Symbol Min. Max. Unit IDIR fall to ILWRE rise time tDLWRH — tICLK + 40 ns IDIR fall to ILWRE fall time tDLWRL — 2 tICLK + 40 ns ICLK IDIR tDLWRL tDLWRH ILWRE (6) FP Input Timing Parameter Symbol Min. Max. Unit FP “L” level pulse width tFPL 100 — ns FP “H” level pulse width tFPH 125 — µs FP “H” detection to CTR value load — 80 150 ns tFPL FP 36 Value tFPH MB86615 2.6.3 Receiving Operation (1) Start Receiving Operation Parameter Value Symbol ICLK rise to ILWRE fall Min. Max. Unit tWREH — 40 ns IV setup time tSIV 40 — ns Data output definition time tDZ — 40 ns Data output disable time tD 10 40 ns IV fall to ICRCE fall time* tERRL — 40 ns * : The ICRCE signal is output when a CRC error is detected in receiving data. ICLK IDIR tWREH ILWRE tSIV IV tDZ tD ID7 to ID0 Hi − Z 1 2 3 tERRL ICRCE 37 MB86615 (2) End Receiving Operation Parameter Value Symbol Min. Max. ICLK rise to ILWRE rise tWREL — 40 ns Data output disable time tZD 0 50 ns ILWRE negate time*1 tWREH 6 tICLK — ns IV rise to ICRCE rise time*2 tERRH — 40 ns *1: This device negates the ILWRE signal upon completion of reading each packet of data. *2: The ICRCE signal is asserted only when a CRC error is detected in data received. ICLK IDIR tWREL tWREH ILWRE IV tZD ID7 to ID0 N−2 N−1 Hi − Z N tERRH ICRCE 38 Unit MB86615 (3) IV Temporary Negation in Receiving Operation Parameter Value Symbol Unit Min. Max. tHIV 40 — ns IV rise to ICRCE rise time tERRH — 40 ns IV fall to ICRCE fall time tERRL — 40 ns IV rise to ICLK rise ICLK IDIR ILWRE tHIV IV ID7 to ID0 N−3 N−2 Hi − Z tERRH N−1 tERRL ICRCE 39 MB86615 (4) FP Signal Output Parameter Symbol Value Min. Max. IDIR fall to FP output enable tZFP — 40 ns FP “L” level pulse width tFPW 600 730 ns — — 40 ns Time stamp match detect to FP output IDIR tZFP FP 40 Unit Hi − Z tFPW MB86615 2.6.4 Clearing the ISO Transmission/Reception FIFO Buffer Using the fifo-clr Bit The ISO transmission/reception FIFO buffer is cleared by setting the fifo-clr bit (bit 4) in the ISO-FIFO control register (address 0Eh) to “1.” Given below is a timing chart for the isochronous interface when the FIFO buffer is cleared. Note that this FIFO buffer clear function is available only when the point-rec bit (bit 7) or length-chk bit (bit 6) in the ISO-FIFO control register has been set to “1.” Parameter Value Symbol IV rise to ILWRE rise ILWRE negate time tCLR Unit Min. Max. tCLR — 4 tICLK ns tWREH — 7 tICLK ns tWREH ILWRE IV * : The ISO transmission/reception FIFO buffer is cleared while the ILWRE signal is negated. 41 MB86615 ■ INTERNAL REGISTERS The MB86615 internal registers have 3-bank construction, with 16-bit access to all registers. Bank 0 contains registers necessary for IEEE 1394 settings and transfer, bank 1 contains registers necessary for AV/C (DVC) operation, and bank 2 contains CSR’s. In addition each bank has registers used in common for MB86615 device control. 1. Bank Common Registers The following registers can be accessed in any bank from bank 0 to bank 2. Address 42 Write operation Read operation 0 mode-control register ← 0 1 (reserved) flag & status register 0 1 0 instruction fetch register ← 0 0 1 1 interrupt mask register interrupt code register 0 0 1 0 0 (reserved) Receiving acknowledge display register 0A 0 0 1 0 1 ASYNC data port (sending) ASYNC data port (receiving) 0C 0 0 1 1 0 mode-control-2 register ← 0E 0 0 1 1 1 ISO-FIFO control register ← 3E 1 1 1 1 1 bank select register ← HEX A5 A4 A3 A2 A1 00 0 0 0 0 02 0 0 0 04 0 0 06 0 08 MB86615 2. Bank 0 Registers Bank 0 contains the registers required for 1394 settings and transfers. Access to this bank is enabled by writing ‘0000h’ to the bank select register (3Eh). Address Write operation Read operation 0 Sending ISO PKT header setting register (high) Receiving ISO PKT header display register (high) 0 1 Sending ISO PKT header setting register (low) Receiving ISO PKT header display register (low) 0 1 0 Sending ASYNC des ID setting register Receiving ASYNC des ID setting register 1 0 1 1 Sending ASYNC PKT param setting register Receiving ASYNC PKT param display register 0 1 1 0 0 Sending ASYNC data length setting register Receiving ASYNC data length display register 1A 0 1 1 0 1 Sending ASYNC ex tcode setting register Receiving ASYNC ex tcode display register 1C 0 1 1 1 0 Sending ASYNC source ID setting register Receiving ASYNC source ID display register 1E 0 1 1 1 1 Sending ASYNC resp param setting register Receiving ASYNC resp param display register 20 1 0 0 0 0 Sending ASYNC des offset setting register (high) Receiving ASYNC des offset display register (high) 22 1 0 0 0 1 Sending ASYNC des offset setting register (middle) Receiving ASYNC des offset display register (middle) 24 1 0 0 1 0 Sending ASYNC des offset setting register (low) Receiving ASYNC des offset display register (low) 26 1 0 0 1 1 (reserved) ← 28 1 0 1 0 0 (reserved) PHY ID display register 2A 1 0 1 0 1 (reserved) NODE config display register 2C 1 0 1 1 0 (reserved) ← HEX A5 A4 A3 A2 A1 10 0 1 0 0 12 0 1 0 14 0 1 16 0 18 2E 1 0 1 1 1 (reserved) PORT config display register 30 1 1 0 0 0 state clear setting register root ID display register 32 1 1 0 0 1 Self ID PKT param setting register ISO resource manager ID display register 34 1 1 0 1 0 Receiving ISO-channel setting register (0, 1) ← 36 1 1 0 1 1 Receiving ISO-channel setting register (2, 3) ← 38 1 1 1 0 0 (reserved) cycle timer monitor display register (high) 3A 1 1 1 0 1 (reserved) cycle timer monitor display register (low) 3C 1 1 1 1 0 (reserved) ← 43 MB86615 3. Bank 1 Registers Bank 1 contains the registers required for AV/C (DVC) protocols. Access to this bank is enabled by writing ‘0001h’ to the bank select register (3Eh). Address 44 Write operation Read operation 0 Sending time stamp offset setting register ← 0 1 Receiving time stamp offset setting register ← 0 1 0 Sending CIP header DBS setting register Receiving CIP header display register (highest) 1 0 1 1 (reserved) Receiving CIP header display register (high) 0 1 1 0 0 Sending CIP header FMT setting register Receiving CIP header display register (low) 1A 0 1 1 0 1 (reserved) Receiving CIP header display register (lowest) 1C 0 1 1 1 0 OMPR (high) ← 1E 0 1 1 1 1 OMPR (low) ← 20 1 0 0 0 0 OPCR0 (high) ← 22 1 0 0 0 1 OPCR0 (low) ← 24 1 0 0 1 0 (reserved) ← 26 1 0 0 1 1 (reserved) ← 28 1 0 1 0 0 (reserved) ← 2A 1 0 1 0 1 (reserved) ← 2C 1 0 1 1 0 IMPR (high) ← 2E 1 0 1 1 1 IMPR (low) ← 30 1 1 0 0 0 IPCR0 (high) ← 32 1 1 0 0 1 IPCR0 (low) ← 34 1 1 0 1 0 (reserved) ← 36 1 1 0 1 1 (reserved) ← HEX A5 A4 A3 A2 A1 10 0 1 0 0 12 0 1 0 14 0 1 16 0 18 38 1 1 1 0 0 (reserved) ← 3A 1 1 1 0 1 (reserved) ← 3C 1 1 1 1 0 set-PCR & FP-timeout setting register ← MB86615 4. Bank 2 Registers Bank 2 contains CSR’s required for Isochronous resource manager. Access to this bank is enabled by writing ‘0002h’ to the bank select register (3Eh). Address Write operation Read operation 0 bus manager ID register (high) ← 0 1 bus manager ID register (low) ← 0 1 0 bandwidth available register (high) ← 1 0 1 1 bandwidth available register (low) ← 0 1 1 0 0 channels available high register (high) ← 1A 0 1 1 0 1 channels available high register (low) ← 1C 0 1 1 1 0 channels available low register (high) ← 1E 0 1 1 1 1 channels available low register (low) ← 20 1 0 0 0 0 (reserved) ← 22 1 0 0 0 1 (reserved) ← 24 1 0 0 1 0 (reserved) ← 26 1 0 0 1 1 (reserved) ← 28 1 0 1 0 0 (reserved) ← 2A 1 0 1 0 1 (reserved) ← 2C 1 0 1 1 0 (reserved) ← 2E 1 0 1 1 1 (reserved) ← 30 1 1 0 0 0 (reserved) ← 32 1 1 0 0 1 (reserved) ← 34 1 1 0 1 0 (reserved) ← 36 1 1 0 1 1 (reserved) ← 38 1 1 1 0 0 (reserved) ← 3A 1 1 1 0 1 (reserved) ← 3C 1 1 1 1 0 (reserved) ← HEX A5 A4 A3 A2 A1 10 0 1 0 0 12 0 1 0 14 0 1 16 0 18 45 MB86615 ■ ORDERING INFORMATION Partnumber 46 Package MB86615PFV 100-pin plastic LQFP (FPT-100P-M05) MB86615PBT 120-pin plastic FBGA (BGA-120P-M01) Remarks MB86615 ■ PACKAGE DIMENSIONS 100-pin plastic LQFP (FPT-100P-M05) +0.20 16.00±0.20(.630±.008)SQ 75 1.50 −0.10 (Mounting height) +.008 .059 −.004 51 14.00±0.10(.551±.004)SQ 76 50 12.00 (.472) REF 15.00 (.591) NOM Details of "A" part 0.15(.006) INDEX 100 0.15(.006) 26 0.15(.006)MAX LEAD No. "B" 25 1 0.40(.016)MAX "A" 0.50(.0197)TYP +0.08 0.18 −0.03 +.003 .007 −.001 +0.05 0.08(.003) 0.127 −0.02 +.002 .005 −.001 M Details of "B" part 0.10±0.10 (STAND OFF) (.004±.004) 0.50±0.20(.020±.008) 0.10(.004) C 0~10˚ Dimensions in mm (inches) 1995 FUJITSU LIMITED F100007S-2C-3 120-pin plastic FBGA (BGA-120P-M01) 12.00±0.10(.472±.004)SQ +0.20 +.008 1.25 –0.10 .049 –.004 (Mounting height) 0.38±0.10(.015±.004) (Stand off) 9.60(.378)REF 0.80(.031)TYP 13 12 11 10 9 8 7 6 0.10(.004) 5 4 3 INDEX 2 1 N M L K J H G F E D C B A C0.80(.031) C 1998 FUJITSU LIMITED B120001S-1C-1 120-Ø0.45±0.10 (120-Ø.018±.004) 0.08(.003) M Dimensions in mm (inches) 47 MB86615 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ F9902 FUJITSU LIMITED Printed in Japan 48 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.