FUJITSU MB89051PFM

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12551-2E
8-bit Proprietary Microcontrollers
CMOS
F2MC-8L MB89051 Series
MB89F051/MB89051
■ DESCRIPTION
The MB89051 series is a general-purpose, single-chip microcontroller that features a compact instruction set and
contains a range of peripheral function set and timers, serial interface, a PWM timer, the USB hub function and
the USB function. The USB hub function, in particular, supports five down ports (one of them is dedicated to an
internal function) allowing them to interface with other USB devices. The microcontrollers also contain one USB
function channel to support full speed.
■ FEATURES
• Package type
64-pin LQFP Package (0.65 mm pitch)
• High-speed operations at low voltage
Minimum execution time : 0.33 µs (Automatically generates a 12 MHz main clock and a 48 MHz USB interface
synchronization clock with an externally supplied 6 MHz clock and the internal PLL circuit.)
(Continued)
■ Package
64-pin plastic LQFP
(FPT-64P-M09)
MB89051 Series
• F2MC-8L CPU core
Instruction set that is optimum to the controllers
-Multiplication and division instructions
-16-bit arithmetic operations
-branch instructions by bit testing
-bit manipulation instructions, etc.
• PLL clock control
The internal PLL clock circuit allows the use of low-speed clocks which are advantageous to noise characteristics.
(6 MHz externally-supplied clock→12 MHz internal system clock)
• Various timers
8-bit PWM timer (can be used as either 8-bit PWM timer 2 channels or PPG timer 1 channel)
Internal 21-bit timebase timer
• Internal USB transceiver circuit (Compatible with full and low speeds)
• USB hub
USB function Compliant to USB Protocol Revision 1.0
Five downstream port channels (One of these channels is dedicated to a function.)
Automatically responds to all USB protocols by hardware.
Descriptor configuration is provided as ROM data for automatic responding by hardware (Vender ID and product
ID) .
String data is not supported.
Allows switching between BUS power supply and own power supply mode.
Power supply to the USB down port is controlled port by port.
• USB function
USB function Compliant to USB Protocol Revision 1.0
Support for full speed when using hub
Support for both low and full speeds when using function
Allows four endpoints to be specified at maximum.
Types of transfer supported: control/interrupt/bulk/isochronous
Built-in DMAC (Maps the buffer for each endpoint on to the internal RAM to directly access the memory for
function’s send and receive data.)
• UART/SIO, SIO Serial Interface
Built-in UART/SIO function (selectable by switching) × 1 channel
Built-in SIO (3.3 V) × 2 channels
• I2C interface*1
Supports Philips I2C bus standards
Uses a two-wire data transfer protocol
Master/slave send/receive
• External interrupt
External interrupt (level detection × 7 channels)
Seven inputs are independent of one another and can also be used for resetting from low-power consumption
mode (the L-level detection feature available) .
• Clock output functions
Able for 12 MHz*2 and 6 MHz*2 clocks to output. (dedicated pins, 3 V)
• Low power consumption (standby mode supported)
Stop mode (There is almost no current consumption since oscillation stops.)
Sleep mode (This mode stops the running CPU.)
(Continued)
2
MB89051 Series
(Continued)
• A maximum of 41 general-purpose I/O ports
General-purpose I/O ports (CMOS) : 37 (7 of 3 V ports)
General-purpose I/O ports (Nch open drain) : 4
• Power supply
Supply voltage: 3.3 V ± 0.3 V or 5.0 V ± 0.5 V
• Operating temperature
TA = −40 ° to +85 °C (When the USB function is not in use.)
TA = 0 °C to +70 °C (When the USB function is in use.)
*1 : I2C license
The customer is licensed to use Philips I2C patent when using this product in an I2C system that complies with
the Philips I2C standard specifications.
*2 : When an external supply clock is at 6 MHz.
3
MB89051 Series
■ PRODUCT LINEUP
Part number
Parameter
ROM size
MB89051
MB89F051
32 KB
32 KB (FLASH)
RAM size
2 KB
Package
LQFP-64 (FPT-64P-M09)
Others
MASK product
CPU functions
Number of instructions
Instruction bit length
Instruction length
Data bit length
Minimum execution time
Interrupt processing time
FLASH product/EVA product
: 136
: 8 bits
: 1 to 3 bytes
: 1, 8, and 16 bits
: 0.33 µs (6 MHz)
: 3 µs (6 MHz)
Peripheral functions
GeneralGeneral purpose I/O ports (37 : CMOS (7 of 3 V ports ) , 4 : Nch open drain)
purpose ports
USB hub
Upstream port : 1 channel
Downstream port : 5 channels (One is dedicated to an internal function.)
Port power supply control method : By individual port
Allows selection between own power supply and bus power supply
USB function
Supports full speed : when using hub
Supports full and low speeds : when using function
End point max 4
Built-in DMAC (Can be set to DMA transfer to the internal RAM)
PWM timer
8-bit PWM timer operation 2 channels (can also be used as a PPG 1 channel timer)
UART
Allows switching between UART (clock-synchronous/asynchronous data transfer allowed)
and SIO (simple serial transfer).
SIO
SIO
SIO (simple serial) × 2 channels (3 V)
I2C interface
One channel. Supports Phillips I2C bus standards. Uses a 2-wire protocol for communications
with other devices.
Timebase
timer
21-bit timebase timer
Clock output
Allows clock output of 12 MHz* and 6 MHz* (3 V)
Standby mode
Sleep mode and Stop mode
* : When external supply clock is at 6 MHz.
4
MB89051 Series
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
• Before evaluating using the FLASH product, it is necessary to confirm its differences from the product that will
actually be used.
2. Current Consumption
• When operating at low speed, FLASH products will consume more current than mask ROM products. However,
in sleep/stop mode the current consumption is the same.
• For detailed information on each package, see “■PACKAGE DIMENSIONS”
3. USB Pull-up Resistor control
• Remains in high impedance state until USB connection take place. Before the USB connection, use USBP
pin output to control pull-up resistance by software.
• The example of connection
MB89051 series
Host PC
3.3 V
USBP pin
1.5 kΩ
D+
RPVP pin
D−
RPVM pin
5
MB89051 Series
■ PIN ASSIGNMENT
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
P33/INT3/SO1
P32/INT2/SI1
P31/INT1
D4VM
D4VP
D3VM
D3VP
D2VM
D2VP
D5VM
D5VP
USBP
RPVM
RPVP
C
VCC
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P53/SDA
P54/SCL
RST
MOD0
MOD1
X0
X1
VSS
P27
P26
P25
P24
P23
P22
P21
P20
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P34/INT4/SCK1
P35/INT5/SCK2
P36/INT6/SO2
P37/INT7/SI2
CLK1
CLK2
P40/POW5
P41/POW2
P42/POW3
P43/POW4
P44/UCK
P45/UO
P46/UI/PWM1
VSS
P47/PWM2
MOD2
(FPT-64P-M09)
6
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
MB89051 Series
■ PIN DESCRIPTION
Pin No.
Pin name
Circuit
type
1
P34/INT4/
SCK1
E
General-purpose CMOS I/O pin
The external interrupt input is a hysteresis input. (Level detection)
SIO1 clock I/O
2
P35/INT5/
SCK2
E
General-purpose CMOS I/O pin
The external interrupt input is a hysteresis input. (Level detection)
SIO2 clock I/O
3
P36/INT6/
SO2
B
General-purpose CMOS I/O pin
The external interrupt input is a hysteresis input. (Level detection)
SIO2 serial data output
4
P37/INT7/SI2
E
General-purpose CMOS I/O pin
The external interrupt input is a hysteresis input. (Level detection)
SIO2 serial data input
5
CLK1
M
6 MHz clock output pin (When external supply clock is at 6 MHz.)
6
CLK2
M
12 MHz clock output pin (When external supply clock is at 6 MHz.)
7
P40/POW5
B
General-purpose CMOS I/O pin
This pin also serves as USB Down Port power control signal.
8
P41/POW2
B
General-purpose CMOS I/O pin
This pin also serves as USB Down Port power control signal.
9
P42/POW3
B
General-purpose CMOS I/O pin
This pin also serves as USB Down Port power control signal.
10
P43/POW4
B
General-purpose CMOS I/O pin
This pin also serves as USB Down Port power control signal.
11
P44/UCK
E
General-purpose CMOS I/O pin
UART/S10 clock I/O
12
P45/UO
B
General-purpose CMOS I/O pin
UART/S10 serial data output
13
P46/UI/
PWM1
N
Nch open drain general-purpose I/O pin
UART/S10 serial data input
PWM timer
14
VSS

Power supply pin (GND)
15
P47/PWM2
K
Nch open drain general-purpose I/O pin
PWM timer
16
MOD2
F
An operating mode designation pin. Connect directly to Vss.
17
P53/SDA
K
Nch open drain general-purpose I/O pin
Also serve as I2C interface data input/output pin.
18
P54/SCL
K
Nch open drain general-purpose I/O pin
Also serve as I2C interface clock input/output pin.
19
RST
I
Reset pin (Reset on the negative logic low level.)
20
MOD0
F
An operating mode designation pin. Connect directly to Vss.
21
MOD1
F
An operating mode designation pin. Connect directly to Vss.
Function
(Continued)
7
MB89051 Series
Pin No.
Pin name
22
X0
23
X1
24
Circuit
type
Function
A
Pins for the connection of crystal oscillation circuit.(6 MHz)
VSS

Power supply pin (GND)
25
P27
B
General-purpose CMOS I/O pin*
26
P26
B
General-purpose CMOS I/O pin*
27
P25
B
General-purpose CMOS I/O pin*
28
P24
B
General-purpose CMOS I/O pin*
29
P23
B
General-purpose CMOS I/O pin*
30
P22
B
General-purpose CMOS I/O pin*
31
P21
B
General-purpose CMOS I/O pin*
32
P20
B
General-purpose CMOS I/O pin*
33
P17
B
General-purpose CMOS I/O pin
34
P16
B
General-purpose CMOS I/O pin
35
P15
B
General-purpose CMOS I/O pin
36
P14
B
General-purpose CMOS I/O pin
37
P13
B
General-purpose CMOS I/O pin
38
P12
B
General-purpose CMOS I/O pin
39
P11
B
General-purpose CMOS I/O pin
40
P10
B
General-purpose CMOS I/O pin
41
P07
B
General-purpose CMOS I/O pin
42
P06
B
General-purpose CMOS I/O pin
43
P05
B
General-purpose CMOS I/O pin
44
P04
B
General-purpose CMOS I/O pin
45
P03
B
General-purpose CMOS I/O pin
46
P02
B
General-purpose CMOS I/O pin
47
P01
B
General-purpose CMOS I/O pin
48
P00
B
General-purpose CMOS I/O pin
49
VCC

Power supply pin.
50
C

Connect an external capacitor of 0.1 µF. When using with 3.3 V power
supply, connect this pin with the Vcc pin to set to 3.3 V input.
51
RPVP
USBDRV USB route port + pin
52
RPVM
USBDRV USB router port − pin
53
USBP
54
D5VP
USBDRV USB down port 5 + pin
55
D5VM
USBDRV USB down port 5 − pin
L
USB pull-up resistance connection pin.
* : For output only on the emulator.
(Continued)
8
MB89051 Series
(Continued)
Circuit
type
Pin No.
Pin name
Function
56
D2VP
USBDRV USB down port 2 + pin
57
D2VM
USBDRV USB down port 2 − pin
58
D3VP
USBDRV USB down port 3 + pin
59
D3VM
USBDRV USB down port 3 − pin
60
D4VP
USBDRV USB down port 4 + pin
61
D4VM
USBDRV USB down port 4 − pin
62
P31/INT1
B
General-purpose CMOS I/O pin
External interrupt input (Hysteresis input (level detection) )
63
P32/INT2/SI1
E
General-purpose CMOS I/O pin
External interrupt input (Hysteresis input (level detection) )
SIO1 serial data input
64
P33/INT3/
SO1
B
General-purpose CMOS I/O pin
External interrupt input (Hysteresis input (level detection) )
SIO1 serial data output
9
MB89051 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
• Oscillation feedback resistance :
1 MΩ approx.
X1
A
X0
Stanby control signal
• CMOS I/O
R
Pch
Pullup control register
Pch
B
Nch
Input
Stanby control
signal
• CMOS I/O
• Hysteresis input
R
Pch
Pullup control register
Pch
E
Nch
Port input
Stanby
control signal
Resource input
• CMOS input
F
Input
• Hysteresis I/O
• Pullup resistance
R
Pch
I
Nch
Input
(Continued)
10
MB89051 Series
(Continued)
Type
Circuit
Remarks
• USB I/O
+
D input
D− input
D+
Differential input
D−
Full D+ output
USBDRV
Full D− output
Low D+ output
Low D− output
Direction
Speed
• Nch open drain I/O
Nch
K
Input
Stanby control
signal
• USB pull-up resistance connection
Pch
L
Nch
• Clock output
Pch
M
Nch
• Nch open drain I/O
• Hysteresis input
Nch
N
Stanby
control signal
Port input
Resource input
11
MB89051 Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than Vcc or lower than Vss is applied to input or output pins
other than the medium- and high-voltage pins or if voltage higher than the rating is applied between Vcc and Vss.
When latchup occurs, power supply current increases rapidly and might thermally damage elements.When
using, take great care not to exceed the absolute maximum ratings.
Also take care to prevent the analog input from exceeding the digital power supply (Vcc) when the power supply
to the analog power system is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions and latchup leading to permanent damage to the
pins.These unused pins should be connected to a pullup or pulldown resistance of at least 2 kΩ between the
pin and the power supply.
Unused I/O pins should be placed in output state to leave it open or pins that are in input state should be handled
the same as unused input pins.
3. Note to noise in the External Reset Pin (RST)
If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST).
4. Power Supply Voltage Fluctuations
Although Vcc power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
could cause malfunctions even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore
important. As stabilization guidelines, it is recommended to control power so that Vcc ripple fluctuations (P-P
value) will be less than 10% of the standard VCC value at the commercial frequency (50 Hz to 60 Hz) and the
transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power
is switched.
5. Note on the clock during operation
This microcontroller uses a PLL for generating the main clock signal. If the oscillator is removed or the clock
input stops during operation, therefor, the microcontroller may keep on operating at the free-running frequency
of the self-oscillation circuit in the PLL. The operation is not however guaranteed.
6. About port 2 (P20 to P27)
Port 2 serves as an output-only terminal on the emulator.
12
MB89051 Series
■ PROGRAMMING AND ERASING FLSH MEMORY
1. Flash Memory
The flash memory is located between 8000H and FFFFH in the CPU memory map and incorporates a flash
memory interface circuit that allows read access and program access from the CPU to be performed in the same
way as mark ROM. Programming and erasing flash memory is also performed via the flash memory interface
circuit by executing instructions in the CPU. This enables the flash memory to be updated in place under the
control of the CPU, providing an efficient method of updating program and data.
2. Flash Memory Features
•
•
•
•
•
•
•
•
32 Kbyte × 8-bit configuration (16 K + 8 K + 8 K sectors)
Automatic programming algorithm (Embedded Algorithm* : Equivalent to MBM29LV200)
Includes an erase pause and restart function
Data polling and toggle bit for detection of program/erase completion
Detection of program/erase completion via CPU interrupt
Compatible with JEDEC-standard command
Sector Protection (sectors can be combined in any combination)
No. of program/erase cycles : 10,000 (Min)
* : Embedded Algorithm is a trademark of Advanced Micro Devices.
3. Procedure for Programming and Erasing Flash Memory
Programming and reading flash memory cannot be performed at the same time. Accordingly, to program or
erase flash memory, the program must first be copied from flash memory to RAM so that programming can be
performed without program access from flash memory.
4. Flash Memory Register
• Control status register (FMCS)
Address bit7
002EH
bit6
bit5
bit4
INTE RDYINT
WE
ReReRDY served
served
R/W
R/W
R/W
R
bit3
R/W
bit2
R/W
bit1
bit0

Reserved

R/W
Initial value
000X00X0B
5. Sector Configuration
The table below shows the sector configuration of flash memory and lists the addresses of each sector for both
during CPU access and a flash memory programming.
• Sector configuration of flash memory
Flash Memory
CPU Address
Programmer Address*
16 Kbytes
FFFFH to C000H
1FFFFH to 1C000H
8 Kbytes
BFFFH to A000H
1BFFFH to 1A000H
8 Kbytes
9FFFH to 8000H
19FFFH to 18000H
* : Programmer address
The programmer address is the address to be used instead of the CPU address when programming data from
a parallel flash memory programmer. Use the programmer address on programming or erasing using a generalpurpose parallel programmer.
13
MB89051 Series
6. ROM Programmer Adaptor and Recommended ROM Programmers
Package
FPT-64P-M09
• Inquiry:
Sunhayato Corp.
Ando Denki K. K.
14
Compatible adapter
Compatible programmers and models
Sunhayato Corp.
Ando Denki K.K.
FLASH-64QF2-32DP-8LF3
: TEL
FAX
E-mail
: TEL
AF9708 (ver 1.60 or higher)
AF9709 (ver 1.60 or higher)
: 81-3-3984-7791
: 81-3-3971-0535
: [email protected]
: 81-3-3733-1160
MB89051 Series
■ BLOCK DIAGRAM
X0
X1
Main clock oscillator
Reset output
Clock control circuit
Power on
reset circuit
(watchdog
timer)
PLL circuit
USB HUB
Circuit
Dp1
UART
USB
Function
Circuit
SIO
CMOS out Port
Nch I/O Port
P53/SDA, P54/SCL
3 V CMOS I/O Port
P31/INT1
P32/INT2/SI1
P33/INT3/SO1
P34/INT4/SCK1
P35/INT5/SCK2
P36/INT6/SO2
P37/INT7/SI2
8 bit PWM
timer
CMOS I/O Port
CLK2
3 V CLK Port
CLK1
CMOS I/O Port
P40/POW5
P41/POW2
P42/POW3
P43/POW4
Internal Bus
D2VM ∼ D5VM
Dp2-5
Nch I/O Port
D2VP ∼ D5VP
USB DRV
RPVM
21-bit timebase timer
Rp
RPVP
RST
DMAC
Clock output
P46/UI/PWM1
P47/PWM2
P44/UCK
P45/UO
P00 ∼ P07, P10 ∼ P17
P20 ∼ P27*
External interrupt (level)
RAM 2 KByte
SIO1
SIO2
F2MC - 8L CPU
ROM 32 K / FLASH 32 KByte
I2C
Other pins
VSS
VCC
MOD0 MOD1 MOD2 USBP C
* : Port 2 serves as an output-only terminal on the emulator.
15
MB89051 Series
■ CPU CORE
1. Memory Size
The MB89051 microcontroller offers a memory space of 64 Kbytes consisting of the I/O, RAM and ROM areas.
The memory space contains areas that are used for specific purposes, such as a general-purpose register and
a vector table.
• I/O area (addresses: 0000H through 007FH)
This area is assigned with the control and data registers, for example, of peripheral functions to be built in.
The I/O area is as accessible as the memory since the area is assigned to a part of the memory space.Direct
addressing also allows the area to be accessed faster.
• RAM area
As an internal data area, a static RAM is built in.
The internal RAM capacity varies with the product type.
The area 80H to FFH can be accessed at high speed with direct addressing.
The area 100H to 1FFH can be used a general-purpose register area. (The usable area is limited depending
on the product.)
When reset, RAM data becomes undefined.
• ROM area
As an internal program area, a ROM is built in.
The internal RAM capacity varies with the product type.
The area FFC0H to FFFFH should be used for a vector table, for example.
• Memory map
MB89F051
MB89051
0000H
0000H
I/O
0080H
I/O
0080H
RAM
0100H
RAM
0100H
Register
Register
0200H
0200H
0880H
0880H
Access
prohibited
8000H
Access
prohibited
8000H
ROM∗
ROM
FFC0H
FFFFH
Vector table
(reset, interrupt and vector call instructions)
16
FFC0H
FFFFH
* : FLASH ROM
MB89051 Series
2. Registers
The MB89051 series has two types of registers; the registers dedicated to specific purposes in the CPU and
the general-purpose registers.
The dedicated registers are as follows:
Program counter (PC)
: A 16-bit register to indicate locations where instructions are stored.
A 16-bit register for temporary storage of operations. In the case of an 8-bit
:
data processing instruction, the lower one byte is used.
A 16-bit register which performs operations with the accumulator.In the case of
:
an 8-bit data processing instruction, the lower one byte is used.
: A 16-bit register for index modification.
: A 16-bit register to point to a memory address.
: A 16-bit register to indicate a stack area.
: A 16-bit register to store a register pointer or a condition code.
Accumulator (A)
Temporary accumulator (T)
Index register (IX)
Extra pointer (EP)
Stack pointer (SP)
Program status (PS)
16 bits
Initial value
FFFDH
: Program counter
PC
A
: Accumulator
Indeterminate
T
: Temporary accumulator
Indeterminate
IX
: Index register
Indeterminate
EP
: Extra pointer
Indeterminate
SP
: Stack pointer
Indeterminate
RP
CCR
I-flag = 0, IL1, 0 = 11
Initial values for other bits are
indeterminate.
: Program status
PS
The PS register can further be divided into the register bank pointer in the higher 8 bits (RP) and the condition
code register in the lower 8 bits (CCR). (See the diagram below.)
RP
PS
bit15 bit14 bit13 bit12 bit11 bit10 bit9
R4
R3 R2 R1 R0
−
−
CCR
bit8
−
bit7
H
bit6
I
bit5
IL1
bit4
IL0
bit3
N
bit2
Z
bit1
bit0
V
C
CCR initial value
X011XXXXB
H-flag
I-flag
IL 1,0
N-flag
Z-flag
V-flag
C-flag
X: Undefined
17
MB89051 Series
The RP points to the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule shown next.
Rule for Conversion of Actual Addresses in the General-purpose Register Area
RP higher bits
"0"
"0"
"0"
"0"
"0"
"0"
OP code lower bits
"0"
"1"
R4
R3
R2
R1
R0
b2
b1
b0
Generated address A15 A14 A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that
control CPU operations at the time of an interrupt.
H flag
I flag
IL1, 0
IL1
IL0
0
0
0
1
1
0
2
1
1
3
N flag
Z flag
V flag
C flag
18
: The flag is set to “1” when an arithmetic operation results in a carry from bit 3 to bit 4 or in a borrow
from bit 4 to bit 3. The bit is cleared to “0” in other instances.The flag is for decimal adjustment
instructions; do not use for other than additions and subtractions.
: Interrupt is enabled when this flag is set to “1.” Interrupt is disabled when this flag is set to “0.” The
flag is set to “0” when reset.
Indicates the level of the interrupt currently enabled.An interrupt is processed only if its level is
:
higher than the value this bit indicates.
Interrupt level
1
High-low
Higher
Lower = no interruption
: The flag is set to “1” when an arithmetic operation results in setting of the MSB to “1” or is cleared
to “0” when the MSB is set to “1.”
: The flag is set to “1” when an arithmetic operation results in “0” or is set to “0” in other instances.
: The flag is set to “1” when an arithmetic operation results in two’s complement overflow or is
cleared to “0” if no overflow occurs.
: The flag is set to “1” when an arithmetic operation results in a carry from bit 7 or in a borrow to bit
7. The flag is cleared to “0” if neither of them occurs. In the case of a shift instruction, the flag is
set to the shift-out value.
MB89051 Series
The following general-purpose registers are provided:
•General-purpose registers : 8-bit data storage registers
The general-purpose registers are 8 bits in length and located in the register banks in the memory.One bank
contains eight registers and the MB89051 microcontrollers allow a total of 16 banks to be used at maximum.
The bank currently in use is indicated by the register bank pointer (RP).
Register Bank Configuration
This address = 0100H + 8 × (RP)
R0
R1
R2
R3
R4
R5
R6
R7
16 banks
Memory area
19
MB89051 Series
■ I/O MAP
Address
Register
name
00H
PDR0
Port 0 data register
01H
DDR0
Port 0 direction register
02H
PDR1
Port 1 data register
03H
DDR1
Port 1 direction register
04H
PDR2
Port 2 data register
Register description
05H
Read/write
Initial value
R/W
XXXXXXXX
W
00000000
R/W
XXXXXXXX
W
00000000
R/W
00000000
Reserved area
06H
DDR2
Port 2 direction register
R/W
00000000
07H
SYCC
System clock control register
R/W
XXX 1 1 X 0 0
08H
STBC
Standby control register
R/W
0 0 0 1 XXXX
09H
WDTC
Watchdog timer control register
R/W
XXXXXXXX
0AH
TBTC
Timebase timer control register
R/W
0 0 XXX 0 0 0
Port 3 data register/Pull-up register for USB
R/W
XXXXXXXX
Port 3 data direction register/
Pull-up control register for USB
R/W
00000000
Vacancy
0BH
0CH
PDR3/USBP
0DH
DDR3/USBPC
0EH
Reserved area
0FH
Vacancy
10H
PDR4
Port 4 data register
R/W
XXXXXXXX
11H
DDR4
Port 4 direction register
R/W
00000000
12H
PDR5
Port 5 data register
R/W
XXX 1 1 XXX
13H to 15H
Reserved area
16H to 20H
Vacancy
21H
PURR0
Port 0 pullup option setting register
R/W
11111111
22H
PURR1
Port 1 pullup option setting register
R/W
11111111
23H
PURR2
Port 2 pullup option setting register
R/W
11111111
24H
PURR3
Port 3 pullup option setting register
R/W
1111111X
25H
PURR4
Port 4 pullup option setting register
R/W
11111111
Reserved area
26H
27H
CTR1
PWM control register 1
R/W
00000000
28H
CTR2
PWM control register 2
R/W
000X0000
29H
CTR3
PWM control register 3
R/W
X 0 0 0 XXXX
2AH
CMR1
PWM compare register 1
W
XXXXXXXX
2BH
CMR2
PWM compare register 2
W
XXXXXXXX
2CH
CKR
Clock output control register
R/W
XXXXXXX 0 0
2DH
SCS
Serial clock switching register
R/W
XXXXXXX 0
(Continued)
20
MB89051 Series
Address
Register
name
2EH
FMCS
Flash memory control status register
(Only built-in Flash Memory products)
2FH
SMC1
30H
SMC2
31H
SSD
32H
SIDR/SODR
33H
SRC
34H
35H
36H
37H
38H
IBSR
IBCR
ICCR
IADR
IDAR
Register description
Read/write
Initial value
R, R/W
000X00X0
Serial mode control register 1
R/W
00000000
Serial mode control register 2
R/W
00000000
R
0 0 0 0 1 XXX
Serial input/serial output data register
R/W
XXXXXXXX
Serial rate control register
Serial status and control register
R/W
XXXXXXXX
2
R
00000000
2
R/W
00011000
2
R/W
0 X 0 XXXXX
2
R/W
XXXXXXXX
2
R/W
XXXXXXXX
R/W
00000000
I C bus status register
I C bus control register
I C clock regeister
I C address register
I C data register
Vacancy
39H
3AH
SMR1
Serial mode register 1
3BH
SDR1
Serial data register 1
R/W
XXXXXXXX
3CH
EIE
External interrupt control register
R/W
00000000
3DH
EIF
External interrupt flag register
R/W
XXXXXXX 0
3EH, 3FH
Vacancy
40H
HMDR
HUB mode register
R/W
1 0 XXXXX 0
41H
HDSR1
Hub descriptor register 1
R/W
XXXXXXXX
42H
HDSR2
Hub descriptor register 2
R/W
XXXXXXXX
43H
HDSR3
Hub descriptor register 3
R/W
XXXXXXXX
44H
HSTR
Hub status register
R/W
00000000
45H
OCCR
Over current register
R/W
0 XXX 0 0 0 0
46H
DADR
Descriptor ROM address register
R/W
XXXXXXXX
47H
Reserved area
48H, 49H
Vacancy
4AH
SMR2
Serial mode register 2
R/W
00000000
4BH
SDR2
Serial data register 2
R/W
XXXXXXXX
R/W
0 0 0 0 0 1 01
4CH, 4DH
4EH
Vacancy
HDSR4
Hub descriptor register 4
Vacancy
4FH
50H
UMDR
USB reset mode register
R/W
1 0 0 0 XX 0 0
51H
DBAR
DMA base address register
R/W
XXXXXXXX
52H
TDCR0
Transfer data count register 0
R/W
X0000000
53H
TDCR1
Transfer data count register 1
R/W
X0000000
R/W
X0000000
Reserved area
54H
55H
TDCR21
Transfer data count register 2
(Continued)
21
MB89051 Series
(Continued)
Address
Register
name
Register description
56H
Initial value
Reserved area
57H
TDCR3
Transfer data count register 3
R/W
X0000000
58H
UCTR
USB control register
R/W
00000000
59H
USTR1
USB status register 1
R/W
00000000
5AH
USTR2
USB status register 2
R
XXXXXX 0 0
5BH
UMSKR
USB interrupt mask register
R/W
00000000
5CH
UFRMR1
USB frame status register 1
R
XXXXXXXX
5DH
UFRMR2
USB frame status register 2
R
XXXXXXXX
5EH
EPER
USB endpoint enable register
R/W
XXXX 0 0 0 1
5FH
EPBR0
End point setup register 0
R/W
X0000000
60H
EPBR11
Endpoint setup register 11
R/W
XX 0 0 0 0 XX
61H
EPBR12
Endpoint setup register 12
R/W
X0000000
62H
EPBR21
Endpoint setup register 21
R/W
XX 0 0 0 0 XX
63H
EPBR22
Endpoint setup register 22
R/W
X0000000
64H
EPBR31
Endpoint setup register 31
R/W
XX 0 0 0 0 XX
65H
EPBR32
Endpoint setup register 32
R/W
X0000000
66H
Reserved area
67H to 78H
Vacancy
79H
Reserved area
7AH
Vacancy
7BH
ILR1
Interrupt level setting register 1
W
11111111
7CH
ILR2
Interrupt level setting register 2
W
11111111
7DH
ILR3
level setting register 3
W
11111111
7EH
ILR4
Interrupt level setting register 4
W
11111111
7FH
Reserved area
• Information about read/write
R/W: Read/write enabled, R: Read only, W: Write only
• Information about initial values
0: The initial value of this bit is “0”.
1: The initial bit of this bit is “1”.
X: The initial value of this bit is undefined.
Note : Vacancies and reserved spaces are not for use.
22
Read/write
MB89051 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
(VSS = 0 V)
Symbol
Rating
Unit
Remarks
Min
Max
VSS−0.3
VSS+6.0
V
VSS−0.3
VCC+0.3
V
Other than P31 to P37, P46,
P47, P53, P54*1
VSS−0.3
3.3
V
P31 to P37
VSS−0.3
VSS+6.0
V
P46,P47,P53, P54*1
VSS−0.3
VCC+0.3
V
Other than P31 to P37, P46,
P47, P53, P54,
CLK1, CLK2, USBP
VSS−0.3
3.6
V
P31 to P37, CLK1, CLK2,
USBP
VSS−0.3
VSS+6.0
V
P46, P47, P53, 54
ICLAMP
−2.0
2.0
mA
*5
Σ|ICLAMP|

20
mA
*5
IOL

15
mA
Normal output*2
“L” level average output current
IOLAV

4
mA
Normal output*3
“L” level total maximum output current
ΣIOL

100
mA
Total normal output
ΣIOLAV

40
mA
Total normal output*4
IOH

−15
mA
Normal output*2
IOHAV

−4
mA
Normal output*3

−50
mA
Total normal output

−10
mA
Total output of P31 to P37,
CLK1, CLK2, USBP.

−20
mA
Total normal output*4

−10
mA
Total output of P31 to P37,
CLK1, CLK2 and USBP.*4
Power supply voltage
Input voltage
Output voltage
Maximum clamp current
Total maximum clamp cuurent
“L” level maximum output current
“L” level total average output current
“H” level maximum outputcurrent
“H” level average outputcurrent
VCC
VI
VO
“H” level total maximum output current
“H” level maximum outputcurrent
“H” level average total output currnt
ΣIOH
ΣIOHAV
Power consumption
PD

300
mW
Operating temperature
TA
−40
+85
°C
Tstg
−55
+150
°C
Storage temperature
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
*1 : VI should not exceed the specified ratings. However, if the maximum current to /from an input is limited by some
means with external components, the ICLAMP rating supersedes the VI rating.
*2 : Maximum output current is defined as the peak value at one curresponding pin.
*3 : Average output current is defined as the average current flowing through one corresponding pin in an internal
of 100 ms. (Average value : operating current × operating duty)
23
MB89051 Series
*4 : Average total output current is defined as the average current flowing through all corresponding pins in an
internal of 100 ms.
*5 : • Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P40 to P45
• Use within recommended operating conditions.
• Use at DC voltage (current)
• The +B signal should always be applied with a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current
to the microcontroller pin does not exceed rated values, either instaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potentional may pass through the protective diode and increase the potentional at the VCC pin, and this may
affect other devices.
• Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply
is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on result.
• Care must be taken not to leave the +B input pin open.
• Note that analog system input pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.)
cannot accept +B signl input.
• Sample recommended circuits :
• Input/Output Equivalent circuits
Protective diode
VCC
Limiting
resistance
P-ch
+B input (0 V to 16 V)
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
24
MB89051 Series
2. Recommended Operating Conditions
Parameter
Symbol
Power supply voltage
VCC
Operating temperature
(VSS = 0 V)
Value
Unit
Remarks
Min
Typ
Max
4.5

5.5
V
At VCC = 5.0 V
3.0

3.6
V
At VCC = 3.3 V*
−40

+85
°C
When the USB function is not
in use.
0

+70
°C
When the USB function is in
use
TA
Smoothing capacitor
CS
0.1

1.0
µF
At VCC = 5.0 V*
Series resistance
RS

16

Ω
When the USB function is in
use
*: Use either a ceramic capacitor or a capacitor with similar frequency characteristics.The capacity of the smoothing
capacitor for the Vcc pin should be greater than that of the Cs.When using with a supply voltage of 3.3 V, connect
pin C with Vcc to input 3.3 V.
• C and USB Port Connection Diagram
RS
D2VP
RS
D2VM
RS
D3VP
RS
RPVP
RS
D3VM
RS
RPVM
RS
D4VP
RS
C
CS
D4VM
RS
D5VP
RS
D5VM
25
MB89051 Series
• Operating voltage vs. Operating frequency
5.5
Guaranteed operation range
5.0
(V)
4.5
Operating voltage VCC
4.0
3.6
Guaranteed operation range
3.0
2.0
1.0
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0 11.0 12.0 13.0
CPU operating frequency (FCH MHz)
(At instruction cycle 4/ FCH)
4.0
2.0
0.8
0.4
0.33
Minimum execution time (instruction cycle) (µs)
However, FCH = clock frequency (Fc) × 2
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
26
MB89051 Series
3. DC Characteristics (Power supply votage : 5.0 V)
Parameter
Sym
bol
Pin
Min
Typ
Max
Unit

0.7 VCC

VCC+0.3
V
P31 to P37

2.5

3.3
V
RST,
UCK, UI

0.8 VCC

VCC+0.3
V
VIHS INT1 to INT7,
SCK1, SCK2,
SI1, SI2

2.9

3.3
V
VIHI2C SCL, SDA

0.8 VCC

VCC+5.5
V
P00 to P07,
P10 to P17,
P20 to P27,
P40 to P47,
P53, P54,
MOD0,
MOD1,
MOD2

VSS−0.3

0.3 VCC
V
P31 to P37

VSS−0.3

0.9
RST,
INT1 to INT7,
UCK, UI

VSS−0.3

0.2 VCC
INT1 to INT7,
SCK1, SCK2,
SI1, SI2

VSS−0.3

0.6

VSS−0.3

0.3 VCC
V

VSS−0.3

VCC+0.3
V
“H” level
Input voltage
VIL
“L” level
Input voltage
VILS
VILI2C SCL, SDA
“H” level
Output voltage
Value
P00 to P07,
P10 to P17,
P20 to P27,
P40 to P47,
P53, P54,
MOD0,
MOD1,
MOD2
VIH
Open-drain output application
voltage
Condition
(VCC = 5.0 V, VSS = 0 V, TA = −40 °C to +85 °C)
VD1
VOH
P53, P54
Remarks
3V
3V
3V
V
3V
P00 to P07,
P10 to P17,
P20 to P24,
P40 to P47
IOH = −2.0 mA
4.0


V
P31 to P37,
CLK1, CLK2
IOH = −1.0 mA
2.6

3.6 V
V
3V
USBP
IOH = −2.4 mA
3.0

3.6 V
V
USB Pull up
(Continued)
27
MB89051 Series
(Continued)
Parameter
“L” level
Output voltage
Input leakage
current
(Hi-Z output
leakage current)
Open-drain output leakage current
Pullup
resistance
(VCC = 5.0 V, VSS = 0 V, TA = −40 °C to + 85 °C)
Sym
bol
VOL
ILI
Pin
Input
capacitance
28
Unit
Remarks
Typ
Max
IOL = 4.0 mA


0.4
V
P31 to P37,
IOL = 1.0 mA
CLK1, CLK2


0.4
V
3V
P00 to P07,
P10 to P17,
P20 to P27,
P31 to P37,
P40 to P47,
−5

+5
µA
When no pullup
re sistance is
speci fied
CLK1, CLK2
−5

+5
µA
USBP
−5

+5
µA


+5
µA
P00 to P07,
P10 to P17,
P20 to P24,
P40 to P47,
P53, P54,
RST
P00 to P07,
P10 to P17,
P20 to P27,
P31 to P37,
P40 to P47,
P53, P54,
RST
ICC
Power supply
current
Value
Min
ILIOD P53, P54
RPULL
Condition
0.0 V < VI < VCC
0.0 V < VI < VSS + 5.5 V
VI = 0.0 V
25
50
100
kΩ
RST is excluded
when pullup
resistance
available is
specified.
FCH = 12.0 MHz,
VCC = 5.0 V,
tinst = 0.333 µs

29
42
mA
MB89F051

28
41
mA
MB89051
ICCS1
FCH = 12.0 MHz,
VCC = 5.0 V,
tinst = 0.333 µs

20
30
mA
Sleep mode
ICCH
TA = + 25 °C

40
70
µA
Stop

5
15
pF
VCC
CIN
Other than
VCC, VSS and f = 1 MHz
C
MB89051 Series
4. DC Characteristics (Power supply votage : 3.3 V)
Parameter
Sym
bol
Pin
Condition
VIH
P00 to P07,
P10 to P17,
P20 to P27,
P31 to P37,
P40 to P47,
P53, P54,
MOD0, MOD1,
MOD2
VIHS
RST,
UCK, UI,
INT1 to INT7,
SCK1, SCK2,
SI1, SI2
Unit
Typ
Max

0.7 VCC

VCC+0.3
V

0.8 VCC

VCC+0.3
V

0.8 VCC

VCC+5.5
V
VIL
P00 to P07,
P10 to P17,
P20 to P27,
P31 to P37,
P40 to P47,
P53, P54,
MOD0, MOD1,
MOD2

VSS−0.3

0.3 VCC
V
VILS
RST,
INT1 to INT7,
UCK, UI,
INT1 to INT7,
SCK1, SCK2,
SI1, SI2

VSS−0.3

0.2 VCC
V

VSS−0.3

0.3 VCC
V

VSS−0.3

VCC+0.3
V
IOH = −2.0 mA
2.6


V
VOH P31 to P37,
CLK1, CLK2
IOH = −1.0 mA
2.6


V
USBP
IOH = −2.4 mA
3.0


V
VIHI2C SCL, SDA
“L” level
Input voltage
VILI2C SCL, SDA
VD1
P53, P54
P00 to P07,
P10 to P17,
P20 to P24,
P40 to P47
“H” level
Output voltage
Value
Min
“H” level
Input voltage
Open-drain
output application
voltage
(VCC = 3.3 V, VSS = 0 V, TA = −40 °C to +85 °C)
Remarks
USB Pull up,
Vcc = 3.1 V to
3.6 V
(Continued)
29
MB89051 Series
(Continued)
Parameter
“L” level
Output voltage
Input leakage
current
(Hi-Z output
leakage current)
Open-drain
output leakage
current
Pullup
resistance
(VCC = 3.3 V, VSS = 0 V, TA = −40 °C to +85 °C)
Sym
bol
VOL
ILI
Pin
Input
capacitance
30
Unit
Typ
Max
IOL = 4.0 mA


0.4
V
P31 to P37,
IOL = 1.0 mA
CLK1, CLK2


0.4
V
P00 to P07,
P10 to P17,
P20 to P27,
P31 to P37,
P40 to P47,
−5

+5
µA
CLK1, CLK2
−5

+5
µA
USBP
−5

+5
µA


+5
µA
P00 to P07,
P10 to P17,
P20 to P24,
P40 to P47,
P53, P54,
RST
P00 to P07,
P10 to P17,
P20 to P27,
P31 to P37,
P40 to P47,
P53, P54,
RST
ICC
Power supply
current
Value
Min
ILIOD P53, P54
RPULL
Condition
0.0 V < VI < VCC
0.0 V < VI < VSS+5.5 V
Remarks
When no pullup
resistance is
specified
RST is excluded
when pullup
resistance
available is
specified.
VI = 0.0 V
25
50
100
kΩ
FCH = 12.0 MHz,
VCC = 3.3 V,
tinst = 0.333 µs

29
42
mA MB89F051

28
41
mA MB89051
ICCS1
FCH = 12.0 MHz,
VCC = 3.3 V,
tinst = 0.333 µs

20
30
mA Sleep mode
ICCH
TA = +25 °C

40
70
µA

10

pF
VCC
CIN
Other than
f = 1 MHz
Vcc and Vss
Stop
MB89051 Series
5. AC Characteristics
(1) Reset Timing
(VCC = 5.0 V, VSS = 0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Condition
tZLZH

RST “L” pulse width
Value
Min
Max
48 tHCYL

Unit
Remarks
ns
Notes : • tHCYL is the oscillation cycle for the internal main clock.
• If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause
malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external
reset pin (RST).
tZLZH
RST
0.2 VCC
0.2 VCC
(2) Power-on reset
(VSS = 0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Condition
Power supply rising time
tR
Power supply cutoff time
tOFF
Value
Unit
Min
Max

0.066
50
ms

4

ns
Remarks
Due to repeated
operations
Note : The power supply must be up within the selected oscillation stabilization time.
When the supply voltage needs to be varied while operating, it is recommended to smoothly start up the
voltage.
tR
tOFF
3.5 V
VCC
0.2 V
0.2 V
0.2 V
31
MB89051 Series
(3) Clock Timing
(VSS = 0 V, TA = −40 °C to +85 °C)
Parameter
Symbol Pin name Condition
Value
Min
Typ
Max
Unit
Clock frequency
FC
X0, X1

6

MHz
Clock cycle time
tXCYL
X0, X1

166.6

ns
Internal main clock
frequency
FCH


12

MHz
Internal clock cycle
tHCYL


83.3

ns

Remarks
Twice the
Fc
tXCYL/2
• X0 and X1 Timing and Conditions
tXCYL
X0
0.2 VCC
0.2 VCC
• Clock Conditions
When a crystal resonator is used
X0
X1
C1
C2
(4) Instruction Cycle
Parameter
Instruction cycle
(Min execution time)
32
(VSS = 0 V, TA = −40 °C to +85 °C)
Symbol
Value
Unit
Remarks
tinst
4 / FCH, 8 / FCH,
16 / FCH, 64 / FCH
µs
When operating at FCH = 12 MHz
tinst = 0.33 µs (4 / FCH)
MB89051 Series
(5) UART Serial I/O Timing
Parameter
(VCC = 5.0 V, VSS = 0 V, TA = −40 °C to +85 °C)
Symbol
Pin name
Serial clock cycle time
tSCYC
UCK
UCK ↓ → UO
tSLOV
UCK, UO
Valid UI → UCK ↑
tIVSH
UI, UCK
UCK ↑ → valid UI hold time
tSHIX
UCK, UI
Serial clock “H” pulse width
tSHSL
Serial clock “L” pulse width
tSLSH
UCK ↓ → UO time
tSLOV
UCK, UO
Valid UI → UCK ↑
tIVSH
UI, UCK
UCK ↑ → valid UI hold time
tSHIX
UCK, UI
Value
Condition
Internal shift
clock mode
UCK
External
shift clock
mode
Unit
Min
Max
2 tinst*

µs
−200
+200
ns
200

ns
200

ns
1 tinst*

µs
1 tinst*

µs
0
200
ns
200

ns
200

ns
Remarks
* : For information on tinst, see “ (4) Instruction Cycle”.
• Internal shift clock mode
tSCYC
UCK
0.8 Vcc
0.2 Vcc
0.2 Vcc
tSLOV
0.8 Vcc
0.2 Vcc
UO
tIVSH
tSHIX
0.8 VCC
0.2 VCC
UI
0.8 VCC
0.2 VCC
• External shift clock mode
tSLSH
tSHSL
UCK
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tSLOV
UO
0.8 Vcc
0.2 Vcc
tIVSH
UI
0.8 VCC
0.2 VCC
tSHIX
0.8 VCC
0.2 VCC
33
MB89051 Series
(6) Serial I/O Timing
(VCC = 5.0 V, Vss = 0V, TA = −40 °C to +85 °C)
Parameter
Symbol
Pin name
Condition
Serial clock cycle time
tSCYC
SCK1, SCK2
SCK ↓ → SO time
tSLOV
SCK1, SO1,
SCK2, SO2
Valid SI → SCK ↑
tIVSH
SCK1, SI1,
SCK2, SI2
SCK ↑ → Valid SI hold time
tSHIX
Serial clock “H” pulse width
Value
Max
2 tinst*

µs
−200
+200
ns
200

ns
SCK1, SI1,
SCK2, SI2
200

ns
tSHSL
SCK1, SCK2
tinst*

µs
Serial clock “L” pulse width
tSLSH
SCK1, SCK2
tinst*

µs
SCK ↓ → SO time
tSLOV
SCK1, SO1,
SCK2, SO2
0
200
ns
Valid SI → SCK
tIVSH
SCK1, SI1,
SCK2, SI2
200

µs
SCK ↑ → Valid SI hold time
tSHIX
SCK1, SI1,
SCK2, SI2
200

µs
Internal
shift clock
mode
External
shift clock
mode
* : For information on tinst, see “ (4) Instruction Cycle”.
• Internal shift clock mode
tSCYC
2.9
SCK1
SCK2
0.6
0.6
tSLOV
2.9
SO1
SO2
0.6
tIVSH
SI1
SI2
tSHIX
2.9
2.9
0.6
0.6
• External shift clock mode
tSLSH
tSHSL
2.9
SCK1
SCK2
0.6
0.6
tSLOV
SO1
SO2
2.9
0.6
tIVSH
SI1
SI2
34
Unit
Min
tSHIX
2.9
2.9
0.6
0.6
2.9
Remarks
MB89051 Series
(7) Peripheral Input Timing
(VCC = 5.0 V, VSS = 0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Peripheral input “H” pulse
width 1
tILIH1
Peripheral input “L” pulse
width 1
tIHIL1
Pin name
Condition
Value
Unit
Min
Max

2 tinst*

µs

2 tinst*

µs
Remarks
INT1 to INT7
* : For information on tinst, see “ (4) Instruction Cycle”.
tIHIL1
tILIH1
INT1 ~ INT7
2.9
0.6
0.8 VCC
0.6
35
MB89051 Series
(8) I2C Timing
(VCC = 5.0 V, VSS = 0 V, TA = −40 °C to +85 °C)
Sym
bol
Pin
Start condition output
tSTA
Stop condition output
Parameter
Value
Unit
Max
SCL,
SDA
1 / 4 × tinst*1 ×
mt* × nt*3 − 20
1 / 4 × tinst*1 ×
mt*2 × nt*3 + 20
ns
Master
mode
tSTO
SCL,
SDA
1 / 4 × tinst*1 ×
(mt*2 × nt*3 + 8) − 20
1 / 4 × tinst*1 ×
(mt*2 × nt*3 + 8) + 20
ns
Master
mode
Start condition detect
tSTA
SCL,
SDA
1 / 4 × tinst*1 × 6 + 40

ns
Stop condition detect
tSTO
SCL,
SDA
1 / 4 × tinst*1 × 6 + 40

ns
Restart condition output tSTASU
SCL,
SDA
1 / 4 × tinst*1 ×
(mt*2 × nt*3 + 8) − 20
1 / 4 × tinst*1 ×
(mt*2 × nt*3 + 8) + 20
ns
Restart condition detect tSTASU
SCL,
SDA
1 / 4 × tinst*1 × 4 + 40

ns
SCL output Low width
tLOW
SCL
1 / 4 × tinst*1 × mt*2 × nt*3
− 20
1 / 4 × tinst*1 × mt*2 × nt*3
+ 20
ns
Master
mode
SCL output High width
tHIGH
SCL
1 / 4 × tinst*1 ×
(mt*2 × nt*3 + 8) − 20
1 / 4 × tinst*1 ×
(mt*2 × nt*3 + 8) + 20
ns
Master
mode
tDO
SDA
1 / 4 × tinst*1 × 4 − 20
1 / 4 × tinst*1 × 4 + 20
ns
SDA output setup time
after interrupt
tDOSU SDA
1 / 4 × tinst*1 × 4 − 20

ns
SCL input Low pulse
width
tLOW
SCL
1 / 4 × tinst*1 × 6 + 40

ns
SCL input High pulse
width
tHIGH
SCL
1 / 4 × tinst*1 × 2 + 40

ns
SDA input setup time
tSU
SDA
40

ns
SDA hold time
tHO
SDA
0

ns
SDA output delay
*1 : For information on tinst, see “ (4) Instruction Cycle”.
*2 : m is defined in the ICCR CS 4 to CS 3 (bit 4 to bit 3) .
*3 : n is defined in the ICCR CS 2 to CS 0 (bit 2 to bit 0) .
Data transmit (master/slave)
tDO
tDO
tSU
SDA
tSU
tDOSU
ACK
tSTASU tSTA
tLOW
tHO
1
SCL
9
Data receive (master/slave)
tHO
tSU
tDO
SDA
SCL
tDO
tDOSU
ACK
tHIGH
36
Remarks
Min
6
7
tLOW
tSTO
8
9
Master
mode
MB89051 Series
6. FLASH Program/Erase characteristics
• Program/Erase characteristics
Parameter
Condition
Value
Unit
Remarks
Min
Typ
Max

1
15
s
Except for the write time before internal
erase operation

5
75
s
Except for the write time before internal
erase operation
Byte program time

8
3,600
µs
Except for the over head time of the system.
Prgram/erase cycle
10,000


cycle
Sector erase time
Chip erase time
TA = +25 °C
Vcc = 5.0 V
37
MB89051 Series
■ ORDERING INFORMATION
Part Number
MB89051PFM
MB89F051PFM
38
Package
64-pin plastic LQFP
(FPT-64P-M09)
Remarks
MB89051 Series
■ PACKAGE DIMENSIONS
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
64-pin plastic LQFP
(FPT-64P-M09)
14.00±0.20(.551±.008)SQ
* 12.00±0.10(.472±.004)SQ
48
0.145±0.055
(.0057±.0022)
33
49
32
0.10(.004)
Details of "A" part
+0.20
1.50 –0.10
+.008
.059 –.004
(Mounting height)
0.25(.010)
INDEX
0~8˚
64
17
1
0.65(.026)
C
"A"
16
0.32±0.05
(.013±.002)
0.13(.005)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
(Stand off)
M
2003 FUJITSU LIMITED F64018S-c-3-5
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
39
MB89051 Series
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
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assumes no liability for any damages whatsoever arising out of
the use of the information.
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function and schematic diagrams, shall not be construed as license
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from the use of information contained herein.
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and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
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and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
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launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
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must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
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of those products from Japan.
F0303
 FUJITSU LIMITED Printed in Japan