Revised September 2000 74ACT818 8-Bit Diagnostic Register General Description Features The ACT818 is a high-speed, general-purpose pipeline register with an on-board diagnostic register for performing serial diagnostics and/or writable control store loading. ■ On-line and off-line system diagnostics The D-to-Y path provides an 8-bit parallel data path pipeline register for normal system operation. The diagnostic register can load parallel data to or from the pipeline register and can output data through the D input port (as in WCS loading). ■ Diagnostic register and diagnostic testing The 8-bit diagnostic register has multiplexer inputs that select parallel inputs from the Y-port or adjacent bits in the diagnostic register to operate as a right-shift-only register. This register can then participate in a serial loop throughout the system where normal data, address, status and control registers are replaced with ACT818 diagnostic pipeline registers. The loop can be used to scan in a complete test routine starting point (Data, Address, etc.). Then after a specified number of machine cycles it scans out the results to be inspected for the expected results. WCS loading can be accomplished using the same technique. An instruction word can be serially shifted into the shadow register and written into the WCS RAM by enabling the D output. ■ Outputs source/sink 24 mA ■ Swaps the contents of diagnostic register and output register ■ Cascadable for wide control words as used in microprogramming ■ Edge-triggered D registers ■ ACT818 has TTL-compatible inputs ■ ACT818 is functionally- and pin-compatible to AMD Am29818 and MMI 74S818 Applications • Register for microprogram control store • Status register • Data register • Instruction register • Interrupt mask register • Pipeline register • General purpose register • Parallel-serial/serial-parallel converter Ordering Code: Order Number Order Package 74ACT818SPC N24C Package Description 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Logic Symbol Connection Diagram FACT is a trademark of Fairchild Semiconductor Corporation. © 2000 Fairchild Semiconductor Corporation DS009801 www.fairchildsemi.com 74ACT818 8-Bit Diagnostic Register July 1988 74ACT818 Pin Descriptions Functional Description Pin Names Data transfers into the diagnostic register occur on the LOW-to-HIGH transition of DCLK. Mode and SDI determine what data source will be loaded. The pipeline register is loaded on the LOW-to-HIGH transition of PCLK. Mode selects whether the data source is the data input or the diagnostic register output. Because of the independence of the clock inputs, data can be shifted in the diagnostic register via DCLK and loaded into the pipeline register from the data input via PCLK simultaneously, as long as no setup or hold times are violated. This simultaneous operation is legal. Description D0–D7 Data Inputs SDI Serial Data Input DCLK Diagnostics Clock MODE Control Input PCLK Pipeline Register Clock OEY Output Enable Input SDO Serial Data Output Y0–Y7 Data Outputs Function Table Inputs SDI X Outputs MODE DCLK PCLK L X L L H X X H X H H X X SDO Diagnostic Reg. Pipeline Reg. S7 SI<SI − 1, NA Operation Serial Shift; D7–D0 Disabled SO<SDI S7 NA PI<DI L SI<YI NA Normal Load Pipeline Register Load Diagnostic Register from Y; SDI NA PI<SI Load Pipeline Register from X H Hold NA Hold Diagnostic Register; DI DI Disabled Diagnostic Register Enabled H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition Diagnostic Register www.fairchildsemi.com Block Diagram 2 Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC +0.5V +20 mA DC Input Voltage (VI) Supply Voltage (VCC) 0V to VCC Output Voltage (VO) −0.5V to VCC +0.5V 0V to VCC −40°C to +85°C Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) DC Output Diode Current (IOK) VO = −0.5V −20 mA VO = VCC + 0.5V 125 mV/ns VIN from 0.8V to 2.0V +20 mA DC Output Voltage (VO) 4.5V to 5.5V Input Voltage (VI) VCC @ 4.5V, 5.5V −0.5V to VCC + 0.5V DC Output Source ± 50 mA or Sink Current (IO) DC VCC or Ground Current ± 50 mA per Output Pin (I CC or IGND) Storage Temperature (TSTG) Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. −65°C to +150 °C Junction Temperature (TJ) 140°C PDIP DC Electrical Characteristics Symbol Parameter VCC TA = +25°C (V) Typ TA = −40°C to +85°C Units Minimum HIGH Level 4.5 1.5 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 IIN Maximum Input Leakage Current 5.5 ± 0.1 ± 1.0 µA IOZ Maximum 3-STATE 5.5 ± 0.5 ± 5.0 µA 5.5 8.0 80.0 µA 1.5 mA VIH VIL Leakage Current ICC Maximum Quiescent Supply Current ICCT Maximum Additional ICC/Input VOH Conditions Guaranteed Limits 5.5 V V VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V VIN = VCC OE = VIH VOUT = 0V, VCC VIN = VCC or GND VIN = VCC − 2.1V VCC = 5.5V VIN = VIL or VIH Minimum HIGH Level Output Voltage, 4.5 3.86 3.76 V IOH = −24 mA Y0–Y7 Outputs 5.5 4.86 4.76 V IOH =−24 mA (Note 2) Level Output Voltage, 4.5 3.86 3.76 V IOH = −8 mA D0–D7, SDO Outputs 5.5 4.86 4.76 V IOH = −8 mA 4.5 0.36 0.44 V IOL = 24 mA Minimum HIGH VOL Level Output Voltage, IOLD Y0–Y7 Outputs 5.5 0.36 0.44 V IOL = 24 mA (Note 2) Maximum LOW Level Output Voltage, 4.5 0.36 0.44 V IOL = 8 mA D0–D7, SDO Outputs 5.5 0.36 0.44 V IOL = 8 mA 5.5 75 mA VOLD = 1.65V Max 5.5 −75 mA VOHD = 3.85V Min 5.5 32 mA VOLD = 1.65V Max 5.5 −32 mA VOHD = 3.85V Min Minimum Dynamic Output Current Y0–Y7 Outputs IOHD Minimum Dynamic Output Current Y0–Y7 Outputs IOLD Minimum Dynamic Output Current D0–D7, SDO Outputs (Note 3) IOHD VIN = VIL or VIH Maximum LOW Minimum Dynamic Output Current D0–D7, SDO Outputs (Note 3) Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Test load 50 pF, 500Ω to ground. 3 www.fairchildsemi.com 74ACT818 Absolute Maximum Ratings(Note 1) 74ACT818 AC Electrical Characteristics Symbol tPHL Parameter Propagation Delay PCLK to Y tPLH Propagation Delay PCLK to Y tPHL Propagation Delay MODE to SDO tPLH Propagation Delay MODE to SDO tPHL Propagation Delay SDI to SDO tPLH Propagation Delay SDI to SDO tPHL Propagation Delay DCLK to SDO tPLH Propagation Delay DCLK to SDO tPZL Output Enable Time OEY to Yn tPLZ Output Disable Time OEY to Yn tPZL Output Enable Time DCLK to Dn tPLZ Output Disable Time DCLK to Dn tPZH Output Enable Time OEY to Yn tPHZ Output Disable Time OEY to Yn tPZH Output Enable Time DCLK to Dn tPHZ Output Disable Time DCLK to Dn VCC TA = +25°C (V) CL = 50 pF CL = 50 pF Units (Note 4) Min Typ Max Min Max 5.0 3.0 6.0 9.0 2.5 9.5 ns 5.0 3.0 6.5 9.0 2.5 10.0 ns 5.0 4.0 8.0 11.0 3.5 12.0 ns 5.0 4.0 8.0 11.5 4.0 12.5 ns 5.0 3.5 7.5 10.5 3.0 12.0 ns 5.0 3.5 7.5 10.5 3.5 12.0 ns 5.0 4.5 9.0 12.5 4.0 14.0 ns 5.0 4.5 9.5 13.0 4.0 14.5 ns 5.0 2.5 6.0 9.0 2.5 10.0 ns 5.0 1.5 5.5 8.0 1.0 9.0 ns 5.0 3.0 8.0 12.0 3.0 13.5 ns 5.0 2.0 8.5 11.0 1.5 12.0 ns 5.0 3.0 8.0 10.0 2.5 11.0 ns 5.0 2.5 9.0 11.0 2.0 11.5 ns 5.0 3.0 6.5 11.5 3.0 13.0 ns 5.0 3.0 7.5 12.0 2.0 13.0 ns Note 4: Voltage Range 5.0 is 5.0V ± 0.5V. www.fairchildsemi.com TA = −40°C to +85°C 4 Symbol Parameter Setup Time tS D to PCLK Hold Time tH D to PCLK tH Setup Time MODE to PCLK tH Hold Time MODE to PCLK Setup Time tS Y to DCLK tS Hold Time Y to DCLK Setup Time tS MODE to DCLK Hold Time tH MODE to DCLK tS Setup Time SDI to DCLK tH Hold Time SDI to DCLK Setup Time tS DCLK to PCLK tS Setup Time PCLK to DCLK Pulse Width tW PCLK HIGH or LOW Pulse Width tW DCLK HIGH or LOW VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Units (Note 5) Typ Guaranteed Minimum 5.0 1.0 4.0 5.0 ns 5.0 0.0 1.0 1.0 ns 5.0 2.5 4.5 5.5 ns 5.0 −1.0 0.0 0.0 ns 5.0 0.5 2.5 2.5 ns 5.0 0 1.0 1.5 ns 5.0 2.0 4.0 4.0 ns 5.0 −0.5 1.0 1.0 ns 5.0 2.0 3.5 4.5 ns 5.0 −0.5 1.0 1.0 ns 5.0 6.0 9.0 10.5 ns 5.0 6.0 11.0 11.5 ns 5.0 2.0 3.0 3.0 ns 5.0 2.0 3.0 3.0 ns Note 5: Voltage range 5.0 is 5.0V ± 0.5V. Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF VCC = OPEN CPD Power Dissipation Capacitance 20 pF VCC = 5.0V 5 Conditions www.fairchildsemi.com 74ACT818 AC Operating Requirements 74ACT818 8-Bit Diagnostic Register Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6