Maxim MAX5803AUB Ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i2c interface Datasheet

MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I2C Interface
General Description
The MAX5803/MAX5804 single-channel, low-power,
8-/10-/12-bit, voltage-output this is an addition to content
digital-to-analog converters (DACs) include output
buffers and an internal reference that is selectable to
be 2.048V, 2.500V, or 4.096V. The MAX5803/MAX5804/
MAX5805 accept a wide supply voltage range of 2.7V to
5.5V with extremely low power (< 1mW) consumption to
accommodate most low-voltage applications. A precision
external reference input allows rail-to-rail operation and
presents a 100kI (typ) load to an external reference.
The MAX5803/MAX5804/MAX5805 have an I 2Ccompatible, 2-wire interface that operates at clock rates
up to 450kHz. The DAC output is buffered and has
a low supply current of 155FA (typical at 3.5V) and a
low offset error of Q0.5mV (typical). On power-up, the
MAX5803/MAX5804/MAX5805 reset the DAC outputs
to zero, providing additional safety for applications that
drive valves or other transducers which need to be off on
power-up.
The MAX5803/MAX5804/MAX5805 include a userconfigurable active-low asynchronous input, AUX for
additional flexibility. This input can be programmed to
asynchronously clear (CLR) or temporarily gate (GATE) the
DAC output to a user-programmable value. A dedicated
active-low asynchronous LDAC input is also included. This
allows simultaneous output updates of multiple devices.
Benefits and Features
S Single High-Accuracy DAC Channel
 12-Bit Accuracy Without Adjustments
 ±1 LSB INL Buffered Voltage Output
 Guaranteed Monotonic Over All Operating
Conditions
S Three Precision Selectable Internal References
 2.048V, 2.500V, or 4.096V
S Internal Output Buffer
 Rail-to-Rail Operation with External Reference
 6.3µs Settling Time
 Output Directly Drives 2kI Loads
S Small, 10-Pin, 2mm x 3mm TDFN and 3mm x 5mm
µMAX Packages
S Wide 2.7V to 5.5V Supply Range
S Fast 400kHz I2C-Compatible, 2-Wire Serial Interface
with Readback Capability
S Power-On-Reset to Zero-Scale DAC Output
S User-Configurable Asynchronous I/O Functions:
CLR, LDAC, GATE
S Three Software-Selectable Power-Down Output
Impedances: 1kI, 100kI, or High Impedance
S Low 155µA DAC Supply Current at 3V
The MAX5803/MAX5804/MAX5805 are available in 10-pin
TDFN/µMAXM packages and are specified over the -40NC
to +125NC temperature range.
Functional Diagram
VDDIO
VDD
REF
Applications
Gain and Offset Adjustment
SCL
Automatic Tuning and Optical Control
SDA
Power Amplifier Control and Biasing
Process Control and Servo Loops
Portable Instrumentation
MAX5803
MAX5804
MAX5805
INTERNAL REFERENCE /
EXTERNAL BUFFER
Programmable Voltage and Current Sources
ADDR
AUX
CODE
REGISTER
8-/10-/
12-BIT
DAC
DAC
LATCH
I2C
SERIAL
INTERFACE
CODE
LDAC
Data Acquisition
BUFFER
OUT
CLEAR /
CLEAR /
LOAD GATE
RESET
RESET
DAC CONTROL LOGIC
POR
POR
POWER
DOWN
100kI 1kI
GND
µMAX is a registered trademark of Maxim Integrated Products, Inc.
Ordering Information appears at end of data sheet.
For related parts and recommended products to use with this part, refer to: www.maximintegrated.com/MAX5803.related
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-6464; Rev 2; 6/13
MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I2C Interface
Absolute Maximum Ratings
Maximum Continuous Current into Any Pin..................... ±50mA
Operating Temperature Range......................... -40NC to +125NC
Storage Temperature Range............................. -65NC to +150NC
Lead Temperature (soldering, 10s).................................+300NC
Soldering Temperature (reflow).......................................+260NC
VDD to GND..............................................................-0.3V to +6V
VDDIO to GND..........................................................-0.3V to +6V
OUT, REF to GND.........-0.3V to lower of (VDD + 0.3V) and +6V
SCL, SDA, AUX, LDAC to GND...............................-0.3V to +6V
ADDR to GND....................................................-0.3V to lower of
(VDDIO + 0.3V) and +6V
Continuous Power Dissipation (TA = +70NC)
TDFN (derate 14.9mW/NC above +70NC)................1188.7mW
µMAX (derate 8.8mW/NC above +70NC)...................707.3mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Package Thermal Characteristics (Note 1)
TDFN
Junction-to-Ambient Thermal Resistance (θJA)........67.3NC/W
µMAX
Junction-to-Ambient Thermal Resistance (θJA)......113.1NC/W
Junction-to-Ambient Thermal Resistance (θJC)............42NC/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI , TA = -40NC to +125NC, unless otherwise noted.)
(Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC PERFORMANCE (Note 3)
Resolution and Monotonicity
Integral Nonlinearity (Note 4)
Differential Nonlinearity (Note 4)
Offset Error (Note 5)
N
INL
DNL
MAX5803
8
MAX5804
10
MAX5805
12
MAX5803, 8 bits
-0.25
±0.05
+0.25
MAX5804, 10 bits
-0.5
±0.2
+0.5
MAX5805, 12 bits
-1
±0. 5
+1
MAX5803, 8 bits
-0.25
±0.05
+0.25
MAX5804, 10 bits
-0.5
±0.1
+0.5
MAX5805, 12 bits
-1
±0.2
+1
OE
-5
±0.5
+5
GE
-1.0
±0.1
Offset Error Drift
Gain Error (Note 5)
Gain Temperature Coefficient
±10
Maxim Integrated
With respect to VREF
LSB
LSB
mV
FV/NC
+1.0
%FS
ppm of
FS/NC
±2.5
With respect to VREF
Zero-Scale Error
Full-Scale Error
Bits
0
+10
mV
-0.5
+0.5
%FS
2
MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I2C Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI , TA = -40NC to +125NC, unless otherwise noted.)
(Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DAC OUTPUT CHARACTERISTICS
No load
Output Voltage Range (Note 6)
2kI load to GND
2kI load to VDD
Load Regulation
VOUT = VFS/2
VOUT = VFS/2
DC Output Impedance
Capacitive Load Handling
CL
Resistive Load Handling
RL
Short-Circuit Output Current
0
VDD
0
VDD 0.2
0.2
VDD
VDD = 3V Q10%,
|IOUT| P 5mA
300
VDD = 5V Q10%,
|IOUT| P 10mA
300
VDD = 3V Q10%,
|IOUT| P 5mA
0.3
VDD = 5V Q10%,
|IOUT| P 10mA
0.3
FV/mA
I
500
2
VDD = 5.5V
V
pF
kI
Sourcing (output
short to GND)
30
Sinking (output
shorted to VDD)
40
mA
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate
Voltage-Output Settling Time
SR
Positive and negative
2.0
¼ scale to ¾ scale, to P 1 LSB, MAX5803
2.8
¼ scale to ¾ scale, to P 1 LSB, MAX5804
5.2
V/µs
µs
¼ scale to ¾ scale, to P 1 LSB, MAX5805
6.3
DAC Glitch Impulse
Major code transition
5.0
nV·s
Digital Feedthrough
Code = 0, all digital inputs from 0V to
VDDIO
0.5
nV·s
Startup calibration time (Note 7)
200
Fs
From power-down mode
60
Fs
VDD = 3V Q10% or 5V Q10%
100
FV/V
Power-Up Time
DC Power-Supply Rejection
Maxim Integrated
3
MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I2C Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI , TA = -40NC to +125NC, unless otherwise noted.)
(Note 2)
PARAMETER
Output Voltage-Noise Density
(DAC Output at Midscale)
SYMBOL
CONDITIONS
f = 1kHz
External reference
f = 10kHz
f = 10kHz
98
2.5V internal
reference
f = 1kHz
117
f = 10kHz
110
4.096V internal
reference
f = 1kHz
152
f = 10kHz
145
f = 0.1Hz to 10Hz
10
2.048V internal
reference
2.5V internal
reference
Integrated Output Noise
(DAC Output at Full Scale)
72
f = 0.1Hz to 300kHz
298
f = 0.1Hz to 10Hz
11
f = 0.1Hz to 10kHz
89
f = 0.1Hz to 300kHz
370
f = 0.1Hz to 10Hz
12
f = 0.1Hz to 10kHz
99
f = 0.1Hz to 300kHz
355
f = 0.1Hz to 10Hz
13
f = 0.1Hz to 10kHz
128
f = 0.1Hz to 300kHz
400
113
100
2.048V internal
reference
f = 1kHz
172
f = 10kHz
157
2.5V internal
reference
f = 1kHz
195
f = 10kHz
180
4.096V internal
reference
f = 1kHz
279
f = 10kHz
258
f = 0.1Hz to 10Hz
12
f = 0.1Hz to 10kHz
88
f = 0.1Hz to 300kHz
280
2.048V internal
reference
2.5V internal
reference
4.096V internal
reference
Maxim Integrated
f = 0.1Hz to 10kHz
f = 10kHz
External reference
UNITS
108
f = 1kHz
External reference
MAX
79
f = 1kHz
4.096V internal
reference
Output Voltage-Noise Density
(DAC Output at Full Scale)
TYP
88
2.048V internal
reference
External reference
Integrated Output Noise
(DAC Output at Midscale)
MIN
f = 0.1Hz to 10Hz
14
f = 0.1Hz to 10kHz
135
f = 0.1Hz to 300kHz
530
f = 0.1Hz to 10Hz
15
f = 0.1Hz to 10kHz
160
f = 0.1Hz to 300kHz
550
f = 0.1Hz to 10Hz
23
f = 0.1Hz to 10kHz
220
f = 0.1Hz to 300kHz
610
nV/√Hz
FVP-P
nV/√Hz
FVP-P
4
MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I2C Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI , TA = -40NC to +125NC, unless otherwise noted.)
(Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
REFERENCE INPUT
Reference Input Range
VREF
Reference Input Current
IREF
Reference Input Impedance
RREF
1.24
VREF = VDD = 5.5V
55
VDD
V
75
FA
75
100
VREF = 2.048V, TA = +25NC
2.043
2.048
2.053
VREF = 2.5V, TA = +25NC
2.494
2.500
2.506
VREF = 4.096V, TA = +25NC
4.086
4.096
4.106
kI
REFERENCE OUPUT
Reference Output Voltage
VREF
VREF = 2.048V
Reference Output Noise Density
VREF = 2.500V
VREF = 4.096V
VREF = 2.048V
Integrated Reference Output
Noise
VREF = 2.500V
VREF = 4.096V
f = 1kHz
129
f = 10kHz
122
f = 1kHz
158
f = 10kHz
151
f = 1kHz
254
f = 10kHz
237
f = 0.1Hz to 10Hz
12
f = 0.1Hz to 10kHz
110
f = 0.1Hz to 300kHz
390
f = 0.1Hz to 10Hz
15
f = 0.1Hz to 10kHz
129
f = 0.1Hz to 300kHz
430
f = 0.1Hz to 10Hz
20
f = 0.1Hz to 10kHz
205
f = 0.1Hz to 300kHz
525
nV/√Hz
FVP-P
Reference Temperature
Coefficient (Note 8)
MAX5805A
±4
±12
MAX5803/MAX5804/MAX5805B
±10
±25
Reference Drive Capacity
External load
Reference Capacitive Load
Handling
Reference Load Regulation
Reference Line Regulation
Maxim Integrated
ISOURCE = 0 to 500FA
V
ppm/NC
25
kI
200
pF
1.0
mV/mA
0.1
mV/V
5
MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I2C Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI , TA = -40NC to +125NC, unless otherwise noted.)
(Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
Supply Voltage
I/O Supply Voltage
VDD
VREF = 4.096V
4.5
5.5
All other options
2.7
5.5
1.8
5.5
VDDIO
External reference
Supply Current (DAC Output at
Midscale) (Note 9)
IDD
Internal reference,
reference pin
undriven
Internal reference,
reference pin driven
External reference
Supply Current (DAC Output at
Full Scale) (Note 9)
IDD
Internal reference,
reference pin
undriven
Internal reference,
reference pin driven
Power-Down Mode Supply
Current (DAC Powered Down,
Reference Remains Active)
(Note 9)
Power-Down Mode Supply
Current (Note 9)
Digital Supply Current (Note 9)
IDD
IPD
Internal reference,
reference pin driven
VREF = 3V
135
190
VREF = 5V
165
225
VREF = 2.048V
190
265
VREF = 2.5V
205
280
VREF = 4.096V
250
340
VREF = 2.048V
215
300
VREF = 2.5V
225
315
VREF = 4.096V
275
375
V
V
FA
VREF = 3V
155
210
VREF = 5V
200
265
VREF = 2.048V
205
280
VREF = 2.5V
220
300
VREF = 4.096V
275
375
VREF = 2.048V
225
310
VREF = 2.5V
240
330
VREF = 4.096V
300
410
VREF = 2.048V
90
135
VREF = 2.5V
93
135
VREF = 4.096V
100
150
0.4
2
FA
1.0
FA
External reference, VDD = VREF
IDDIO
FA
FA
DIGITAL INPUT CHARACTERISTICS (SCL, SDA, ADDR, AUX, LDAC)
Input High Voltage
Input Low Voltage
Maxim Integrated
2.2V < VDDIO < 5.5V
0.7 x
VDDIO
1.8V < VDDIO < 2.2V
0.8 x
VDDIO
VIH
V
2.2V < VDDIO < 5.5V
0.3 x
VDDIO
1.8V < VDDIO < 2.2V
0.2 x
VDDIO
VIL
V
6
MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I2C Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI , TA = -40NC to +125NC, unless otherwise noted.)
(Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Hysteresis Voltage
VH
0.15
Input Leakage Current (Note 9)
IIN
±0.1
Input Capacitance
ADDR Pullup/Pulldown Strength
CIN
RPU, RPD
MAX
UNITS
±1
FA
90
kI
0.2
V
400
kHz
V
3
(Note 10)
30
50
pF
DIGITAL OUTPUT (SDA)
Output Low Voltage
VOL
ISINK = 3mA
I2C TIMING CHARACTERISTICS (SCL, SDA, AUX, LDAC)
SCL Clock Frequency
fSCL
Bus Free Time Between a STOP
and a START Condition
tBUF
1.3
µs
Hold Time Repeated for a START
Condition
tHD;STA
0.6
µs
SCL Pulse Width Low
tLOW
1.3
µs
SCL Pulse Width High
tHIGH
0.6
µs
Setup Time for Repeated START
Condition
tSU;STA
0.6
µs
Data Hold Time
tHD;DAT
0
Data Setup Time
tSU;DAT
100
SDA and SCL Receiving Rise
Time
tR
20 +
CB/10
300
ns
SDA and SCL Receiving Fall
Time
tF
20 +
CB/10
300
ns
SDA Transmitting Fall Time
tF
20 +
CB/10
250
ns
400
pF
Setup Time for STOP Condition
CB
Pulse Width of Suppressed Spike
tSP
CLR Removal Time Prior to a
Recognized START
VDD = 2.7V to 5.5V
ns
ns
0.6
tSU;STO
Bus Capacitance Allowed
900
µs
10
50
ns
tCLRSTA
100
ns
CLR Pulse Width Low
tCLPW
20
ns
LDAC Pulse Width Low
tLDPW
20
ns
400
ns
LDAC Fall to SCLK Fall to Hold
Maxim Integrated
tLDH
Applies to execution edge
7
MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I2C Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI , TA = -40NC to +125NC, unless otherwise noted.)
(Note 2)
Note 2: Electrical specifications are production tested at TA = +25°C. Specifications over the entire operating temperature range
are guaranteed by design and characterization. Typical specifications are at TA = +25°C.
Note 3: DC Performance is tested without load.
Note 4: Linearity is tested with unloaded outputs to within 20mV of GND and VDD.
Note 5: Gain and offset calculated from measurements made with VREF = VDD at code 30 and 4065 for MAX5805, code 8 and
1016 for MAX5804, and code 2 and 254 for MAX5803.
Note 6: Subject to zero and full-scale error limits and VREF settings.
Note 7: On power-up, the device initiates an internal 200Fs (typ) calibration sequence. All commands issued during this time will
be ignored.
Note 8: Specification is guaranteed by design and characterization.
Note 9: Static logic inputs with VIL = VGND and VIH = VDDIO.
Note 10: An unconnected condition on ADDR is sensed via a resistive pullup and pulldown operation; for proper operation, ADDR
should be tied to VDDIO, GND, or left unconnected with minimal capacitance.
SDA
tLOW
tf
tr
tSU;DAT
tHD;STA
tf
tSP
tBUF
tr
SCL
tHD;STA
tCLPW
S
tHIGH
tHD;DAT
CLR
t SU ;STO
tSU;STA
Sr
P
tLDH
S
tLDPW
tCLRSTA
LDAC
Figure 1. I2C Serial Interface Timing Diagram
Maxim Integrated
8
MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I2C Interface
Typical Operating Characteristics
(MAX5805, 12-bit performance, TA = +25NC, unless otherwise noted.)
INL vs. CODE
0.6
0.1
-0.2
DNL (LSB)
0.2
0.2
INL (LSB)
0.4
0
-0.2
-0.4
-0.2
-0.6
-0.6
-0.3
-0.8
-0.8
-0.4
-1.0
-1.0
512 1024 1536 2048 2560 3072 3584 4096
0
DNL vs. CODE
VDD = VREF
0.8
0.6
MAX INL
0.6
0.2
0
-0.2
0
-0.2
-0.4
-0.3
-0.6
-0.6
-0.4
-0.8
-0.8
-0.5
-0.4
MIN INL
-1.0
3.1
3.5
3.9
4.3
4.7
5.1
-40 -25 -10 5 20 35 50 65 80 95 110 125
5.5
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
OFFSET AND ZERO-SCALE ERROR
vs. SUPPLY VOLTAGE
OFFSET AND ZERO-SCALE ERROR
vs. TEMPERATURE
FULL-SCALE ERROR AND GAIN ERROR
vs. SUPPLY VOLTAGE
ERROR (mV)
OFFSET ERROR
0.20
0.15
ZERO-SCALE ERROR
0
OFFSET ERROR (VDD = 3V)
OFFSET ERROR (VDD = 5V)
-0.4
0.10
-1.0
3.1
3.5
3.9
4.3
4.7
SUPPLY VOLTAGE (V)
Maxim Integrated
5.1
5.5
FULL-SCALE ERROR
-0.05
-0.06
GAIN ERROR
-0.07
VREF = 2.5V (EXTERNAL)
NO LOAD
-0.09
-0.8
0
-0.04
-0.08
-0.6
0.05
-0.03
ZERO-SCALE ERROR
0.2
-0.2
-0.02
MAX5803 toc09
0.6
0.4
0.25
VREF = 2.5V (EXTERNAL)
NO LOAD
ERROR (%fs)
0.8
MAX5803 toc08
1.0
0.30
2.7
MIN INL
CODE (LSB)
VREF = 2.5V (EXTERNAL)
NO LOAD
0.35
MIN DNL
-1.0
2.7
MAX5803 toc07
0.40
512 1024 1536 2048 2560 3072 3584 4096
MAX DNL
0.2
-0.2
MIN DNL
MAX INL
0.4
ERROR (LSB)
ERROR (LSB)
0
-0.1
VDD = VREF = 3V
0.8
MAX DNL
0.4
0.1
INL AND DNL vs. TEMPERATURE
1.0
MAX5803 toc05
MAX5803 toc04
1.0
0.2
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
INL AND DNL vs. SUPPLY VOLTAGE
VDD = VREF = 5V
NO LOAD
0.3
0
CODE (LSB)
0.5
0.4
-0.5
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
DNL (LSB)
0
-0.1
-0.4
0
ERROR (mV)
0.3
0.2
0
VDD = VREF = 3V
NO LOAD
0.4
0.4
MAX5803 toc03
VDD = VREF = 5V
NO LOAD
0.8
0.5
MAX5803 toc02
0.6
INL (LSB)
MAX5803 toc01
VDD = VREF = 3V
NO LOAD
0.8
DNL vs. CODE
1.0
MAX5803 toc06
INL vs. CODE
1.0
-0.10
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
SUPPLY VOLTAGE (V)
9
MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I2C Interface
Typical Operating Characteristics (continued)
(MAX5805, 12-bit performance, TA = +25NC, unless otherwise noted.)
0.06
GAIN ERROR (VDD = 3V)
0.04
260
VREF = 2.048V,
VDD = 3V
VREF = 2.5V, VDD = 3V
220
180
0.02
140
0
100
DAC ON
REFERENCE PAD DRIVEN
250
200
DAC OFF
REFERENCE
OUTPUT ONLY
150
100
VREF = VDD = 5V
DAC ON
REFERENCE PAD
UNDRIVEN
VDD = VDDIO
VDAC = FULL SCALE
NO LOAD
50
VREF = VDD = 3V
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(2.500V INTERNAL REFERENCE)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(4.096V INTERNAL REFERENCE)
POWER-DOWN MODE SUPPLY
CURRENT vs. SUPPLY VOLTAGE
DAC ON
REFERENCE PAD UNDRIVEN
150
DAC ON EXT REFERENCE = 2.5V
100
VDD = VDDIO
VDAC = FULL SCALE
NO LOAD
50
DAC OFF
REFERENCE
OUTPUT ONLY
0
2.7
3.1
3.5
3.9
4.3
4.7
5.1
300
250
DAC OFF
REFERENCE
OUTPUT ONLY
200
150
100
VDD = VDDIO
VDAC = FULL SCALE
NO LOAD
50
0
5.5
DAC ON
REFERENCE PAD
UNDRIVEN
4.00
4.25
4.50
4.75
5.25
150
VDD = VREF(EXT) = 5V
VDD = VREF(EXT) = 3V
NO LOAD, TA = +25°C
0
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
Maxim Integrated
VDD = VREF
(EXTERNAL, ACTIVE)
0.7
5.5
0.6
TA = +85°C
0.5
0.4
TA = +125°C
0.3
0.2
TA = +25°C
0.1
5.50
2.7
3.1
3.5
60
MAX5803 toc16
200
50
5.1
TA = -40°C
3.9
4.3
4.7
5.1
5.5
IREF (EXTERNAL) vs. CODE
250
100
4.7
SUPPLY VOLTAGE (V)
VDD = VREF
NO LOAD
55
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
VDD = 5V,
VDD = 5V,
VDD = 5V, VREF(INT) = 2.048V V
REF(INT) = 2.5V
VREF(INT) = 4.096V
4.3
0
5.00
SUPPLY CURRENT vs. CODE
(FOR INTERNAL REF, PIN IS UNDRIVEN)
350
3.9
0.8
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
300
3.5
MAX5803 toc15
350
3.1
MAX5803 toc17
200
DAC ON
REFERENCE PAD DRIVEN
2.7
POWER-DOWN SUPPLY CURRENT (µA)
250
400
SUPPLY CURRENT (µA)
DAC ON REFERENCE PAD DRIVEN
MAX5803 toc14
-40 -25 -10 5 20 35 50 65 80 95 110 125
300
SUPPLY CURRENT (µA)
300
VREF = 4.096V,
VDD = 5V
SUPPLY CURRENT (µA)
0.08
300
MAX5803 toc11
GAIN ERROR (VDD = 5V)
FULL-SCALE ERROR
VDD = VDDIO
VDAC_ = FULL SCALE
DAC ENABLED
NO LOAD
340
MAX5803 toc13
ERROR (%fsr)
0.10
380
SUPPLY CURRENT (µA)
VREF = 2.5V (EXTERNAL)
NO LOAD
MAX5803 toc10
0.12
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(2.048V INTERNAL REFERENCE)
SUPPLY CURRENT vs. TEMPERATURE
(PIN UNDRIVEN FOR INTERNAL REF MODES)
MAX5803 toc12
FULL-SCALE ERROR AND GAIN ERROR
vs. TEMPERATURE
50
45
VREF = 5V
40
35
VREF = 3V
30
25
20
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
10
MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I2C Interface
Typical Operating Characteristics (continued)
(MAX5805, 12-bit performance, TA = +25NC, unless otherwise noted.)
SETTLING TO ±1 LSB
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
SETTLING TO ±1 LSB
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
MAX5803 toc18
5.9µs
MAX5803 toc19
ZOOMED
VOUT
1 LSB/div
VOUT
2V/div
ZOOMED
VOUT
1 LSB/div
VOUT
2V/div
3/4 SCALE TO 1/4 SCALE
1/4 SCALE TO 3/4
SCALE
TRIGGER
PULSE
10V/div
6.3µs
TRIGGER
PULSE
10V/div
2µs/div
2µs/div
MAJOR CODE TRANSITION GLITCH ENERGY
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
MAJOR CODE TRANSITION GLITCH ENERGY
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
MAX5803 toc20
MAX5803 toc21
1 LSB CHANGE
(MIDCODE TRANSITION
0x800 TO 0x7FF)
GILTCH IMPULSE = 5nV*S
ZOOMED
VOUT
1.25mV/div
ZOOMED
VOUT
1.25mV/div
TRIGGER
PULSE
5V/div
TRIGGER
PULSE
5V/div
2µs/div
1 LSB CHANGE
(MIDCODE TRANSITION
0x7FF TO 0x800)
GILTCH IMPULSE = 5nV*S
2µs/div
VOUT vs. TIME TRANSIENT
EXITING POWER-DOWN
POWER-ON RESET TO 0V
MAX5803 toc22
MAX5803 toc23
VCLK
5V/div
0V
VDD = VREF = 5V
10kI LOAD TO VDD
36TH EDGE
VDD
2V/div
0V
VOUT
1V/div
VDD = 5V, VREF = 2.5V
EXTERNAL
20µs/div
Maxim Integrated
VOUT
2V/div
0V
0V
40µs/div
11
MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I2C Interface
Typical Operating Characteristics (continued)
(MAX5805, 12-bit performance, TA = +25NC, unless otherwise noted.)
DIGITAL FEEDTHROUGH
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
3
VDD = VREF = 5V
DAC AT MIDSCALE
VDD = VREF
MIDSCALE
2
1
∆VOUT (mV)
VOUT
125µV/div
MAX5803 toc25
OUTPUT LOAD REGULATION
MAX5803 toc24
VDD = 3V
0
DIGITAL FEEDTHROUGH = 0.1nV*s
VDD = 5V
-1
-2
-3
-30
1µs/div
-20
-10
0
10
20
30
40
IOUT (mA)
HEADROOM AT RAILS
vs. OUTPUT CURRENT (VDD = VREF)
VDD = 5V
4.5
200
3.5
100
3.0
0
-100
VDD = 3V
-200
2.5
1.5
1.0
-400
0.5
-500
0
0
10
20
VDD = 3V, SOURCING
FULL SCALE
2.0
-300
-40 -30 -20 -10
VDD = 5V, SOURCING
FULL SCALE
4.0
VOUT (V)
∆VOUT (mV)
300
5.0
30
40
50
VDD = 3V AND 5V SINKING
ZERO SCALE
0
1
2
3
4
5
6
7
8
9
VDD = 5V, VREF = 4.096V
(INTERNAL)
300
VDD = 5V, VREF = 2.5V
(INTERNAL)
250
200
VDD = 5V, VREF = 2.048V
(INTERNAL)
150
100
50
VDD = 5V, VREF = 5V
(EXTERNAL)
0
1k
100
IOUT (mA)
IOUT (mA)
100k
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (VDD = 5V, VREF = 2.048V)
MAX5803 toc29
MAX5803 toc30
MIDSCALE UNLOADED
VP-P = 10µV
VOUT
5µV/div
10k
FREQUENCY (Hz)
0.1Hz TO 10Hz OUTPUT NOISE, EXTERNAL
REFERENCE (VDD = 5V, VREF = 4.5V)
MIDSCALE UNLOADED
VP-P = 11µV
VOUT
5µV/div
4s/div
Maxim Integrated
10
350
MAX5803 toc28
VDD = VREF
MIDSCALE
NOISE-VOLTAGE DENSITY (nV/√(Hz))
400
MAX5803 toc26
500
NOISE-VOLTAGE DENSITY
vs. FREQUENCY (DAC AT MIDSCALE)
MAX5803 toc27
OUTPUT CURRENT LIMITING
4s/div
12
MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I2C Interface
Typical Operating Characteristics (continued)
(MAX5805, 12-bit performance, TA = +25NC, unless otherwise noted.)
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (VDD = 5V, VREF = 2.500V)
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (VDD = 5V, VREF = 4.096V)
MAX5803 toc31
MAX5803 toc32
MIDSCALE UNLOADED
VP-P = 12µV
MIDSCALE UNLOADED
VP-P = 13µV
VOUT
5µV/div
VOUT
5µV/div
4s/div
4s/div
VREF DRIFT vs. TEMPERATURE
35
∆VREF (mV)
-0.10
25
20
15
-0.15
-0.20
10
0
-0.30
200
400
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
2000
MAX5803 toc35
VREF = 2.5V
250
200
150
100
VDD = 5V
1800
ALL I/O PINS SWEPT
1600
SUPPLY CURRENT (µA)
350
1400
VREF = 2.048V
VDDIO = 5V
1000
800
VDDIO = 3V
600
VDDIO = 1.8V
200
0
500
1200
400
50
300
INTERNAL REFERENCE NOISE
DENSITY vs. FREQUENCY
VREF = 4.096V
300
100
REFERENCE OUTPUT CURRENT (µA)
450
400
0
TEMPERATURE COEFFICIENT (ppm/°C)
MAX5803 toc36
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
NOISE-VOLTAGE DENSITY (nV/√(Hz))
VREF = 2.048V, 2.5V, 4.096V
-0.25
5
0
100
1k
10k
FREQUENCY (Hz)
Maxim Integrated
VDD = 5V
INTERNAL REFERENCE
-0.05
30
MAX5803 toc34
VDD = 2.7V
VREF = 2.5V
BOX METHOD
40
DEVICE COUNT
REFERENCE LOAD REGULATION
0
MAX5803 toc33
45
100k
0
1
2
3
4
5
INPUT LOGIC VOLTAGE (V)
13
MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I2C Interface
Pin Configurations
TOP VIEW
1
LDAC
2
ADDR
3
SCL
4
SDA
5
10 REF
+
AUX
MAX5803
MAX5804
MAX5805
*EP
AUX
1
2
+
10
REF
9
OUT
8
GND
9
OUT
LDAC
8
GND
ADDR
3
7
VDD
SCL
4
7
VDD
6
VDDIO
SDA
5
6
VDDIO
TDFN
MAX5803
MAX5804
MAX5805
µMAX
*CONNECTED TO GND
Pin Description
PIN
NAME
1
AUX
FUNCTION
Active-Low Auxilliary Asynchronous Input. User Configurable, see Table 7.
2
LDAC
Dedicated Active-Low Asynchronous Load DAC
3
ADDR
I2C Interface Address Selection
4
SCL
I2C Interface Clock Input
5
SDA
I2C Bidirectional Serial Data
6
VDDIO
Digital Interface Power-Supply Input
7
VDD
Supply Voltage Input. Bypass VDD with a 0.1FF capacitor to GND.
8
GND
Ground
9
OUT
Buffered DAC Output
10
REF
Reference Voltage Input/Output
—
EP
Maxim Integrated
Exposed Pad (TDFN Only). Connect to ground.
14
MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I2C Interface
Detailed Description
The MAX5803/MAX5804/MAX5805 are single-channel,
low-power, 8-/10-/12-bit voltage-output digital-to-analog
converters (DACs) with an internal output buffer. The
wide supply voltage range of 2.7V to 5.5V and low
power consumption accommodate low-power and lowvoltage applications. The devices present a 100kI
(typ) load to the external reference. The internal output
buffer allows rail-to-rail operation. An internal voltage
reference is available with software selectable options
of 2.048V, 2.500V, or 4.096V. The devices feature a
fast 400kHz I2C-compatible interface. The MAX5803/
MAX5804/MAX5805 include a serial-in/parallel-out shift
register, internal CODE and DAC registers, a power-onreset (POR) circuit to initialize the DAC output to code
zero, and control logic. A user-configurable AUX pin
is available to asynchronously clear or gate the device
output independent of the serial interface.
DAC Output (OUT)
The MAX5803/MAX5804/MAX5805 include an internal
buffer on the DAC output. The internal output buffer
provides improved load regulation for the DAC output.
The output buffer slews at 1V/Fs (typ) and drives up to
2kI in parallel with 500pF. The analog supply voltage
(VDD) determines the maximum output voltage range
of the devices as VDD powers the output buffer. Under
no-load conditions, the output buffer drives from GND to
VDD, subject to offset and gain errors. With a 2kI load
to GND, the output buffer drives from GND to within and
200mV of VDD. With a 2kI load to VDD, the output buffer
drives from VDD to within 200mV of GND.
The DAC ideal output voltage is defined by:
D
V=
OUT V REF × N
2
Where D = code loaded into the DAC register, VREF =
reference voltage, N = resolution.
Internal Register Structure
The user interface is separated from the DAC logic to
minimize digital feedthrough. Within the serial interface
is an input shift register, the contents of which can
be routed to control registers or the DAC itself, as
determined by the user command.
Within the device there is a CODE register followed by
a DAC Latch register (see the Functional Diagram).
Maxim Integrated
The contents of the CODE register hold pending DAC
output settings which can later be loaded into the DAC
registers. The CODE register can be updated using both
CODE and CODE_LOAD user commands. The contents
of the DAC register hold the current DAC output settings.
The DAC register can be updated directly from the serial
interface using the CODE_LOAD commands or can
upload the current contents of the CODE register using
LOAD commands or the LDAC input.
The contents of both CODE and DAC registers are
maintained during all software power-down states, so that
when the DAC is returned to a normal operating mode, it
returns to its previously stored output settings. Any CODE
or LOAD commands issued during software power-down
states continue to update the register contents. The
SW_CLEAR command clears the contents of the CODE
and DAC registers to the user-programmable default
values. The SW_RESET command resets all configuration
registers to their power-on default states, while resetting
the CODE and DAC registers to zero scale.
Internal Reference
The MAX5803/MAX5804/MAX5805 include an internal
precision voltage reference that is software selectable to
be 2.048V, 2.500V, or 4.096V. When an internal reference
is selected, that voltage is available on the REF pin
for other external circuitry (see the Typical Operating
Circuits) and can drive a 25kI load.
External Reference
The external reference input features a typical input
impedance of 100kI and accepts an input voltage
from +1.24V to VDD. Connect an external voltage
supply between REF and GND to apply an external
reference. The MAX5803/4/5 power up and reset to
external reference mode. Visit www.maximintegrated.
com/products/references for a list of available external
voltage-reference devices.
AUX Input
The MAX5803/MAX5804/MAX5805 provide an asynchronous AUX (active-low) input. Use the CONFIG command
to program the device to use the input in one of the following modes: CLR (default), GATE, or disabled.
CLR Mode
In CLR mode, the AUX input performs an asynchronous
level sensitive CLEAR operation when pulled low. If
CLR is configured and asserted, all CODE and DAC
15
MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I2C Interface
data registers are cleared to their default/return values
as defined by the configuration settings. Other userconfiguration settings are not affected.
MAX5804/MAX5805 DAC output updates in response to
each completed I/O CODE instruction update edge. A
software LOAD command is also provided.
Some I2C interface commands are gated by CLR activity
during the transfer sequence. If CLR is issued during a
command write sequence, any gated commands within
the sequence are ignored. If CLR is issued during an
I2C command read sequence, the exchange continues
as normal, however the data read back may be stale.
The user may determine the state of the CLR input by
issuing a status read. In all cases, the I2C interface
continues to function according to protocol, however
slave ACK pulses beyond the command acknowledge
are not sent for gated write commands (notifying the
FP that these instructions are being ignored). Any nongated commands appearing in the transfer sequence
are fully acknowledged and executed. In order for the
gating condition to be removed, remove CLR prior
to a recognized START condition, meeting tCLRSTA
requirements.
The LDAC operation does not interact with the user
interface directly. However, in order to achieve the best
possible glitch performance, timing with respect to the
interface update edge should follow tLDH specifications
when issuing CODE commands. Using the software
LOAD command with the Broadcast ID provides a
software-based means of synchronously updating several
MAX5803/MAX5804/MAX5805 devices on a shared bus.
GATE Mode
Use of the GATE mode provides a means of momentarily
holding the DAC in a user-selectable default/return state,
returning the DAC to the last programmed state upon
removal. The MAX5803/MAX5804/MAX5805 also feature
a software-accessible GATE command. While asserted
in GATE mode, the AUX pin does not interfere with
RETURN, CODE, or DAC register updates and related
load activity. The user may determine the gate status of
the device by issuing a status read. I2C readbacks of
CODE and DAC register content while gated continue to
return the current register values, which may differ from
the actual DAC output level.
LDAC Input
The MAX5803/MAX5804/MAX5805 provide a dedicated
asynchronous LDAC (active-low) input. The LDAC input
performs an asynchronous level sensitive LOAD operation
when pulled low. Use of the LDAC input mode provides
a means of updating multiple devices together as a
group. Users wishing to control the DAC update instance
independently of the I/O instruction should hold LDAC
high during programming cycles. Once programming
is complete, LDAC may be strobed and the new CODE
register content is loaded into the DAC latch output.
Users wishing to load new DAC data in direct response
to I/O CODE register activity should connect LDAC
permanently low; in this configuration, the MAX5803/
Maxim Integrated
VDDIO Input
The MAX5803/MAX5804/MAX5805 feature a separate
supply pin (VDDIO) for the digital interface (1.8V to 5.5V).
If present, connect VDDIO to the I/O supply of the host
processor.
I2C Serial Interface
The MAX5803/MAX5804/MAX5805 feature an I2C-/
SMBusK-compatible, 2-wire serial interface consisting of
a serial data line (SDA) and a serial clock line (SCL). SDA
and SCL enable communication between the MAX5803/
MAX5804/MAX5805 and the master at clock rates up
to 400kHz. Figure 1 shows the 2-wire interface timing
diagram. The master generates SCL and initiates data
transfer on the bus. The master device writes data to the
MAX5803/MAX5804/MAX5805 by transmitting the proper
slave address followed by the command byte and then
the data word. Each transmit sequence is framed by a
START (S) or Repeated START (Sr) condition and a STOP
(P) condition. Each word transmitted to the MAX5803/
MAX5804/MAX5805 is 8 bits long and is followed by an
acknowledge clock pulse.
A master reading data from the MAX5803/MAX5804/
MAX5805 must transmit the proper slave address
followed by a series of nine SCL pulses for each byte
of data requested. The MAX5803/MAX5804/MAX5805
transmit data on SDA in sync with the master-generated
SCL pulses. The master acknowledges receipt of each
byte of data. Each read sequence is framed by a START
or Repeated START condition, a not acknowledge, and
a STOP condition. SDA operates as both an input and
an open-drain output. A pullup resistor, typically 4.7kI is
required on SDA. SCL operates only as an input. A pullup
resistor, typically 4.7kI, is required on SCL if there are
multiple masters on the bus, or if the single master has
an open-drain SCL output.
16
MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I2C Interface
Series resistors in line with SDA and SCL are optional.
Series resistors protect the digital inputs of the MAX5803/
MAX5804/MAX5805 from high voltage spikes on the
bus lines and minimize crosstalk and undershoot of
the bus signals. The MAX5803/MAX5804/MAX5805 can
accommodate bus voltages higher than VDD up to
a limit of 5.5V; bus voltages lower than VDD are not
recommended and may result in significantly increased
interface currents. The MAX5803/MAX5804/MAX5805
digital inputs are double buffered. Depending on the
command issued through the serial interface, the CODE
register(s) can be loaded without affecting the DAC
register(s) using the write command. To update the DAC
registers, either drive the AUX input low while in LDAC
mode to asynchronously update the DAC output, or use
the software LOAD command.
I2C START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START
condition. A START condition is a high-to-low transition
on SDA with SCL high. A STOP condition is a low-tohigh transition on SDA while SCL is high (Figure 2). A
START condition from the master signals the beginning
of a transmission to the MAX5803/MAX5804/MAX5805.
The master terminates transmission and frees the bus
by issuing a STOP condition. The bus remains active if
a Repeated START condition is generated instead of a
STOP condition.
I2C Early STOP and Repeated START
Conditions
The MAX5803/MAX5804/MAX5805 recognize a STOP
condition at any point during data transmission except
if the STOP condition occurs in the same high pulse
as a START condition. Transmissions ending in an
early STOP condition do not impact the internal device
settings. If STOP occurs during a readback byte, the
transmission is terminated and a later read mode request
begins transfer of the requested register data from the
beginning (this applies to combined format I2C read
mode transfers only, interface verification mode transfers
will be corrupted, see Figure 2.)
I2C Slave Address
The slave address is defined as the seven most significant
bits (MSBs) followed by the R/W bit. See Figure 4. The
five most significant bits are 00110 with the 2 LSBs
determined by ADDR as shown in Table 1. Setting the
R/W bit to 1 configures the MAX5803/MAX5804/MAX5805
for read mode. Setting the R/W bit to 0 configures
the MAX5803/MAX5804/MAX5805 for write mode. The
slave address is the first byte of information sent to the
MAX5803/MAX5804/MAX5805 after the START condition.
The MAX5803/MAX5804/MAX5805 have the ability to
detect an unconnected state on the ADDR input for
additional address flexibility; if leaving the ADDR input
unconnected, be certain to minimize all loading on the
pin (i.e. provide a landing for the pin, but do not allow any
board traces). Using the ADDR input, up to three devices
can be run on a single I2C bus
S
Sr
P
SCL
SDA
VALID START, REPEATED START, AND STOP PULSES
P
S
S
P
P
S
P
Table 1. I2C Slave Address LSBs
A[6:2] = 00110
ADDR
A1
A0
VDD
1
1
N.C.
1
0
GND
0
0
Maxim Integrated
INVALID START/STOP PULSE PAIRINGS - ALL WILL BE RECOGNIZED AS STARTS
Figure 2. I2C START, Repeated START, and STOP Conditions
17
MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I2C Interface
I2C Broadcast Address
A broadcast address is provided for the purpose of
updating or configuring all MAX5803/MAX5804/MAX5805
devices on a given I2C bus. All MAX5803/MAX5804/
MAX5805 devices acknowledge and respond to the
broadcast device address 00110010. The broadcast
mode is intended for use in write mode only (as indicated
by R/W = 0 in the address given).
I2C Acknowledge
In write mode, the acknowledge bit (ACK) is a clocked
9th bit that the MAX5803/MAX5804/MAX5805 use to
handshake receipt of each byte of data as shown in
Figure 3. The MAX5803/MAX5804/MAX5805 pull down
SDA during the entire master-generated 9th clock pulse
if the previous byte is successfully received. Monitoring
ACK allows for detection of unsuccessful data transfers.
An unsuccessful data transfer occurs if a receiving
device is busy or if a system fault has occurred. In the
event of an unsuccessful data transfer, the bus master
will retry communication.
In read mode, the master pulls down SDA during the
9th clock cycle to acknowledge receipt of data from the
MAX5803/MAX5804/MAX5805. An acknowledge is sent
by the master after each read byte to allow data transfer
to continue. A not-acknowledge is sent when the master
reads the final byte of data from the MAX5803/MAX5804/
MAX5805, followed by a STOP condition.
I2C Command Byte and Data Bytes
A command byte follows the slave address. A command
byte is typically followed by two data bytes unless it
is the last byte in the transmission. If data bytes follow
the command byte, the command byte indicates the
address of the register that is to receive the following
two data bytes. The data bytes are stored in a temporary
CLOCK PULSE
FOR
ACKNOWLEDGMENT
START
CONDITION
SCL
1
2
9
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
register and then transferred to the appropriate register
during the ACK periods between bytes. This avoids any
glitching or digital feedthrough to the DAC while the
interface is active.
I2C Write Operations
A master device communicates with the MAX5803/
MAX5804/MAX5805 by transmitting the proper slave
address followed by command and data words. Each
transmit sequence is framed by a START or Repeated
START condition and a STOP condition as described
above. Each word is 8 bits long and is always followed
by an acknowledge clock (ACK) pulse as shown in
Figure 4 and Figure 5. The first byte contains the address
of the MAX5803/MAX5804/MAX5805 with R/W = 0 to
indicate a write. The second byte contains the register
(or command) to be written and the third and fourth bytes
contain the data to be written. By repeating the register
address plus data pairs (Byte #2 through Byte #4 in
Figure 4 and Figure 5), the user can perform multiple
register writes using a single I2C command sequence.
There is no limit as to how many registers the user can
write with a single command. The MAX5803/MAX5804/
MAX5805 support this capability for all user-accessible
write mode commands.
Combined Format I2C Readback Operations
Each readback sequence is framed by a START or
Repeated START condition and a STOP condition. Each
word is 8 bits long and is followed by an acknowledge
clock pulse as shown in Figure 6. The first byte contains
the address of the MAX5803/MAX5804/MAX5805 with
R/W = 0 to indicate a write. The second byte contains
the register that is to be read back. There is a Repeated
START condition, followed by the device address with
R/W = 1 to indicate a read and an acknowledge clock.
The master has control of the SCL line but the MAX5803/
MAX5804/MAX5805 take over the SDA line. The final two
bytes in the frame contain the register data readback
followed by a STOP condition. If additional bytes beyond
those required to readback the requested data are
provided, the MAX5803/MAX5804/MAX5805 will continue
to readback ones. Readback of the RETURN register
is supported for the RETURN command (B[23:20] =
0111). Readback of the CODE register is supported for
the CODE command (B[23:20] = 1000). Readback of
the DAC register is supported for all LOAD commands
(B[23:20] = 1001, 1010, or 1011).
Figure 3. I2C Acknowledge
Maxim Integrated
18
MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I2C Interface
Interface Verification I2C Readback
Operations
Readback of all other registers is not directly supported.
All requests to read unsupported registers read back
the device’s current status and configuration settings as
shown in Table 2. The status register contains information
on the current clear, gate, and load status of the device
(with a one indicating an asserted status), as well as user
configuration settings for the reference, power-down,
AUX mode, and default operation.
WRITE COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS
While the MAX5803/MAX5804/MAX5805 support
standard I2C readback of selected registers, it is also
capable of functioning in an interface verification mode.
This mode is accessed any time a readback operation
follows an executed write mode command. In this mode,
the last executed three-byte command is read back in its
entirety. This behavior allows verification of the interface.
WRITE DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
WRITE DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
START
STOP
0 0 1 1 0 A1 A0 W A 23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9 8 A 7 6 5 4 3 2 1 0 A
SDA
SCL
COMMAND EXECUTED
A
ACK. GENERATED BY MAX5803/MAX5804/MAX5805
Figure 4. I2C Single Register Write Sequence
START
SDA
SCL
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS
0 0 1 1
WRITE COMMAND1
BYTE #2: COMMAND1 BYTE
(B[23:16])
WRITE DATA1
BYTE #3: DATA1 HIGH BYTE
(B[15:8])
0 A1 A0 W A 23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9
WRITE DATA1
BYTE #4: DATA1 LOW BYTE
(B[7:0])
8 A 7 6 5 4 3 2 1 0 A
COMMAND1
EXECUTED
ADDITIONAL COMMAND AND
DATA PAIRS (3 BYTE BLOCKS)
BYTE #5: COMMANDn BYTE
(B[23:16])
BYTE #6: DATAn HIGH BYTE
(B[15:8])
BYTE #7: DATAn LOW BYTE
(B[7:0])
STOP
23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9 8 A 7 6 5 4 3 2 1 0 A
A
ACK. GENERATED BY MAX5803/MAX5804/MAX5805
COMMANDn
EXECUTED
Figure 5. Multiple Register Write Sequence (Standard I2C Protocol)
Maxim Integrated
19
MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I2C Interface
Sample command sequences are shown in Figure 7. The
first command transfer is given in write mode with R/W =
0 and must be run to completion to qualify for interface
verification readback. There is now a STOP/START pair
or Repeated START condition required, followed by the
readback transfer with R/W = 1 to indicate a read and
an acknowledge clock from the MAX5803/MAX5804/
MAX5805. The master still has control of the SCL line but
the MAX5803/MAX5804/MAX5805 take over the SDA line.
The final three bytes in the frame contain the command
and register data written in the first transfer presented
for readback, followed by a STOP condition. If additional
bytes beyond those required to read back the requested
WRITE ADDRESS
BYTE #1: I2C SLAVE
ADDRESS
START
SDA
SCL
WRITE COMMAND1
BYTE #2: COMMAND1
BYTE
data are provided, the MAX5803/MAX5804/MAX5805 will
continue to read back ones.
It is not necessary for the write and read mode transfers
to occur immediately in sequence. I2C transfers involving
other devices do not impact the MAX5803/MAX5804/
MAX5805 readback mode. Toggling between readback
modes is based on the length of the preceding write
mode transfer. Combined format I2C readback operation
is resumed if a write command greater than two bytes
but less than four bytes is supplied. For commands writ­
ten using multiple register write sequences, only the last
command executed is read back. For each command
written, the readback sequence can only be completed
READ ADDRESS
REPEATED BYTE #3: I2C SLAVE
START
ADDRESS
READ DATA
BYTE #4: DATA1 HIGH
BYTE (B[15:8])
READ DATA
BYTE #5: DATA1
LOWBYTE (B[7:0])
STOP
0 0 1 1 0 A1 A0 R A D D D D D D D D A D D D D D D D D ~A
0 0 1 1 0 A1 A0 W A N N N N N N N N A
A ACK. GENERATED BY I2C MASTER
A ACK. GENERATED BY MAX5803/MAX5804/MAX5805
Figure 6. Standard I2C Register Read Sequence
Table 2. Standard I2C User Readback Data
COMMAND BYTE (REQUEST)
READBACK DATA HIGH BYTE
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
0
0
0
0
X
X
X
X
0
1
0
1
0
READBACK DATA LOW BYTE
B8
B7
B6
B5
B4
B3
B2
B1
B0
PART_ID[7:0]
MAX5803 = 0x8A
MAX5804 = 0x92
MAX5805 = 0x82
REV_ID[2:0]
(000)
0
1
1
1
X
X
X
X
RETURN[11:4]
RETURN[3:0]
0
0
0
0
1
0
0
0
X
X
X
X
CODE[11:4]
CODE[3:0]
0
0
0
0
1
0
0
1
X
X
X
X
DAC[11:4]
DAC[3:0]
0
0
0
0
1
0
X
X
X
X
DAC[11:4]
DAC[3:0]
0
0
0
0
1
1
X
X
X
X
DAC[11:4]
DAC[3:0]
0
0
0
0
Any other command
CLR
GATE
0
0
LOAD
1
1
1
RF[3:0]
PD[1:0]
AB[2:0]
DF[2:0]
Table 3. DAC Data Bit Positions
PART
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
MAX5803
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
MAX5804
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
MAX5805
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
Maxim Integrated
20
MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I2C Interface
one time; partial and/or multiple attempts to readback
executed in succession will not yield usable data.
I2C Compatibility
The MAX5803/MAX5804/MAX5805 are fully compatible
with existing I2C systems. SCL and SDA are highimpedance inputs; SDA provides an open drain which
pulls the data line low to transmit data or ACK pulses.
Figure 8 shows a typical I2C application.
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS
START
0
SDA
0 1
WRITE COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
I2C User-Command Register Map
This section lists the user-accessible commands and
registers for the MAX5803/MAX5804/MAX5805.
Table 4 provides detailed information about the I2C
Command Registers.
WRITE DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
0 A1 A0 W A 23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9
1
WRITE DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
8 A 7
6
5
4
3
2
1
STOP
0
A
SCL
POINTER UPDATED
(QUALIFIES FOR COMBINED READ BACK)
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS
START
0
0 1
1
0
SDA
0
1
READ DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
0 A1 A0 R A 23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS
START
READ COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
COMMAND EXECUTED
(QUALIFIES FOR INTERFACE READ BACK)
1
WRITE COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
READ DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
8 A 7
WRITE DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
0 A1 A0 W A 23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9
6
5
4
3
2
1
STOP
0
~A
WRITE DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
8 A 7
6
5
4
3
2
1
REPEATED
START
0
A
SCL
POINTER UPDATED
(QUALIFIES FOR COMBINED READ BACK)
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS
0
0
1
1
A
READ COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
COMMAND EXECUTED
(QUALIFIES FOR INTERFACE READ BACK)
READ DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
0 A1 A0 R A 23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9
ACK. GENERATED BY MAX5803 /MAX5804/MAX5805
A
READ DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
8 A 7
6
5
4
3
2
1
STOP
0
~A
ACK. GENERATED BY I2C MASTER
Figure 7. Interface Verification I2C Register Read Sequences
Maxim Integrated
21
MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I2C Interface
CODE Command
The CODE command (B[23:20] = 1000) updates the
CODE register content for the DAC. Changes to the
CODE register content based on this command will not
affect the DAC output directly unless the LDAC input
is in a low state. Otherwise, a subsequent hardware
or software LOAD operation will be required to move
this content to the active DAC latch. This command is
gated when CLR is asserted, updates to this register are
ignored while the register is being cleared. See Table
3 and Table 4.
µC
SDA
MAX5803
MAX5804
MAX5805
SCL
SCL
SDA
ADDR
LOAD Command
The LOAD command (B[23:20] = 1001) updates the DAC
latch register content by uploading the current contents
of the CODE register. This command is gated when CLR
is asserted, updates to this register are ignored while the
register is being cleared. See Table 3 and Table 4.
CODE_LOAD Command
The CODE_LOAD command (B[23:20] = 1010 and 1011)
updates the CODE register contents as well as the DAC
register content of the DAC. This command is gated
when CLR is asserted, updates to these registers are
ignored while the register is being cleared. See Table 3
Maxim Integrated
MAX5803
MAX5804
MAX5805
+5V
SCL
SDA
ADDR
Figure 8. Typical I2C Application Circuit
22
B23
1
1
1
1
0
CODE
LOAD
CODE_LOAD
CODE_LOAD
RETURN
DAC COMMANDS
COMMAND
Maxim Integrated
1
0
0
0
0
B22
1
1
1
0
0
B21
1
1
0
1
0
B20
X
X
X
X
X
B19
X
X
X
X
X
B18
X
X
X
X
X
B17
X
X
X
X
X
B16
Table 4. I2C Commands Summary
X
B15
X
X
X
B8
X
B7
B6
B5
REGISTER DATA[3:0]
DATA[11:4]
DATA[3:0]
RETURN REGISTER
CODE AND DAC
X
CODE AND DAC REGISTER
X
REGISTER DATA[3:0]
X
DATA[11:4]
X
B4
CODE AND DAC
X
DATA[3:0]
X
B9
CODE AND DAC REGISTER
X
B10
CODE REGISTER
B11
DATA[11:4]
B12
CODE REGISTER
B13
RETURN REGISTER DATA[11:4]
B14
X
X
X
X
X
B3
X
X
X
X
X
B2
X
X
X
X
X
B1
X
X
X
X
X
B0
contents for the DAC
RETURN register
Updates the
register
while updating DAC
CODE register
writes data to the
Simultaneously
register
while updating DAC
CODE register
writes data to the
Simultaneously
to the DAC register
the CODE registers
Transfers data from
CODE register
Writes data to the
DESCRIPTION
MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I2C Interface
23
COMMAND
B23
B22
Maxim Integrated
0
0
0
0
SOFTWARE
POWER
CONFIG
DEFAULT
1
1
1
0
0
1
0
1
0
1
0
1
0
0
1
1
B21
1
0
0
1
0
1
0
B20
X
X
X
X
X
X
B16
Type:
11 = 4.1V
10 = 2.0V
01 = 2.5V
00 = EXT
Ref Mode
B17
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Other = No Effect
101 = RST
100 = CLR
001 = GATE
000 = END
B18
B19
0 = No Drive
1 = Drive Pin
X
X
X
X
X
X
X
B15
X
X
X
X
X
X
X
B14
X
X
X
X
X
X
X
B13
X
X
X
X
X
X
X
B12
X
X
X
X
X
X
X
B11
X
X
X
X
X
X
X
B10
Reserved Commands: Any commands not specifically listed above are reserved for Maxim internal use only.
No Operation
NO OPERATION COMMANDS
0
REF
CONFIGURATION COMMANDS
0 = Default
1 = Always ON
Table 4. I2C Commands Summary (continued)
X
X
X
X
X
X
X
B9
X
X
X
X
X
X
X
B8
X
X
B6
X
000 = POR
X
X
X
X
X
X
Other = No Effect
100 = RETURN
011 = FULL
010 = MID
001 = ZERO
111 = NONE
110 = CLEAR
011 = GATE
X
X
X
B3
AUX Mode:
X
X
X
B4
X
X
X
X
X
X
Other = No Effect
X
X
X
B5
Default Values:
X
11 = HiZ
10 = 100kI
01 = 1kI
00 = DAC
Mode:
Power
X
X
B7
X
X
X
X
X
X
X
B2
X
X
X
X
X
X
X
B1
X
X
X
X
X
X
X
B0
the part.
will have no effect on
These commands
value for the DAC
Sets the default
of the AUX input
Updates the function
mode
Sets the Power
chosen
operation of the type
Executes a software
operating mode.
Sets the reference
DESCRIPTION
MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I2C Interface
24
MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I2C Interface
REF Command
SOFTWARE Commands
The REF (B[23:20] = 0010) command updates the global
reference setting used for the DAC. Set B[17:16] = 00 to
use an external reference for the DAC or set B[17:16] to
01, 10, or 11 to select either the 2.5V, 2.048V, or 4.096V
internal reference, respectively.
The SOFTWARE (B[23:20] = 0011) commands provide
a means of issuing several flexible software actions. See
Table 6.
If RF3 (B19) is set to zero (default) in the REF command,
the REF I/O will not be driven by the internal reference
circuit, saving current. If RF3 is set to one, the REF I/O
will be driven by the internal reference circuit, consuming
an additional 25FA (typ) of current when the reference is
powered; when the reference is powered down, the REF
I/O will be high-impedance.
END (000):Used to end any active gate operation,
returning to normal operation (default).
The SOFTWARE Command Action Mode is selected by
B[18:16]:
GATE (001):
DAC contents will be gated to their
DEFAULT selected values until the gate
condition is removed.
CLEAR (100):
All CODE and DAC contents will be
cleared to their DEFAULT selected
values.
If RF2 (B18) is set to zero (default) in the REF command,
the reference will be powered down any time the DAC
is powered down (in STANDBY mode). If RF2 (B18) is
set to one, the reference will remain powered even if the
DAC is powered down, allowing continued operation of
external circuitry. In this mode, the 1FA shutdown state is
not available. See Table 5.
RESET (101):
All CODE, DAC, RETURN, and
configuration registers reset to their
power-up defaults (including REF,
POWER, and CONFIG settings),
simulating a power cycle reset.
OTHER:
Table 5. REF (0010) Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10
1
0
RF3 RF2 RF1 RF0
REF COMMAND
0 = Off in Standby
1 = On in Standby
0
0 = REF Not driven
1 = REF Driven
0
DEFAULT VALUES
0
0
X
X
X
Ref Mode:
00 = EXT
01 = 2.5V
10 = 2.0V
11 = 4.0V
0
0
X
X
X
No effect.
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
X
X
X
X
X
X
X
X
X
X
X
X
X
Don’t Care
X
X
COMMAND BYTE
X
X
X
Don’t Care
X
X
X
X
X
DATA HIGH BYTE
X
X
X
DATA LOW BYTE
Table 6. SOFTWARE (0011) Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
0
1
1
X
SOFTWARE
COMMANDS
Don’t Care
0
DEFAULT VALUES
X
SW2 SW1 SW0 X
X
Mode:
000: END
001: GATE
100: CLR
101: RST
Other: No
Effect
0
COMMAND BYTE
Maxim Integrated
X
0
0
X
X
X
X
B8
B7
B6
B5
B4
B3
B2
B1
B0
X
X
X
X
X
X
X
X
X
X
X
X
Don’t Care
X
X
X
X
X
Don’t Care
X
DATA HIGH BYTE
X
X
X
X
X
X
X
DATA LOW BYTE
25
MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I2C Interface
POWER Command
mode, the DAC register retains its value so that the
output is restored when the device powers up. The serial
interface remains active in power-down mode with all
registers accessible.
The MAX5803/MAX5804/MAX5805 feature a softwarecontrolled POWER mode command (B[23:20] = 0100).
In power-down, the DAC output is disconnected from
the buffer and is grounded with either one of the two
selectable internal resistors or set to high impedance.
See Table 7 and Table 8 for the selectable internal
resistor values in power-down mode. In power-down
In power-down mode, the internal reference can be
powered down or it can be set to remain powered-on for
external use. Also, in power-down mode, parts using the
external reference do not load the REF pin. See Table 7.
Table 7. POWER (0100) Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
0
1
0
0
X
POWER
COMMAND
DEFAULT VALUES
X
X
X
X
X
X
Don’t Care
X
X
X
COMMAND BYTE
X
X
X
X
B8
X
X
X
X
X
X
B6
B5
B4
B3
B2
B1
B0
X
X
X
X
X
X
X
X
Power
Mode:
00 =
Normal
01 = 1kI
10 =
100kI
11 = Hi-Z
Don’t Care
X
B7
PD1 PD0
X
X
X
0
0
DATA HIGH BYTE
Don’t Care
X
X
X
X
DATA LOW BYTE
Table 8. Selectable DAC Output Impedance in Power-Down Mode
PD1 (B7)
PD0 (B6)
0
0
Normal operation
0
1
Power-down with internal 1kI pulldown resistor to GND.
1
0
Power-down with internal 100kI pulldown resistor to GND.
1
1
Power-down with high-impedance output.
Maxim Integrated
OPERATING MODE
26
MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I2C Interface
CONFIG Command
The CONFIG command (B[23:20] = 0101) updates
the function of the AUX input enabling its gate or clear
(default) operation mode. See Table 9.
AUX Config settings are written by B[5:3]:
GATE (011): AUX functions as a GATE. DAC code is
gated to DEFAULT value input when pin
is low.
CLEAR (110): AUX functions as a CLR input (default).
CODE and DAC content is cleared to
DEFAULT value if pin is low.
NONE (111):
AUX functions are disabled.
OTHER:
AUX function is not altered.
DEFAULT Command
DEFAULT (0110): The DEFAULT command selects the
default value for the DAC. These default values are used
for all future clear and gate operations. The new default
setting is determined by bits DF[2:0]. See Table 10.
Available default values are:
POR (000):DAC defaults to power-on reset value
(default).
ZERO (001):
DAC defaults to zero scale.
MID (010):
DAC defaults to midscale.
FULL (011):
DAC defaults to full scale.
RETURN (100): DAC defaults to value specified by the
RETURN register
OTHER:
No effect, the default setting remains
unchanged.
Note: The selected default values do not apply to resets
initiated by SW_RESET commands or supply cycling,
both of which return the DACs to the power-on reset state
(zero scale).
Table 9. CONFIG (0101) Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
0
1
0
1
X
CONFIG COMMAND
DEFAULT VALUES
X
X
X
X
X
X
Don’t Care
X
X
X
X
X
X
X
B8
B7
B6
X
X
X
Don’t
Care
Don’t Care
X
X
X
COMMAND BYTE
X
X
X
X
X
X
X
X
DATA HIGH BYTE
B5
B4
B3
AB2 AB1 AB0
AUXB Mode:
011 = GATE
110 = CLEAR
111 = NONE
Other = No
Effect
1
1
0
B2
B1
B0
X
X
X
Don’t Care
X
X
X
DATA LOW BYTE
Table 10. DEFAULT (0110) Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
0
1
1
0
X
DEFAULT
COMMAND
DEFAULT VALUES
X
X
X
X
X
Don’t Care
X
X
COMMAND BYTE
Maxim Integrated
X
X
X
X
X
X
B8
X
X
X
X
X
X
B6
B5
B4
B3
B2
B1
B0
X
X
X
X
X
Default Values:
000: POR
001: ZERO
010: MID
011: FULL
100: RETURN
Other: No
Effect
Don’t Care
X
B7
DF2 DF1 DF0
X
DATA HIGH BYTE
X
X
0
0
0
Don’t Care
X
X
X
X
X
DATA LOW BYTE
27
MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I2C Interface
RETURN Command
The RETURN command (B[23:20] = 0111) updates the
RETURN register content for the DAC. If the DEFAULT
configuration register is set to RETURN mode, the DAC
will be cleared or gated to the RETURN register value in
the event of a SW or HW CLEAR or GATE condition. It is
not necessary to program this register if the DEFAULT =
RETURN mode will not be used. The data format for the
RETURN register is identical to that used for CODE and
LOAD operations. See Table 3 and Table 4.
Applications Information
Power-On Reset (POR)
When power is applied to VDD, the DAC output is
set to zero scale. To optimize DAC linearity, wait until
the supplies have settled and the internal setup and
calibration sequence completes (200Fs, typ).
Power Supplies and Bypassing
Considerations
Bypass VDD with high-quality ceramic capacitors to
a low-impedance ground as close as possible to the
device. Minimize lead lengths to reduce lead inductance.
Connect GND to the analog ground plane.
Layout Considerations
Digital and AC transient signals on GND can create noise
at the output. Connect GND to form the star ground for
the DAC system. Refer remote DAC loads to this system
ground for the best possible performance. Use proper
grounding techniques, such as a multilayer board with
a low-inductance ground plane, or star connect all
ground return paths back to the MAX5803/MAX5804/
MAX5805 GND. Carefully layout the traces between
channels to reduce AC cross-coupling. Do not use wirewrapped boards and sockets. Use shielding to maximize
noise immunity. Do not run analog and digital signals
parallel to one another, especially clock signals. Avoid
routing digital lines underneath the MAX5803/MAX5804/
MAX5805 package.
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the measured transfer function
from a straight line drawn between two codes once offset
and gain errors have been nullified.
Maxim Integrated
Differential Nonlinearity (DNL)
DNL is the difference between an actual step height and
the ideal value of 1 LSB. If the magnitude of the DNL P
1 LSB, the DAC guarantees no missing codes and is
monotonic. If the magnitude of the DNL R 1 LSB, the DAC
output may still be monotonic.
Offset Error
Offset error indicates how well the actual transfer function
matches the ideal transfer function. The offset error is
calculated from two measurements near zero code and
near maximum code.
Gain Error
Gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
Zero-Scale Error
Zero-scale error is the difference between the DAC
output voltage when set to code zero and ground. This
includes offset and other die level nonidealities.
Full-Scale Error
Full-scale error is the difference between the DAC output
voltage when set to full scale and the reference voltage.
This includes offset, gain error, and other die level
nonidealities.
Settling Time
The settling time is the amount of time required from the
start of a transition, until the DAC output settles to the new
output value within the converter’s specified accuracy.
Digital Feedthrough
Digital feedthrough is the amount of noise that appears
on the DAC output when the DAC digital control lines are
toggled.
Digital-to-Analog Glitch Impulse
A major carry transition occurs at the midscale point
where the MSB changes from low to high and all other
bits change from high to low, or where the MSB changes
from high to low and all other bits change from low to
high. The duration of the magnitude of the switching
glitch during a major carry transition is referred to as the
digital-to-analog glitch impulse.
The digital-to-analog power-up glitch is the duration of
the magnitude of the switching glitch that occurs as the
device exits power-down mode.
28
MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I2C Interface
Typical Operating Circuits
100nF
100nF
VDD
VDDIO
RPU
5kI
4.7µF
RPU
5kI
OUT
DAC
VOUT = -VREF to +VREF
SDA
MICRO CONTROLLER
SCL
ADDR
LDAC
MAX5803
MAX5804
MAX5805
REF
R1
AUX
R2
R1 = R2
GND
NOTE: BIPOLAR OPERATION SHOWN
100nF
100nF
VDDIO
RPU
5kI
4.7µF
VDD
RPU
5kI
OUT
DAC
VOUT = 0V to VREF
SDA
MICRO CONTROLLER
SCL
ADDR
LDAC
MAX5803
MAX5804
MAX5805
REF
AUX
GND
NOTE: UNIPOLAR OPERATION SHOWN
Maxim Integrated
29
MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I2C Interface
Ordering Information
PIN-PACKAGE
RESOLUTION (BIT)
INTERNAL REFERENCE TEMPCO (ppm/NC)
MAX5803ATB+T
PART
10 TDFN-EP*
8
10 (typ), 25 (max)
MAX5803AUB+
10 FMAX
8
10 (typ), 25 (max)
MAX5804ATB+T
10 TDFN-EP*
10
10 (typ), 25 (max)
MAX5804AUB+
10 FMAX
10
10 (typ), 25 (max)
MAX5805AAUB+
10 FMAX
12
4 (typ), 12 (max)
MAX5805BATB+T
10 TDFN-EP*
12
10 (typ), 25 (max)
MAX5805BAUB+
10 FMAX
12
10 (typ), 25 (max)
Note: All devices are specified over the -40°C to +125°C temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*EP = Exposed pad.
Chip Information
PROCESS: BiCMOS
Maxim Integrated
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character,
but the drawing pertains to the package regardless of RoHS
status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
10 TDFN-EP
T1032N+1
21-0429
90-0082
10 FMAX
U10+2
21-0061
90-0330
30
MAX5803/MAX5804/MAX5805
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and I2C Interface
Revision History
REVISION
NUMBER
REVISION
DATE
DESCRIPTION
0
11/12
Initial release
1
2/13
Released the MAX5803/MAX5804. Updated the Electrical Characteristics.
2
6/13
Released the MAX5803/MAX5804/MAX5805 TDFN packages.
PAGES
CHANGED
—
2–8, 30
30
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
©
2013 Maxim Integrated Products, Inc.
31
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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