FUJITSU SEMICONDUCTOR DATA SHEET DS07-12561-1E 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89202 Series MB89202/F202/V201 ■ DESCRIPTION The MB89202 series is a line of single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such, timers, a serial interface, an A/D converter and an external interrupt. ■ FEATURES • • • • • • • • • • • • • • F2MC-8L family CPU core Maximum memory space : 64 Kbytes Minimum execution time : 0.32 µs/12.5 MHz Interrupt processing time : 2.88 µs/12.5 MHz I/O ports : Max 26 channels 21-bit time-base timer 8-bit PWM timer 8/16-bit capture timer/counter 10-bit A/D converter : 8 channels UART 8-bit serial I/O External interrupt 1 : 3 channels External interrupt 2 : 8 channels Wild Register : 2 bytes (Continued) ■ PACKAGES 32-pin plastic SH-DIP 34-pin plastic SSOP (DIP-32P-M06) (FPT-34P-M03) MB89202 Series (Continued) • MB89F202 : Flash (at least 10,000 program / erase cycles) with read protection • Low-power consumption modes ( sleep mode, and stop mode) • SH-DIP-32, SSOP-34 package • CMOS Technology ■ PRODUCT LINEUP Part number MB89202 MB89F202 MB89V201 Classification Mask ROM product Flash memory product (read protection) Evaluation product (for development) ROM size 16 K × 8 bits (internal mask ROM) 16 K × 8 bits (internal flash) 32K x 8 bits (external EPROM) Parameter 512 × 8 bits RAM size CPU functions Ports Number of instructions : Instruction bit length : Instruction length : Data bit length : Minimum execution time : Interrupt processing time : 136 8 bits 1 to 3 bytes 1, 8, 16 bits 0.32 µs to 5.1 µs (12.5 MHz) 2.88 µs to 46.1 µs (12.5 MHz) General-purpose I/O ports (CMOS) : 26 (also serve as peripherals ) (4 ports are also an N-ch open-drain type.) 21-bit time-base timer 21-bit Interrupt cycle : 0.66 ms, 2.64 ms, 21 ms, or 335.5 ms with 12.5 MHz main clock Watchdog timer Reset generation cycle : 335.5 ms minimum with 12.5 MHz main clock 8-bit PWM timer 8-bit interval timer operation (square output capable, operating clock cycle : 0.32 µs , 2.56 µs, 5.1 µs, 20.5 µs) 8-bit resolution PWM operation (conversion cycle : 81.9 µs to 21.47 s : in the selection of internal shift clock of 8/16-bit capture timer) Count clock selectable between 8-bit and 16-bit timer/counter outputs 8/16-bit capture, timer/counter 8-bit capture timer/counter × 1 channel + 8-bit timer or 16-bit capture timer/counter × 1 channel Capable of event count operation and square wave output using external clock input with 8-bit timer 0 or 16-bit counter UART 8-bit Serial I/O 12-bit PPG timer Transfer data length : 6/7/8 bits 8 bits LSB first/MSB first selectable One clock selectable from four operation clocks (one external shift clock, three internal shift clocks : 0.8 µs, 6.4 µs, 25.6 µs) Output frequency : Pulse width and cycle selectable External interrupt 1 (wake-up function) 3 channels (Interrupt vector, request flag, request output enabled) Edge selectable (Rising edge, falling edge, or both edges) Also available for resetting stop/sleep mode (Edge detectable even in stop mode) External interrupt 2 (wake-up function) 1 channel with 8 inputs (Independent L-level interrupt and input enable) Also available for resetting stop/sleep mode (Level detectable even in stop mode) (Continued) 2 MB89202 Series (Continued) Part number Parameter 10-bit A/D converter MB89202 MB89V201 MB89F202 10-bit precision × 8 channels A/D conversion function (Conversion time : 12.16 µs/12.5 MHz) Continuous activation by 8/16-bit timer/counter output or time-base timer counter Wild Register 8-bit × 2 Standby mode Sleep mode, and Stop mode Overhead time from reset to the first instruction execution Power supply voltage*2 Power-on reset : Oscillation stabillization wait*1 External reset : a few µs Software reset : a few µs Power-on reset : Voltage regulator and oscillation stabillization wait (31.5 ms/12.5 MHz) External reset : Oscillation stabillization wait (21.0 ms/12.5 MHz) Software reset : a few µs 2.2 V to 5.5 V Power-on reset : Oscillation stabillization wait (21.0 ms / 12.5 MHz) External reset : Oscillation stabillization wait (21.0 ms / 12.5 MHz) Software reset : a few µs 3.5 V to 5.5 V 2.7 V to 5.5 V *1 : Check section “■ MASK OPTIONS” *2 : The minimum operating voltage varies with the operating frequency, the function, and the connected ICE. (The operating voltage of the A/D converter is assured separately. Check section “■ ELECTRICAL CHARACTERISTICS.”) ■ PACKAGE AND CORRESPONDING PRODUCTS Package MB89202 MB89F202 MB89V201 DIP-32P-M06 × FPT-34P-M03 × FPT-64P-M03 : Available × × × : Not available ■ DIFFERENCES AMONG PRODUCTS • Memory Size Before evaluating using the evaluation product, verify its differences from the product that will actually be used. • Mask Options Functions that can be selected as options and how to designate these options vary by the product. Before using options check section “■ MASK OPTIONS”. 3 MB89202 Series ■ PIN ASSIGNMENTS (TOP VIEW) P04/INT24 1 32 VCC P05/INT25 2 31 P03/INT23/AN7 P06/INT26 3 30 P02/INT22/AN6 P07/INT27 4 29 P01/INT21/AN5 P60 5 28 P00/INT20/AN4 P61 6 27 P43/AN3* RST 7 26 P42/AN2* X0 8 25 P41/AN1* X1 9 24 P40/AN0* VSS 10 23 P72* P37/BZ/PPG 11 22 P71* P36/INT12 12 21 P70* P35/INT11 13 20 P50/PWM P34/TO/INT10 14 19 P30/UCK/SCK P33/EC 15 18 P31/UO/SO C 16 17 P32/UI/SI * : Large-current drive type (DIP-32P-M06) (Continued) 4 MB89202 Series (Continued) (TOP VIEW) P04/INT24 1 34 VCC P05/INT25 2 33 P03/INT23/AN7 P06/INT26 3 32 P02/INT22/AN6 P07/INT27 4 31 P01/INT21/AN5 P60 5 30 P00/INT20/AN4 P61 6 29 P43/AN3 * RST 7 28 P42/AN2 * X0 8 27 P41/AN1 * X1 9 26 P40/AN0 * 10 25 P72 * P37/BZ/PPG 11 24 P71 * P36/INT12 12 23 P70 * P35/INT11 13 22 N.C. P34/TO/INT10 14 21 P50/PWM P33/EC 15 20 P30/UCK/SCK N.C. 16 19 P31/UO/SO C 17 18 P32/UI/SI VSS *: Large-current drive type N.C. : Internally connected. Do not use. (FPT-34P-M03) 5 MB89202 Series ■ PIN DESCRIPTION Pin No. Pin name SH-DIP32*1 SSOP34*2 8 8 X0 9 9 X1 5, 6 5, 6 P60, P61 Circuit type Function A Pins for connecting the crystal for the main clock. To use an external clock, input the signal to X0 and leave X1 open. H/E General-purpose CMOS input port for MB89F202. General-puspose CMOS I/O port for MB89202/MB89V201. C Reset I/O pin. This pin serves as an N-channel open-drain reset output with pull-up resistor (not available for MB89F202) and a reset input as well. The reset is a hysteresis input. It outputs the “L” signal in response to an internal reset request. Also, it initializes the internal circuit upon input of the “L” signal. P00/INT20/ AN4 28 to 31 30 to 33 to P03/ INT23/AN7 G General-purpose CMOS I/O ports. These pins also serve as an input (wake-up input) of external interrupt 2 or as an 10-bit A/D converter analog input. The input of external interrupt 2 is a hysteresis input. 7 7 RST 1 to 4 1 to 4 P04/INT24 to P07/INT27 D General-purpose CMOS I/O ports. These pins also serve as an input (wake-up input) of external interrupt 2. The input of external interrupt 2 is a hysteresis input. 19 20 P30/UCK/ SCK B General-purpose CMOS I/O ports. This pin also serves as the clock I/O pin for the UART or 8-bit serial I/O. The resource is a hysteresis input. 18 19 P31/UO/SO E General-purpose CMOS I/O ports. This pin also serves as the data output pin for the UART or 8-bit serial I/O. 17 18 P32/UI/SI B General-purpose CMOS I/O ports. This pin also serves as the data input pin for the UART or 8-bit serial I/O. The resource is a hysteresis input. 15 15 P33/EC B General-purpose CMOS I/O ports. This pin also serves as the external clock input pin for the 8/16-bit capture timer/counter. The resource is a hysteresis input. 14 14 P34/TO/ INT10 B General-purpose CMOS I/O ports. This pin also serves as the output pin for the 8/16-bit capture timer/ counter or as the input pin for external interrupt 1. The resource is a hysteresis input. 13, 12 13, 12 P35/INT11, P36/INT12 B General-purpose CMOS I/O ports. These pins also serve as the input pin for external interrupt 1. The resource is a hysteresis input. 11 11 P37/BZ/ PPG E General-purpose CMOS I/O ports. This pin also serves as the buzzer output pin or the 12-bit PPG output. 20 21 P50/PWM E General-purpose CMOS I/O ports. This pin also serves as the 8-bit PWM timer output pin. (Continued) 6 MB89202 Series (Continued) Pin No. SH-DIP32*1 Pin name Circuit type Function P40/AN0 to P43/ AN3 F General-purpose CMOS I/O ports. These pins can also be used as N-channel open-drain ports. These pins also serve as 10-bit A/D converter analog input pins. E General-purpose CMOS I/O ports. SSOP34*2 24 to 27 26 to 29 21 to 23 23 to 25 P70 to P72 32 34 VCC ⎯ Power supply pin 10 10 VSS ⎯ Power (GND) pin 16 17 C ⎯ MB89F202: Capacitance pin for regulating the power supply. Connect an external ceramic capacitor of about 0.1µF. MB89202: This pin is not internally connected. It is unnecessary to connect a capacitor. ⎯ 16, 22 N.C. ⎯ Internally connected pins Be sure to leave it open. *1 : DIP-32P-M06 *2 : FPT-34P-M03 7 MB89202 Series ■ I/O CIRCUIT TYPE Type Circuit Remarks • At an oscillation feedback resistance of approximately 500 kΩ X1 A X0 Standby control signal • CMOS output • Hysteresis input • Pull-up resistor optional P-ch P-ch B N-ch Port input / Resource input Input enable P-ch (not available for MB89F202) C N-ch • At an output pull-up resister (P-ch) of approximately 50 kΩ/5.0 V (not available for MB89F202) • N-ch open-drain reset output • Hysteresis input Reset • • • • P-ch CMOS output CMOS input Hysteresis input (Resource input) Pull-up resistor optional P-ch D N-ch Input enable Port input Input enable Resource input (Continued) 8 MB89202 Series (Continued) Type Circuit Remarks P-ch • • • • CMOS output CMOS input Pull-up resistor optional P70-P72 are large-current drive type • • • • • CMOS output CMOS input Analog input N-ch open-drain output available P40-P43 are large-current drive type • • • • CMOS output CMOS input Hysteresis input (Resource input) Analog input P-ch E N-ch Port input Input enable P-ch Open-drain control N-ch F Analog input Input enable Port input A/D enable P-ch P-ch G N-ch Input enable Port input Input enable Resource input Analog input A/D enable • CMOS input H Input enable Port input 9 MB89202 Series ■ HANDLING DEVICES • Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in section “■ ELECTRICAL CHARACTERISTICS” is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. • Treatment of Unused Input Pins Leaving unused input terminals open may lead to permanent damage due to malfunction and latchup; pull up or pull down the terminals through the resistors of 2 kΩ or more. Make the unused I/O terminal in a state of output and leave it open or if it is in an input state, handle it with the same procedure as the input terminals. • Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. • Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 Hz to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. • Precautions when Using an External Clock When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and wake-up from stop mode. • About the Wild Register Function No wild register can be debugged on the MB89V201. For the operation check, test the MB89F202 installed on a target system. • Program Execution in RAM When the MB89V201 is used, no program can be executed in RAM. • Note to Noise in the External Reset Pin (RST) If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST). • External pullup for the External Reset Pin (RST) of MB89F202 Internal pullup control for RST pin is not available for MB89F202. To ensure proper external reset control in MB89F202, an external pullup (recommend 100 kΩ) for RST pin must be required. (Continued) 10 MB89202 Series (Continued) • Notes on selecting mask option Please select “With reset output” by the mask option when power-on reset is generated at the power supply ON, and the device is used without inputting external reset. 11 MB89202 Series ■ PROGRAMMING AND ERASE FLASH MEMORY ON THE MB89F202 1. Flash Memory The flash memory is located between C000H and FFFFH in the CPU memory map and incorporates a flash memory interface circuit that allows read access and program access from the CPU to be performed in the same way as mask ROM. Programming and erasing flash memory is also performed via the flash memory interface circuit by executing instructions in the CPU. This enables the flash memory to be updated in place under the control of the CPU, providing an efficient method of updating program and data. 2. Flash Memory Features • • • • • • 16 K byte × 8-bit configuration Automatic programming algorithm (Embedded Algorithm*) Data polling and toggle bit for detection of program/erase completion Detection of program/erase completion via CPU interrupt Compatible with JEDEC-standard commands No. of program / erase cycles : Minimum 10,000 * : Embedded Algorithm is a trademark of Advanced Micro Devices. 3. Procedure for Programming and Erasing Flash Memory Programming and reading flash memory cannot be performed at the same time. Accordingly, to program or erase flash memory, the program must first be copied from flash memory to RAM so that programming can be performed without program access from flash memory. 4. Flash Memory Control Status Register (FMCS) bit 7 bit 6 bit 5 bit 4 INTE RDYINT WE RDY R/W R/W R/W R bit 3 bit 2 bit 1 bit 0 Address 0079H Initial value 000X----B 5. Memory Space The memory space for the CPU access and for the flash programmer access is listed below. Memory size CPU address Programmer address 16 K bytes FFFFH to C000H FFFFH to C000H 6. Flash Programmer Adapter and Recommended Flash Programmers • Parallel programmer Part number Package Adapter Part number Programmer Part number * MB89F202P-SH DIP-32P-M06 TEF200-89F202-PSH MB89F202PFV FPT-34P-M03 TEF200-89F202-PFV AF9708, AF9709/B, AF9723 + AF9834 * : For the programmer and the version of the programmer,contact the Flash Support Group, Inc. Inquiry : Flash Support Group, Inc. : FAX : 81-(53)-428-8377 : E-mail : [email protected] • Serial programmer (PC programmer) Part number Package Adapter Part number MB89F202P-SH DIP-32P-M06 ROM3-DIP32PM06-8L MB89F202PFV FPT-34P-M03 ROM3-FPT34PM03-8L Inquiries : Adapter : Sunhayato Corp. : FAX : 81-(3)-3971-0535 E-mail : [email protected] PC programmer software : FUJITSU LIMITED 12 MB89202 Series 7. Flash Content Protection Flash content can be read using parallel / serial programmer if the flash content protection mechanism is not activated. One predefined area of the flash (FFFCH) is assigned to be used for preventing the read access of flash content. If the protection code "01H" is written in this address (FFFCH), the flash content cannot be read by any parallel/ serial programmer. Note : The program written into the flash cannot be verified once the flash protection code is written ("01H" in FFFCH). It is advised to write the flash protection code at last. ■ PROGRAMMING TO THE EPROM WITH EVALUATION PRODUCT DEVICE 1. EPROM for Use MBM27C256A (DIP-28) 2. Memory Space. Normal operating mode Address 0000H I/O 0080H RAM 512 bytes 0280H Not available Corresponding adresses on the ROM programmer Address 8000H 0000H PROM 32 Kbytes FFFFH EPROM 32 Kbytes 7FFFH 3. Programming to the EPROM (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0000H to 7FFFH. (3) Program to 0000H to 7FFFH with the EPROM programmer. 13 MB89202 Series ■ BLOCK DIAGRAM X0 Main clock oscillator X1 Time-base timer Clock controller Reset circuit Port 6 RST 2 Port 5 CMOS I/O port 8-bit PWM P50 / PWM CMOS I/O port P60 ,P61 CMOS I/O port 4 8 Port 0 P00 / INT20 / AN4 4 to P03 / INT23 / AN7 8-bit serial I/O 10-bit A/D Converter 8/16-bit capture timer/ counter 4 Port 4 4 P40 / AN0* 4 to P43 / AN3* External interrupt2 (wake-up) P30 / UCK / SCK P31 / UO / SO P32 / UI / SI CMOS I/O port (N-ch OD) Exernal interrupt 1 P33 / EC Port 3 P04 / INT24 to P07 / INT27 UART Serial function switching CMOS I/O port Internal bus P70* to P72* Port 7 UART prescaler 3 3 P34 / TO / INT10 2 P35 / INT11, P36 / INT12 512 bytes RAM 12-bit PPG P37 / BZ / PPG F2MC - 8 L CPU Other pins VCC, VSS, C Buzzer output 16 Kbytes ROM Wild register * : Large-current drive type 14 CMOS I/O port MB89202 Series ■ CPU CORE 1. Memory Space The microcontrollers of the MB89202 series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89202 series is structured as illustrated below. • Memory Space MB89202 MB89F202 0000H I/O 0080H I/O 0080H RAM 512 Bytes I/O 0080H RAM 512 Bytes RAM 512 Bytes 0100H Register 0100H Register 0100H MB89V201 0000H Register 0000H 0200H 0200H 0200H 0280H 0280H 0280H Not available Not available Not available 8000H C000H C000H ROM 16 KBytes FFFFH External EPROM 32 KBytes FLASH 16 KBytes FFFFH FFFFH 15 MB89202 Series 2. Registers The MB89202 series has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided : Program counter (PC) : A 16-bit register for indicating instruction storage positions Accumulator (A) : A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX) : A 16-bit register for index modification Extra pointer (EP) : A 16-bit pointer for indicating a memory address Stack pointer (SP) : A 16-bit register for indicating a stack area Program status (PS) : A 16-bit register for storing a register pointer, a condition code Initial value 16 bits : Program counter FFFDH A : Accumulator Undefined T : Temporary accumulator Undefined IX : Index register Undefined EP : Extra pointer Undefined SP : Stack pointer Undefined PC RP I-flag = 0, IL1, 0 = 11 The other bit values are undefined. : Program status CCR PS The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR) . (See the diagram below.) • Structure of the Program Status Register RP CCR bit15 bit14 bit13 bit12 bit11 bit10 bit9 R3 R2 R1 R0 − − PS R4 H-flag I-flag IL1,0 N-flag Z-flag × : Undefined V-flag C-flag 16 bit8 − bit7 H bit6 I bit5 IL1 bit4 IL0 bit3 N bit2 Z bit1 bit0 V C CCR initial value X011XXXXB MB89202 Series The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. • Rule for Conversion of Actual Addresses of the General-purpose Register Area Lower OP codes RP "0" Generated addresses "0" "0" "0" "0" "0" A15 A14 A13 A12 A11 A10 "0" A9 "1" A8 R4 A7 R3 A6 R2 R1 A5 R0 A4 b2 A3 A2 b1 A1 b0 A0 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag : Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared to “0” otherwise. This flag is for decimal adjustment instructions. I-flag : Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when the flag is cleared to “0”. Cleared to “0” at the reset. IL1, 0 : Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 IL0 Interrupt level 0 0 0 1 1 0 2 1 1 3 1 High-low High Low = no interrupt N-flag : Set to “1” if the MSB becomes to “1” as the result of an arithmetic operation. Cleared to “0” when the bit is cleared to “0”. Z-flag : Set to “1” when an arithmetic operation results in 0. Cleared to “0” otherwise. V-flag : Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0” if the overflow does not occur. C-flag : Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to “0” otherwise. Set to the shift-out value in the case of a shift instruction. 17 MB89202 Series The following general-purpose registers are provided : General-purpose registers : An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 16 banks can be used on the MB89202 series. The bank currently in use is indicated by the register bank pointer (RP) . • Register Bank Configuration This address = 0100H + 8 × (RP) R0 R1 R2 R3 R4 R5 R6 R7 16 banks Memory area 18 MB89202 Series ■ I/O MAP Address Register name Register description 0000H PDR0 Port 0 data register 0001H DDR0 Port 0 data direction register 0002H to 00006H Read/write Initial value R/W X X XXXX X X W 0 0 0 00 0 0 0 Reserved 0007H SYCC System clock control register R/W 1 - - MM 1 0 0 0008H STBC Standby control register R/W 0 0 0 10 - - - 0009H WDTC Watchdog timer control register R/W 0 - - - XX XX 000AH TBTC Time-base timer control register R/W 0 0 - - - 0 0 0 R/W X X XXXX X X Reserved 000BH 000CH PDR3 Port 3 data register 000DH DDR3 Port 3 data direction register W 0 0 0 00 0 0 0 000EH RSFR Reset flag register R XXXX- - - - 000FH PDR4 Port 4 data register R/W - - - - XX XX 0010H DDR4 Port 4 data direction register R/W - - - - 0 0 0 0 0011H OUT4 Port 4 output format register R/W - - - - 0 0 0 0 0012H PDR5 Port 5 data register R/W - - - - - - - X 0013H DDR5 Port 5 data direction register R/W - - - - - - - 0 0014H RCR21 12-bit PPG control register 1 R/W 0 0 0 00 0 0 0 0015H RCR22 12-bit PPG control register 2 R/W - - 0 00 0 0 0 0016H RCR23 12-bit PPG control register 3 R/W 0 - 0 00 0 0 0 0017H RCR24 12-bit PPG control register 4 R/W - - 0 00 0 0 0 0018H BZCR Buzzer register R/W - - - - - 0 0 0 0019H TCCR Capture control register R/W 0 0 0 00 0 0 0 001AH TCR1 Timer 1 control register R/W 0 0 0 - 0 0 0 0 001BH TCR0 Timer 0 control register R/W 0 0 0 00 0 0 0 001CH TDR1 Timer 1 data register R/W X X XXXX X X 001DH TDR0 Timer 0 data register R/W X X XXXX X X 001EH TCPH Capture data register H R X X XXXX X X 001FH TCPL Capture data register L R X X XXXX X X 0020H TCR2 Timer output control register R/W - - - - - - 0 0 R/W 0 - 0 00 0 0 0 W X X XXXX X X R/W 0 0 0 00 0 0 0 Reserved 0021H 0022H CNTR PWM control register 0023H COMR PWM compare register 0024H EIC1 External interrupt 1 Control register 1 (Continued) 19 MB89202 Series Address Register name 0025H EIC2 Register description External interrupt 1 Control register 2 0026H Read/write Initial value R/W - - - - 0 0 0 0 Reserved 0027H 0028H SMC Serial mode control register R/W 0 0 0 00 - 0 0 0029H SRC Serial rate control register R/W - - 0 11 0 0 0 002AH SSD Serial status and data register R/W 0 0 1 00 - 1 X SIDR Serial input data register R X X XXXX X X SODR Serial output data register W X X XXXX X X R/W - - - - 0 0 1 0 002BH 002CH UPC Clock division selection register 002DH to 002FH Reserved 0030H ADC1 A/D converter control register 1 R/W - 0 0 00 0 0 0 0031H ADC2 A/D converter control register 2 R/W - 0 0 00 0 0 1 0032H ADDH A/D converter data register H R - - - - - - XX 0033H ADDL A/D converter data register L R X X XXXX X X 0034H ADEN A/D enable register R/W 0 0 0 00 0 0 0 0035H Reserved 0036H EIE2 External interrupt 2 control register1 R/W 0 0 0 00 0 0 0 0037H EIF2 External interrupt 2 control register2 R/W - - - - - - - 0 Reserved 0038H 0039H SMR Serial mode register R/W 0 0 0 00 0 0 0 003AH SDR Serial data register R/W X X XXXX X X 003BH SSEL Serial function switching register R/W - - - - - - - 0 003CH to 003FH Reserved 0040H WRARH0 Upper-address setting register R/W X X XXXX X X 0041H WRARL0 Lower-address setting register R/W X X XXXX X X 0042H WRDR0 Data setting register 0 R/W X X XXXX X X 0043H WRARH1 Upper-address setting register R/W X X XXXX X X 0044H WRARL1 Lower-address setting register R/W X X XXXX X X 0045H WRDR1 Data setting register 1 R/W X X XXXX X X 0046H WREN Address comparison EN register R/W X X XXXX 0 0 0047H WROR Wild-register data test register R/W - - - - - - 0 0 0048H to 005FH Reserved (Continued) 20 MB89202 Series (Continued) Address Register name Register description Read/write Initial value 0060H PDR6 Port 6 data register R/W - - - - - - XX 0061H DDR6 Port 6 data direction register* R/W - - - - - - 0 0 0062H PUL6 Port 6 pull-up setting register R/W - - - - - - 0 0 0063H PDR7 Port 7 data register R/W - - - - - X XX 0064H DDR7 Port 7 data direction register R/W - - - - - 0 0 0 0065H PUL7 Port 7 pull-up setting register R/W - - - - - 0 0 0 0066H to 006FH Reserved 0070H PUL0 Port-0 pull-up setting register R/W 0 0 0 00 0 0 0 0071H PUL3 Port-3 pull-up setting register R/W 0 0 0 00 0 0 0 0072H PUL5 Port-5 pull-up setting register R/W - - - - - - - 0 R/W 0 0 0 X- - - - 0073H to 0078H 0079H Reserved FMCS Flash memory control status register 007AH Reserved 007BH ILR1 Interrupt level setting register1 W 1 1 1 11 1 1 1 007CH ILR2 Interrupt level setting register2 W 1 1 1 11 1 1 1 007DH ILR3 Interrupt level setting register3 W 1 1 1 11 1 1 1 007EH ILR4 Interrupt level setting register4 W 1 1 1 11 1 1 1 007FH ITR Interrupt test register Not available - - - - - - 0 0 - : Unused, X : Undefined, M : Set using the mask option * : No used in MB89F202 Note : Do not use prohibited areas. 21 MB89202 Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Symbol Rating Unit Min Max VCC VSS − 0.3 VSS + 6.0 V Input voltage* VI VSS − 0.3 VCC + 0.3 V Output voltage* VO VSS − 0.3 VCC + 6.0 V “L” level maximum output current IOL ⎯ 15 mA Power supply voltage* Remarks IOLAV1 ⎯ 4 mA Average value (operating current × operating rate) Pins excluding P40 to P43, P70 to P72 IOLAV2 ⎯ 12 mA Average value (operating current × operating rate) Pins P40 to P43, P70 to P72 “L” level total maximum output current ΣIOL ⎯ 100 mA “H” level maximum output current IOH ⎯ −10 mA Pins excluding P60, P61 “H” level average output current IOHAV ⎯ −4 mA Average value (operating current × operating rate) “H” level total maximum output current ΣIOH ⎯ −50 mA Power consumption Pd ⎯ 200 mW Operating temperature Ta −40 +85 °C Tstg −55 +150 °C “L” level average output current Storage temperature * : This parameter is based on VSS = 0.0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 22 MB89202 Series 2. Recommended Operating Conditions (Vss = 0.0V) Parameter Symbol Value Unit Remarks Min Max 2.2 5.5 V MB89202 3.5 5.5 V MB89F202 2.7 5.5 V MB89V201 1.5 5.5 V Retains the RAM state in stop mode VIH 0.7 VCC VCC + 0.3 V P00 to P07, P31, P37, P40 to P43, P50, P60, P61, P70 to P72 VIHS 0.8 VCC VCC + 0.3 V RST, EC, INT20 to INT27, UCK/SCK, INT10 to INT12, P30, P32 to P36, UI/SI VIL VSS − 0.3 0.3 VCC V P00 to P07, P31, P37, P40 to P43, P50, P60, P61, P70 to P72 VILS VSS − 0.3 0.2 VCC V RST, EC, INT20 to INT27, UCK/SCK, INT10 to INT12, P30, P32 to P36, UI/SI Open-drain output pin application voltage VD VSS − 0.3 VCC + 0.3 V P40 to P43, RST Operating temperature Ta −40 +85 °C Room temperature is recommended for programming the flash memory on MB89F202 Power supply voltage VCC “H” level input voltage “L” level input voltage 23 MB89202 Series Operating Assurance for MB89202 and MB89V201 6 5.5 Operating voltage (V) 5 Analog accuracy assurance range 4.5 4 Operation assurance range 3.5 3 2.7 2.2 2 : Area is assured only for the MB89202 1 0 1 2 3 4 5 6 7 8 Operating Frequency (MHz) 9 10 11 12.5 9 10 11 12.5 Operating Assurance for MB89F202 6 5.5 Operating voltage (V) 5 Analog accuracy assurance range 4.5 Operation assurance range 4 3.5 3 2 1 0 1 2 3 4 5 6 7 8 Operating Frequency (MHz) WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 24 MB89202 Series 3. DC Characteristics (VCC = 5.0 V ± 10%, VSS = 0.0 V, FCH = 12.5 MHz (External clock) , Ta = −40 °C to +85 °C) Parameter Symbol Pin name Condition Value Min Typ Max Unit Remarks VIH P00 to P07, P31, P37, P40 to P43, P50, P60, P61, P70 to P72 ⎯ 0.7 VCC ⎯ VCC + 0.3 V VIHS P30, P32 to P36, RST UCK/SCK, UI/SI, EC, INT20 to INT27, INT10 to INT12 ⎯ 0.8 VCC ⎯ VCC + 0.3 V VIL P00 to P07, P31, P37, P40 to P43, P50, P60, P61, P70 to P72 ⎯ VSS − 0.3 ⎯ 0.3 VCC V VILS P30, P32 to P36, RST, UCK/SCK, UI/SI, EC, INT20 to INT27, INT10 to INT12 ⎯ VSS − 0.3 ⎯ 0.2 VCC V Open-drain output pin application voltage VD P40 to P43, RST ⎯ VSS − 0.3 ⎯ VCC + 0.3 V “H” level output voltage VOH P00 to P07, P30 to P37, P40 to P43, P50, IOH = −4.0 mA P70 to P72 4.0 ⎯ ⎯ V VOL1 P00 to P07, P30 to P37, IOL = 4.0 mA P50, RST ⎯ ⎯ 0.4 V VOL2 P40 to P43, P70 to P72 ⎯ ⎯ 0.4 V ⎯ ⎯ ±5 Without µA pull-up resistor “H” level input voltage “L” level input voltage “L” level output voltage Input leakage current Pull-up resistance ILI RPULL IOL = 12.0 mA P00 to P07, P30 to P37, P40 to P43, P50 , 0.45 V < VI < VCC P60, P61, RST, P70 to P72 P00 to P07, P30 to P37, P50, RST, P70 to P72 P00 to P07, P30 to P37, P50, P70 to P72 MB89202 VI = 0.0 V 25 50 100 kΩ MB89F202 (Continued) 25 MB89202 Series (Continued) Parameter Symbol ICC Power supply current ICCS ICCH Input capacitance 26 CIN Pin name Normal operation mode (External clock, highest gear speed) VCC Sleep mode (External clock, highest gear speed) Stop mode Ta = +25 °C (External clock) Other than C, VCC, VSS Condition Value Unit Remarks Min Typ Max When A/D converter stops ⎯ 8 12 mA MB89202 ⎯ 6 9 mA MB89F202 When A/D converter starts ⎯ 10 15 mA MB89202 ⎯ 8 12 mA MB89F202 ⎯ 4 6 mA MB89202 ⎯ 3 5 mA MB89F202 ⎯ ⎯ 1 µA MB89202 ⎯ ⎯ 10 µA MB89F202 ⎯ 10 ⎯ pF When A/D converter stops When A/D converter stops ⎯ MB89202 Series 4. AC Characteristics (1) Reset Timing (VSS = 0.0 V, Ta = −40 °C to +85 °C) Parameter Symbol Condition tZLZH tirst RST “L” pulse width Internal reset pulse extension Value Unit Min Max ⎯ 45 ⎯ ns ⎯ 48 tHCYL* ⎯ ns Remarks * : tHCYL 1 oscillating clock cycle time tZLZH 0.8 VCC 0.2 VCC 0.2 VCC RST Internal reset signal tirst Notes: •When the power-on reset option is not on, leave the external reset on until oscillation becomes stable. • If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST). (2) Power-on Reset (VSS = 0.0 V, Ta = −40 °C to +85 °C) Parameter Symbol Power supply rising time tR Power supply cut-off time tOFF Condition ⎯ tR Value Unit Min Max ⎯ 50 ms 1 ⎯ ms Remarks Due to repeated operations tOFF 3.5 V VCC 0.2 V 0.2 V 0.2 V Note : The supply voltage must be set to the minimum value required for operation within the prescribed default oscillation settling time. 27 MB89202 Series (3) Clock Timing (VSS = 0.0 V, Ta = –40°C to +85°C) Symbol Parameter Condition Value Min Max Unit Clock frequency FCH 1 12.5 MHz Clock cycle time tXCYL 80 1000 ns Input clock pulse width tWH tWL 20 ⎯ ns Input clock rising/falling time tCR tCF ⎯ 10 ns ⎯ Remarks • X0 and X1 Timing and Conditions tXCYL tWH tWL tCR tCF X0 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 0.2 VCC • Main Clock Conditions When a crystal or ceramic resonator is used X0 X1 When an exernal clock is used X0 X1 open (4) Instruction Cycle 28 Parameter Symbol Value (typical) Unit Instruction cycle (minimum execution time) tINST 4/FCH, 8/FCH, 16/FCH, 64/FCH µs Remarks tINST = 0.32 µs when operating at FCH = 12.5 MHz (4/FCH) MB89202 Series (5) Peripheral Input Timing (VCC = 5.0 V ± 10%, VSS = 0.0 V, Ta = −40 °C to +85 °C) Parameter Symbol Pin name Peripheral input “H” pulse width tILIH Peripheral input “L” pulse width tIHIL INT10 to INT12, INT20 to INT27, EC Value Unit Min Max 2 tINST* ⎯ µs 2 tINST* ⎯ µs Remarks * : For information on tINST see “ (4) Instruction Cycle”. tIHIL tILIH INT10 to INT12, INT20 to INT27, EC 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC (VCC = 5.0 V ± 10%, VSS = 0.0 V, Ta = −40 °C to +85 °C) Parameter Symbol Pin name Peripheral input “H” noise limit tIHNC Peripheral input “L” noise limit tILNC P00 to P07, P30 to P37, P40 to P43, P50,P60,P61, P70 to P72, RST, EC, INT20 to INT27, INT10 to INT12 P00 to P07, P30 to P37, P40 to P43, P50, P60, P61, P70 to P72, RST, EC, INT20 to INT27, INT10 to INT12 tIHNC Value Unit Min Typ Max ⎯ 45 ⎯ ns ⎯ 45 ⎯ ns Remarks tILNC 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 29 MB89202 Series (6) UART, Serial I/O Timing (VCC = 5.0 V ± 10%, VSS = 0.0 V, Ta = −40 °C to +85 °C) Symbol Pin name Serial clock cycle time tSCYC UCK/SCK UCK/SCK ↓ → SO time tSLOV Valid SI → UCK/SCK↑ Parameter Condition Value Max 2 tINST* ⎯ µs −200 200 ns tIVSH UCK/SCK, SO Internal shift UCK/SCK, SI clock mode 1/2 tINST* ⎯ µs UCK/SCK ↑ → Valid SI hold time tSHIX UCK/SCK, SI 1/2 tINST* ⎯ µs Serial clock “H” pulse width tSHSL UCK/SCK tINST* ⎯ µs Serial clock “L” pulse width tSLSH UCK/SCK tINST* ⎯ µs UCK/SCK ↓ → SO time tSLOV UCK/SCK, SO 0 200 ns Valid SI → UCK/SCK tIVSH UCK/SCK, SI 1/2 tINST* ⎯ µs UCK/SCK ↑ → Valid SI hold time tSHIX UCK/SCK, SI 1/2 tINST* ⎯ µs External shift clock mode * : For information on tinst, see “ (4) Instruction Cycle”. • Internal Shift Clock Mode tSCYC 2.4 V UCK/SCK 0.8 V 0.8 V tSLOV 2.4 V 0.8 V SO tIVSH tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC SI • External Shift Clock Mode tSLSH tSHSL 0.8 VCC UCK/SCK 0.2 VCC 0.2 VCC tSLOV SO 2.4 V 0.8 V tIVSH SI 30 Unit Remarks Min tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 0.8 VCC MB89202 Series 5. A/D Converter (1) A/D Converter Electrical Characteristics (VSS = 0.0 V, Ta = −40 °C to +85 °C) Parameter Symbol Resolution Total error Linearity error ⎯ Differential linearity error Value Unit Min Typ Max ⎯ ⎯ 10 bit −5.0 ⎯ +5.0 LSB −3.0 ⎯ +3.0 LSB −2.5 ⎯ +2.5 LSB Zero transition voltage VOT VSS − 3.5 LSB VSS + 0.5 LSB VSS + 4.5 LSB V Full-scale transition voltage VFST VCC − 6.5 LSB VCC − 1.5 LSB VCC + 2.0 LSB V A/D mode conversion time ⎯ ⎯ ⎯ 38 tINST* µs Analog port input current IAIN ⎯ ⎯ 10 µA Analog input voltage range ⎯ 0 ⎯ VCC V Power supply voltage for A/D accuracy assurance VCC 4.5 ⎯ 5.5 V Remarks * : For information on tinst, see “ (4) Instruction Cycle” in “4. AC Characteristics.” 31 MB89202 Series (2) A/D Converter Glossary • Resolution Analog changes that are identifiable with the A/D converter When the number of bits is 10, analog voltage can be divided into 210 = 1024. • Linearity error (unit : LSB) The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with the full-scale transition point (“11 1111 1111” ↔ “11 1111 1110”) from actual conversion characteristics • Differential linearity error (unit : LSB) The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value • Total error (unit : LSB) The difference between theoretical and actual conversion values Total error Theoretical I/O characteristics VFST 3FFH 3FFH 3FEH 3FEH 1.5 LSB 3FDH Digital output Digital output 3FDH 004H VOT 003H Actual conversion value {1 LSB × N + 0.5 LSB} 004H VNT Actual conversion value 003H 1 LSB 002H 002H 001H Theoretical value 001H 0.5 LSB AVSS VCC AVSS 1 LSB = VFST − VOT 1022 Total error of digital output N = (V) VCC Analog input Analog input Zero transition error VNT − {1 LSB × N + 0.5 LSB} 1 LSB Full-scale transition error Theoretical value 004H Actual conversion value 3FFH Actual conversion value 002H Theoretical conversion value Actual conversion value Digital output Digital output 003H 3FEH 3FDH 001H VOT (Measured value) VFST (Measured value) 3FCH Actual conversion value AVSS VCC Analog input Analog input (Continued) 32 MB89202 Series (Continued) Differential linearity error 3FFH Actual conversion value 3FEH {1 LSB × N + VOT} Theoretical conversion value N+1 Actual conversion value 3FDH VFST (Measured value) VNT 004H Actual conversion value Digital output Digital output Linearity error V (N + 1) T N N−1 VNT 003H 002H 001H Theoretical conversion value N−2 Actual conversion value VOT (Measured value) AVSS VCC Analog input Analog input Linearity error of digital output N = VCC AVSS VNT − {1 LSB × N + VOT} 1 LSB Differential linearity error of digital output N = V (N + 1) T − VNT −1 1 LSB 33 MB89202 Series (3) Notes on Using A/D Converter • About the external impedance of analog input and its sampling time • A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. • Analog input circuit model R Analog input Comparator ↑ During sampling : ON C R 2.2 kΩ (Max) 2.0 kΩ (Max) MB89202 MB89F202 Note : The values are reference values. C 45 pF (Max) 16 pF (Max) • To satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. • The relationship between the external impedance and minimum sampling time [External impedance = 0 kΩ to 100 kΩ] MB89F202 MB89202 MB89F202 20 MB89202 18 90 External impedance (kΩ) External impedance (kΩ) 100 [External impedance = 0 kΩ to 20 kΩ] 80 70 60 50 40 30 20 10 16 14 12 10 8 6 4 2 0 0 5 10 15 20 25 Minimum sampling time (µs) 30 35 0 0 1 2 3 4 5 6 7 8 Minimum sampling time (µs) • If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin. • About errors As |VCC − AVSS| becomes smaller, values of relative errors grow larger. 34 MB89202 Series 6. MB89F202 Flash Memory Program / Erase Characteristics Parameter Value Unit Remarks Min Typ Max Chip erase time (16 KB) ⎯ 0.5*1 7.5*2 s Excludes programming prior to erasure Byte programming time ⎯ 32 3600 µs Excludes system-level overhead Program / Erase cycle 10,000 ⎯ ⎯ cycle *1: Ta = + 25 °C, Vcc = 3.0 V, 10,000 cycles *2: Ta = + 85 °C, Vcc = 2.7 V, 10,000 cycles 35 MB89202 Series ■ EXAMPLE CHARACTERISTICS 1. Power supply current • MB89202/F202 : 4 MHz (when external clock are used) MB89202 Normal operation mode (ICC1 − VCC, ICC2 − VCC) MB89F202 Normal operation mode (ICC1 − VCC, ICC2 − VCC) (FCH = 4 MHz, Ta = +25 ˚C) 4.0 (FCH = 4 MHz, Ta = +25 ˚C) 3.0 2.0 ICC1 (gear : 4 divide) ICC1 (gear : 4 divide) ICC (mA) ICC (mA) 3.0 2.0 1.0 ICC2 (gear : 64 divide) 1.0 ICC2 (gear : 64 divide) 0.0 0.0 1 2 3 4 5 6 1 7 2 3 MB89202 Sleep mode (ICCs1 − VCC, ICCs2 − VCC) 6 7 (FCH = 4 MHz, Ta = +25 ˚C) 1.5 1.0 ICCS1 (gear : 4 divide) ICCS (mA) ICCS (mA) 1.0 ICCS1 (gear : 4 divide) 0.5 0.5 ICCS2 (gear : 64 divide) ICCS2 (gear : 64 divide) 0.0 0.0 1 2 3 4 VCC (V) 36 5 MB89F202 Sleep mode (ICCs1 − VCC, ICCs2 − VCC) (FCH = 4 MHz, Ta = +25 ˚C) 1.5 4 VCC (V) VCC (V) 5 6 7 1 2 3 4 5 VCC (V) 6 7 MB89202 Series • MB89202/F202 : 8 MHz ( when external clock are used) MB89F202 Normal operation mode (ICC1 − VCC, ICC2 − VCC) MB89202 Normal operation mode (ICC1 − VCC, ICC2 − VCC) (FCH = 8 MHz, Ta = +25 ˚C) 8.0 (FCH = 8 MHz, Ta = +25 ˚C) 5.0 4.0 6.0 ICC (mA) 4.0 ICC1 (gear : 4 divide) 3.0 2.0 ICC2 (gear : 64 divide) 2.0 1.0 ICC2 (gear : 64 divide) 0.0 0.0 1 2 3 4 5 6 1 7 2 3 MB89202 Sleep mode (ICCs1 − VCC, ICCs2 − VCC) 5 6 7 MB89F202 Sleep mode (ICCs1 − VCC, ICCs2 − VCC) (FCH = 8 MHz, Ta = +25 ˚C) 2.5 4 VCC (V) VCC (V) (FCH = 8 MHz, Ta = +25 ˚C) 2.0 2.0 1.5 ICCS1 (gear : 4 divide) 1.5 ICCS (mA) ICCS (mA) ICC (mA) ICC1 (gear : 4 divide) 1.0 ICCS1 (gear : 4 divide) 1.0 0.5 0.5 ICCS2 (gear : 64 divide) ICCS2 (gear : 64 divide) 0.0 0.0 1 2 3 4 VCC (V) 5 6 7 1 2 3 4 5 VCC (V) 6 7 37 MB89202 Series • MB89202/F202 : 12.5 MHz (when external clock is used) MB89202 Normal operation mode (ICC1 − VCC, ICC2 − VCC) MB89F202 Normal operation mode (ICC1 − VCC, ICC2 − VCC) (FCH = 12.5 MHz, Ta = +25 ˚C) 10.0 (FCH = 12.5 MHz, Ta = +25 ˚C) 5.0 9.0 4.0 8.0 ICC1 (gear : 4 divide) ICC1 (gear : 4 divide) 6.0 ICC (mA) ICC (mA) 7.0 5.0 3.0 2.0 4.0 3.0 1.0 2.0 1.0 ICC2 (gear : 64 divide) ICC2 (gear : 64 divide) 0.0 0.0 1 2 3 4 5 VCC (V) 6 1 7 2 4 VCC (V) 5 6 7 MB89F202 Sleep mode (ICCs1 − VCC, ICCs2 − VCC) MB89202 Sleep mode (ICCs1 − VCC, ICCs2 − VCC) (FCH = 12.5 MHz, Ta = +25 ˚C) 3.0 3 (FCH = 12.5 MHz, Ta = +25 ˚C) 2.0 ICCS1 (gear : 4 divide) 2.5 1.5 ICCS1 (gear : 4 divide) ICCs (mA) ICCs (mA) 2.0 1.5 1.0 ICCS2 (gear : 64 divide) 1.0 0.5 0.5 ICCS2 (gear : 64 divide) 0.0 0.0 1 2 3 4 VCC (V) 38 5 6 7 1 2 3 4 5 VCC (V) 6 7 MB89202 Series • MB89202/F202 : 12.5 MHz (when external clock is used) MB89202 Stop mode (ICCH − Ta) MB89F202 Stop mode (ICCH − Ta) 4.0 3.5 3.5 3.0 3.0 2.5 2.5 ICCH (µA) ICCH (µA) (FCH = 12.5 MHz, VCC = 5.5 V) 4.0 2.0 (FCH = 12.5 MHz, VCC = 5.5 V) 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0.0 0.0 -40 -15 10 Ta ( °C) 35 60 85 -40 -15 10 35 60 85 Ta ( °C) 39 MB89202 Series 2. “L” level output voltage MB89202 VOL vs. IOL1 MB89202 VOL vs. IOL2 VCC = 2.0 V 0.6 VCC = 2.0 V 0.6 0.5 0.5 VCC = 2.5 V VCC = 2.5 V 0.4 VCC = 3.0 V VOL (V) VOL (V) 0.4 VCC = 3.5 V VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V VCC = 6.0 V 0.3 VCC = 3.0 V VCC = 3.5 V VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V VCC = 6.0 V 0.3 0.2 0.2 0.1 0.1 0.0 0.0 1 2 3 4 5 4 6 6 8 3. “H” level output voltage MB89202 (VCC − VOH) vs. IOH VCC = 2.0 V 0.8 0.7 VCC = 2.5 V 0.6 VCC − VOH (V) 12 IOL2 (mA) IOL1 (mA) 0.5 VCC = 3.0 V 0.4 VCC = 3.5 V VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V VCC = 6.0 V 0.3 0.2 0.1 0.0 −1 −2 −3 −4 IOH (mA) 40 10 −5 −6 14 16 MB89202 Series ■ MASK OPTIONS No. Part number MB89202 Specifying procedure Specify when ordering masking MB89F202 MB89V201 Specify by part number 1 Selection of initial value of main clock oscillation settling time* (with FCH = 12.5 MHz) 01 : 214/FCH (Approx.1.31 ms) 10 : 217/FCH (Approx.10.5 ms) 11 : 218/FCH (Approx.21.0 ms) Selectable Fixed to 218/FCH Fixed to 218/FCH 2 Reset pin output With reset output Without reset output Selectable With reset output With reset output 3 Power on reset selection With power on reset Without power on reset Selectable With power on reset With power on reset FCH : Main clock oscillation frequency * : Initial value to which the oscillation settling time bit (SYCC : WT1, WT0) in the system clock control register is set Note • Notes on selecting mask option Please select “With reset output” by the mask option when power-on reset is generated at the power supply ON, and the device is used without inputting external reset. ■ ORDERING INFORMATION Part number MB89202P-SH MB89F202P-SH MB89202PFV MB89F202PFV MB89V201PFV Package Remarks 32-pin plastic SH-DIP (DIP-32P-M06) 34-pin plastic SSOP (FPT-34P-M03) 64-pin plastic LQFP (FPT-64P-M03) 41 MB89202 Series ■ PACKAGE DIMENSIONS 32-pin plastic SH-DIP (DIP-32P-M06) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. +0.20 *28.00 –0.30 1.102 +.008 –.012 INDEX *8.89±0.25 (.350±.010) 1.02 +0.30 –0.20 +.012 .040 –.008 +0.70 4.70 –0.20 0.51(.020) MIN. +.028 .185 –.008 3.30 .130 +0.20 –0.30 +.008 –.012 +0.03 0.27 –0.07 +.001 .011 –.003 1.27(.050) MAX. C 2003 FUJITSU LIMITED D32018S-c-1-1 1.778(.070) 0.48 .019 +0.08 –0.12 +.003 –.005 0.25(.010) M 10.16(.400) 0~15˚ Dimensions in mm (inches). Note: The values in parentheses are reference values (Continued) 42 MB89202 Series (Continued) 34-pin plastic SSOP (FPT-34P-M03) Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max). Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. *1 11.00±0.10(.433±.004) 34 0.17±0.03 (.007±.001) 18 *2 6.10±0.10 (.240±.004) INDEX Details of "A" part 8.10±0.20 (.319±.008) +0.20 1.25 –0.10 +.008 .049 –.004 (Mounting height) 0.25(.010) 1 0~8˚ 17 0.65(.0265) 0.24 .009 +0.08 –0.07 +.003 –.003 "A" 0.10(.004) M 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.10±0.10 (.004±.004) (Stand off) 0.10(.004) C 2003 FUJITSU LIMITED F34003S-c-2-3 Dimensions in mm (inches). Note: The values in parentheses are reference values 43 MB89202 Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0503 © 2005 FUJITSU LIMITED Printed in Japan