Sony CXP87240A Cmos 8-bit single chip microcomputer Datasheet

CXP87240A/87248A
CMOS 8-bit Single Chip Microcomputer
Description
The CXP87240A/87248A is a CMOS 8-bit microcomputer which consists of A/D converter, serial
interface, timer/counter, time base timer, vector
interruption, high precision timing pattern generation
circuit, PWM generator, PWM for tuner, VISS/VASS
circuit, 32kHz timer/event counter, remote control
receiving circuit, general purpose prescaler, HSYNC
counter, VCR vertical sync separation circuit and the
measuring circuit which measure signals of capstan
FG and drum FG/PG and other servo systems, as
well as basic configurations like 8-bit CPU, ROM,
RAM and I/O port. They are integrated into a single
chip.
Also CXP87240A/87248A provides sleep/stop
function which enables to lower power consumption
and ultra-low speed instruction mode in 32kHz
operation.
100 pin QFP (PIastic)
100 pin LQFP (PIastic)
Structure
Silicon gate CMOS IC
Features
• A wide instruction set (213 instructions) which cover various types of data
— 16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation instruction
• Minimum instruction cycle
During operation 333ns/12MHz (3.0 to 5.5V)
During operation 250ns/16MHz (4.5 to 5.5V)
During operation 122µs/32kHz
• Incorporated ROM capacity
40Kbytes (CXP87240A), 48Kbytes (CXP87248A)
• Incorporated RAM capacity
1376bytes
• Peripheral functions
— A/D converter
8-bit, 12-channel, successive approximation system
(Conversion time 20.0µs/16MHz)
— Serial interface
Incorporated buffer RAM (1 to 32 bytes auto transfer) 1-channel
Incorporated 8-bit and 8-stage FIFO
(1 to 8 bytes auto transfer) 1-channel
— Timer
8-bit timer, 8-bit timer/counter, 19-bit time base timer,
32kHz timer/counter
— High precision timing pattern generator PPG 19-pin 32-stage programmable
RTG 5-pin 2-channel
— PWM/DA gate output
PWM 12-bit, 2-channel (Repetitive frequency 62kHz/16MHz)
DA gate pulse output 13-bit, 4-channel
— Servo input control
Capstan FG, Drum FG/PG, CTL input
— VSYNC separator
— FRC capture unit
Incorporated 26-bit and 8-stage FIFO
— PWM output
14-bit, 1-channel
— VISS/VASS circuit
Pulse duty auto detection circuit
— Remote control receiving circuit
8-bit pulse measuring counter, 6-stage FIFO
— General purpose prescaler
7-bit (SYNC1 input frequency divided, FRC capture possible)
— HSYNC counter
12-bit event counter (counts the SYNC1 input.)
• Interruption
22 factors, 15 vectors, multi-interruption possible
• Standby mode
SLEEP/STOP
• Package
100-pin plastic QFP/LQFP
• Piggyback/evaluation chip
CXP87200A 100-pin ceramic QFP/LQFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E94833-ST
AVDD
FIFO
SERIAL
INTERFACE UNIT
(CH1)
PI3/ADJ
PE1/HCOUT
PE2/PWM0
PE4/DAA0
PE6/DAB0
PE3/PWM1
PE5/DAA1
PE7/DAB1
PI2/PWM
PI1/RMC
PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL
PG6/EXI0
PG7/EXI1
2
HSYNC COUNTER
PROGRAMMABLE PRESCALER
12 BIT PWM GENERATOR CH1
12 BIT PWM GENERATOR CH0
14 BIT PWM GENERATOR
VISS/VASS
FIFO
SERVO INPUT
CONTROL
REMOCON INPUT
CTL
DRUM
CAPSTAN
VSYNC SEPARATOR
PG4/SYNC0
PG5/SYNC1
8 BIT TIMER/COUNTER 0
RAM
SERIAL
INTERFACE UNIT
(CH0)
A/D CONVERTER
4
2
2
3
2
2
2
PE0/INT0
NMI
PI4/INT1/NMI
PE1/INT2
2
32kHz
TIMER/COUNTER
PRESCALER/
TIME BASE TIMER
RAM
1376 BYTES
1
CH
REALTIME
PULSE
GENERATOR
CH0
RST
MP
VDD
Vss
CLOCK
GENERATOR/
SYSTEM CONTROL
5
RAM
FIFO
ROM
40K/48K BYTES
SPC700
CPU CORE
AA
19
PROGRAMMABLE
PATTERN
GENERATOR
FRC
CAPTURE UNIT
INTERRUPT CONTROLLER
AVREF
8 BIT TIMER 1
12
AVss
PI3/TO/DDO
PE1/EC
PI7/SI1
PI6/SO1
PI5/SCK1
CS0
SI0
SO0
SCK0
AN0 to AN3
PF0/AN4
to
PF7/AN11
TEX
TX
PA0/PPO0
to
PC2/PPO18
PC0 to PC7
8
8
PG0 to PG7
PH0 to PH7
8
8
8
PJ0 to PJ7
PI1 to PI7
PF4 to PF7
4
7
PF0 to PF3
PE2 to PE7
PE0 to PE1
PE0/CKOUT
4
6
2
PB0 to PB7
8
PD0 to PD7
PA0 to PA7
8
PORT B
EXTAL
XTAL
PC3/RTO3
to
PC7/RTO7
PORT A
PORT C
PORT D
PORT E
PORT F
PORT G
PORT H
PORT I
–2–
PORT J
Block Diagram
CXP87240A/87248A
CXP87240A/87248A
PI5/SCK1
PI4/INT1/NMI
PI3/TO/DDO/ADJ
PI2/PWM
PI1/RMC
TEX
TX
VDD
VSS
NC
PA7/PPO7
PA6/PPO6
PA5/PPO5
PA4/PPO4
PA3/PPO3
PA2/PPO2
PA1/PPO1
PA0/PPO0
PB7/PPO15
PB6/PPO14
Pin Configuration 1 (Top View) 100-pin QFP package
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
PB5/PPO13
1
80
PI6/SO1
PB4/PPO12
2
79
PI7/SI1
PB3/PPO11
3
78
PE0/INT0/CKOUT
PB2/PPO10
4
77
PE1/EC/INT2/HCOUT
PB1/PPO9
5
76
PE2/PWM0
PB0/PPO8
6
75
PE3/PWM1
PC7/RTO7
7
74
PE4/DAA0
PC6/RTO6
8
73
PE5/DAA1
PC5/RTO5
9
72
PE6/DAB0
PC4/RTO4
10
71
PE7/DAB1
PC3/RTO3
11
70
PG0/CFG
PC2/PPO18
12
69
PG1/DFG
PC1/PPO17
13
68
PG2/DPG
PC0/PPO16
14
67
PG3/PBCTL
PJ7
15
66
PG4/SYNC0
PJ6
16
65
PG5/SYNC1
PJ5
17
64
PG6/EXI0
PJ4
18
63
PG7/EXI1
PJ3
19
62
AN0
PJ2
20
61
AN1
PJ1
21
60
AN2
PJ0
22
59
AN3
PD7
23
58
PF0/AN4
PD6
24
57
PF1/AN5
PD5
25
56
PF2/AN6
PD4
26
55
PF3/AN7
PD3
27
54
AVDD
PD2
28
53
AVREF
PD1
29
52
AVSS
PD0
30
51
PF4/AN8
PF5/AN9
PF6/AN10
PF7/AN11
SCK0
SO0
SI0
CS0
EXTAL
XTAL
VSS
RST
MP
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note) 1. NC (Pin 90) is always connected to VDD.
2. Vss (Pins 41 and 88) are both connected to GND.
–3–
CXP87240A/87248A
PE0/INT0/CKOUT
PI7/SI1
PI6/SO1
PI5/SCK1
PI4/INT1/NMI
PI3/TO/DDO/ADJ
PI2/PWM
PI1/RMC
TEX
TX
VDD
VSS
NC
PA7/PPO7
PA6/PPO6
PA5/PPO5
PA4/PPO4
PA3/PPO3
PA2/PPO2
PA1/PPO1
PA0/PPO0
PB7/PPO15
PB6/PPO14
PB5/PPO13
PB4/PPO12
Pin Configuration 2 (Top View) 100-pin LQFP package
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PB3/PPO11
1
75
PE1/EC/INT2/HCOUT
PB2/PPO10
2
74
PE2/PWM0
PB1/PPO9
3
73
PE3/PWM1
PB0/PPO8
4
72
PE4/DAA0
PC7/RTO7
5
71
PE5/DAA1
PC6/RTO6
6
70
PE6/DAB0
PC5/RTO5
7
69
PE7/DAB1
PC4/RTO4
8
68
PG0/CFG
PC3/RTO3
9
67
PG1/DFG
PC2/PPO18
10
66
PG2/DPG
PC1/PPO17
11
65
PG3/PBCTL
PC0/PPO16
12
64
PG4/SYNC0
PJ7
13
63
PG5/SYNC1
PJ6
14
62
PG6/EXI0
PJ5
15
61
PG7/EXI1
PJ4
16
60
AN0
PJ3
17
59
AN1
PJ2
18
58
AN2
PJ1
19
57
AN3
PJ0
20
56
PF0/AN4
PD7
21
55
PF1/AN5
PD6
22
54
PF2/AN6
PD5
23
53
PF3/AN7
PD4
24
52
AVDD
PD3
25
51
AVREF
AVSS
PF4/AN8
PF5/AN9
PF6/AN10
PF7/AN11
SCK0
SO0
SI0
CS0
EXTAL
XTAL
VSS
RST
MP
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
PD0
PD1
PD2
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note) 1. NC (Pin 88) is always connected to VDD.
2. Vss (Pins 39 and 86) are both connected to GND.
–4–
CXP87240A/87248A
Pin Description
Symbol
I/O
Description
Output/
Real time
output
(Port A)
8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)
PB0/PPO8
to
PB7/PPO15
Output/
Real time
output
(Port B)
8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)
Programmable pattern generator (PPG)
output.
Functions as high precision real time
pulse output port.
(19 pins)
PB0 and PB2 can be 3-state controlled
with PPG.
PC0/PPO16
to
PC2/PPO18
I/O/
Real time
output
PC3/RTO3
to
PC7/RTO7
I/O/
Real time
output
(Port C)
8-bit I/O port, enables to
specify I/O by bit unit.
Data is gated with PPO or
RTO contents by OR-gate
and they are output.
(8 pins)
Real time pulse generator (RTG) output.
Functions as high precision real time
pulse output port. (5 pins)
PA0/PPO0
to
PA7/PPO7
PD0 to PD7
PE0/INT0/
CKOUT
I/O
(Port D)
8-bit I/O port. Enable to specify I/O by 4-bit unit.
Enables to drive 12mA sink current.
(8 pins)
Input pin to request external interruption.
Active when falling edge.
Input/Input/Output
(Port E)
8-bit port.
Lower 2 bits
are input
pins and
upper 6 bits
are output
pins.
(8 pins)
PC3 can be 3-state controlled with RTG.
System clock frequency division output.
External event Input pin to request
Coincidence signal
external interruption.
input pin for
output pin for
timer/counter. Active when falling edge. HSYNC counter.
PE1/EC/INT2/
HCOUT
Input/Input/Input/
Output
PE2/PWM0
Output/Output
PE3/PWM1
Output/Output
PE4/DAA0
Output/Output
PE5/DAA1
Output/Output
PE6/DAB0
Output/Output
PE7/DAB1
Output/Output
AN0 to AN3
Input
Analog input pins to A/D converter. (12 pins)
PF0/AN4
to
PF3/AN7
Input/Input
PF4/AN8
to
PF7/AN11
Output/Input
(Port F)
Lower 4 bits are input port and upper 4 bits are output port.
Lower 4 bits also serve as standby release input pin.
(8 pins)
SCK0
I/O
Serial clock (CH0) I/O pin.
SO0
Ouput
Serial data (CH0) output pin.
SI0
Input
Serial data (CH0) input pin.
CS0
Input
Serial chip select (CH0) input pin.
PWM output pins.
(2 pins)
DA gate pulse output pins.
(4 pins)
–5–
CXP87240A/87248A
Symbol
I/O
Description
PG0/CFG
Input/Input
Capstan FG input pin.
PG1/DFG
Input/Input
Drum FG input pin.
PG2/DPG
Input/Input
Drum PG input pin.
PG3/PBCTL
Input/Input
PG4/SYNC0
Input/Input
PG5/SYNC1
Input/Input
PG6/EXI0
Input/Input
PG7/EXI1
Input/Input
(Port G)
8-bit input port.
(8 pins)
Playback CTL pulse input pin.
External event input pin of timer/counter.
Composite sync signal input pin.
External input pin to FRC capture unit.
(Port H)
8-bit output port ; Medium withstand voltage (12V) and high current
(12mA), N-ch open drain output.
(8 pins)
PH0 to PH7
Output
PI1/RMC
I/O/Input
Remote control receiving circuit input pin.
PI2/PWM
I/O/Output
14-bit PWM output pin.
PI3/TO/
DDO/ADJ
I/O/Output/
Output/Output
PI4/INT1/
NMI
I/O/Input/Input
PI5/SCK1
I/O/I/O
PI6/SO1
I/O/Output
Serial data (CH1) output pin.
PI7/SI1
I/O/Input
Serial data (CH1) input pin.
PJ0 to PJ7
I/O
EXTAL
Input
XTAL
Output
TEX
Input
TX
Output
Connecting pin of crystal oscillator for 32kHz timer clock. When used
as event counter, input to TEX pin and leave TX pin open. (Feedback
resistor is not removed.)
RST
Input
System reset pin of active "L" level.
MP
Input
Microprocessor mode input pin. Always connect to GND.
Timer/counter, CTL duty detection, 32kHz oscillation
adjustment output pin.
Input pin to request external interruption and
non-maskable interruption. Active when falling edge.
Serial clock (CH1) I/O pin.
(Port J)
8-bit I/O port. Function as standby release input can be specified by bit
unit. I/O can be specified by bit unit.
Connecting pin of crystal oscillator for system clock. When supplying
the external clock, input the external clock to EXTAL pin and input
opposite phase clock to XTAL pin.
Positive power supply pin of A/D converter.
AVDD
AVREF
(Port I)
7-bit I/O port.
I/O port can be
specified by bit
unit.
(7 pins)
Input
Reference voltage input pin of A/D converter.
AVss
GND pin of A/D converter.
VDD
Positive power supply pin.
Vss
GND pin. Connect both Vss pins to GND.
–6–
CXP87240A/87248A
Input/Output Circuit Formats for Pins
Pin
When reset
Hi-Z
Circuit format
Port A
Port B
PA0 /PPO0
to
PA7/PPO7
PB4/PPO12
to
PB7/PPO15
AA
AA
AAA
AAA
PPO data
Port A or Port B
Output becomes active from Hi-Z
by data writing to port register.
Data bus
RD
12 pins
PB0 /PPO8
PB2/PPO10
AA
AA
AAA
AAA
AAAA
AAAA
AAAA
AAA
AAA
PPO8 or PPO10
PB0 or PB2 data
RD
Hi-Z
Data bus
2 pins
Output becomes active from Hi-Z
by data writing to port register.
PPO9 or PPO11
PPG control
status register bit 0
3-state control
selection
AA
AA
PPO9 or PPO11
PB1/PPO9
PB3/PPO11
PB1 or PB3 data
Data bus
Output becomes active from Hi-Z
by data writing to port register.
RD
2 pins
–7–
Hi-Z
CXP87240A/87248A
Pin
When reset
Circuit format
Port C
AAA
AAA
AAA
PPO, RTO data
PC0/PPO16
to
PC2/PPO18
PC5/RTO5
to
PC7/RTO7
AA
AA
AA
AA
Input
protection
circuit
Port C data
IP
Port C direction
(Every bit)
Data bus
Hi-Z
RD (Port C)
Data bus
6 pins
RD (Port C direction)
AAA
AAA
AAA
AAAAA
AAAAA
AAAAA
AAA
AAA
AAA
RTO3
PC3 data
PC3 direction
PC3/RTO3
AA
AA
Hi-Z
AA
AA
Hi-Z
Data bus
RD
Data bus
RD
1 pins
RTO4
RTG interruption
control register
bit7
3-state control selection
RTO4
PC4 data
PC4/RTO4
PC4 direction
Data bus
RD
RTO data is OR-gate data of ch0 and ch1.
Data bus
RD
1 pins
–8–
CXP87240A/87248A
Pin
Port D
PD0
to
PD7
When reset
Circuit format
AAAA
AAAA
AAAA
AA
AA
AA
AA
High
current
12mA
Port D data
Hi-Z
IP
Port D direction
(Every 4 bits)
PD0 to 3
PD4 to 7
Data bus
RD (Port D)
8 pins
Port E
AAAA
AAAA AA
AA
Port E/PWM
selection register
bit 0, 1
PE0/INT0/
CKOUT
PS1
PS2
PS3
MPX
Data bus
RD
AA
AA
AA
AA
IP
Hi-Z
Input
protection
circuit
Interruption circuit
1 pin
Port E
From HSYNC
counter
AA
AA
AA
AA
Hi-z control
HCOUT
PE1/EC/INT2/
HCOUT
IP
Data bus
RD (Port E)
1 pin
To interruption circuit/
event counter
–9–
Input
protection
circuit
Hi-Z
CXP87240A/87248A
Pin
AA
AA
AAAA
AA
AAAA
AA
AAAA
When reset
Circuit format
Port E
AA
DA gate output
or PWM output
MPX
Hi-Z control
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
Port E data
Hi-Z
Port/DA output
select
Data bus
RD (Port E)
4 pins
Port E
AA
AA
AAAA
AA
AAAA
AAAA
AA
DA gate output
MPX
Hi-Z control
PE6/DAB0
PE7/DAB1
Port E data
H level
Port/DA output
select
Data bus
2 pins
RD (Port E)
AN0
to
AN3
IP
4 pins
Port F
PF0/AN4
to
PF3/AN7
AAAA
AAAA
Input multiplexer
A/D converter
Input multiplexer
A/D converter
IP
Hi-Z
Data bus
4 pins
Hi-Z
RD (Port F)
– 10 –
CXP87240A/87248A
Pin
When reset
Circuit format
AAA
AA
AAAAAAA AA
AA
AA
AAAA
AAAA
AA
Port F
PF4/AN8
to
PF7/AN11
Port F data
Data bus
IP
RD
(Port F)
4 pins
A/D
converter
Hi-Z
Port/AD select
Input multiplexer
Port G
PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL
PG4/SYNC0
PG5/SYNC1
PG6/EXI0
PG7/EXI1
Schmitt input
Servo input
IP
Data bus
Hi-Z
RD (Port G)
Note) For PG4/SYNC0, PG5/SYNC1, CMOS schmitt input and TTL schmitt
input can be selected with the mask option.
8 pins
AA
AA
Port H
PH0
to
PH7
Medium withstand
voltage 12V
AAAA
Port H data
Data bus
8 pins
Hi-Z
High current
12mA
RD (Port H)
AAAA
AA
AAAA
AAAA
AA
AAAA
AA
AAAA
Port I
Port I function
select
PI2/PWM
PI3/TO/
DDO/ADJ
PI2: From 14-bit PWM
PI3: From timer/counter,
CTL duty detection circuit,
32kHz timer
MPX
Port I data
Port I direction
Data
bus
2 pins
RD (Port I)
– 11 –
AA
AA
AA
IP
Hi-Z
CXP87240A/87248A
AAAA
AAAA
AAAA
Pin
When reset
Circuit format
Port I
AA
AA
AA
Port I data
PI1/RMC
PI4/INT1/NMI
PI7/SI1
Port I direction
IP
Data bus
RD (Port I)
3 pins
Hi-Z
Schmitt input
PI1: To remote control circuit
PI4: To interruption circuit
PI7: To serial CH1
AAAA
AA
AAAA
AAAA
AA
A
AAAA
AA
AAA
A
AAAA AAA
AA
AAA
AAA
AAA
A
AAA
A
AA
A
Port I
Port I function
select
PI5/SCK1
PI6/SO1
From serial CH1
MPX
Port I data
Port I direction
MPX
IP
Note)
PI5 is schmitt input
PI6 is inverter input
Data
bus
2 pins
Hi-Z
RD (Port I)
To serial CH1
Port J
Port J data
PJ0
to
PJ7
Port J direction
IP
Data bus
RD
(Port J)
Hi-Z
Edge detection
Standby release
Data bus
8 pins
RD
CS0
SI0
AA
A
AAA
Schmitt input
IP
2 pins
SO0
1 pin
SO0 from SIO
SO0 output enable
– 12 –
Hi-Z
To SIO
AA
AA
Hi-Z
CXP87240A/87248A
Pin
AA
AA
AA
AA
Internal serial clock
from SIO
SCK0
IP
SCK0 output enable
External serial clock to SIO
EXTAL
XTAL
RST
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA AA
AA
AAA
EXTAL
• Shows the circuit
composition during
oscillation.
IP
• Feedback resistor is
removed during stop.
Oscillation
XTAL
2 pins
2 pins
Hi-Z
Schmitt input
1 pin
TEX
TX
When reset
Circuit format
32kHz
timer counter
TEX
TX
• Shows the circuit
composition during
oscillation.
• Feedback resistor is
removed during 32kHz
oscillation circuit stop
by software.
At this time TEX pin
outputs "L" level and TX
pin outputs "H" level.
IP
Oscillation
Pull-up resistor
Mask option
Schmitt input
OP
L level
IP
1 pin
MP
IP
1 pin
– 13 –
CPU mode
Hi-Z
CXP87240A/87248A
Absolute Maximum Ratings
Item
(Vss=0V)
Symbol
VDD
Supply voltage
AVDD
Rating
Unit
–0.3 to +7.0
AVss to +7.0∗1
V
V
Remarks
V
Input voltage
VIN
–0.3 to +0.3
–0.3 to +7.0∗2
Output voltage
VOUT
–0.3 to +7.0∗2
V
Medium withstand output voltage
VOUTP
–0.3 to +15.0
V
High level output current
IOH
–5
mA
High level total output current
∑IOH
–50
mA
Total of output pins
IOL
15
mA
IOLC
20
mA
Other than high current output
pins: per pin
High current port pin∗3: per pin
Low level total output current
∑IOL
130
mA
Total of output pins
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
Allowable power dissipation
PD
AVSS
Low level output current
V
600
380
mW
PH pin
QFP package type
LQFP package type
∗1 AVDD and VDD should be set to a same voltage.
∗2 VIN and VOUT should not exceed VDD + 0.3V.
∗3 The high current operation transistors are the N-CH transistors of the PD and PH ports.
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
better take place under the recommended operating conditions. Exceeding those conditions may
adversely affect the reliability of the LSI.
– 14 –
CXP87240A/87248A
Recommended Operating Conditions
Item
Supply voltage
Analog power supply
High level
input voltage
Symbol
Min.
Max.
3.0
5.5
Guaranteed range during high speed mode
(1/2 dividing clock) operation
2.7
5.5
Guaranteed range during low speed mode.
(1/16 dividing clock) operation
2.7
5.5
2.5
5.5
3.0
5.5
V
Guaranteed data hold operation range
during STOP
∗1
VIH
0.7VDD
VDD
V
∗2
0.8VDD
VDD
VIHS
V
5.5
V
VIHTS
2.2
5.5
V
VDD
AVDD
VIHEX
Low level
input voltage
∗1
∗2
∗3
∗4
∗5
∗6
∗7
∗8
∗9
Remarks
Guaranteed operation range by TEX clock
VDD – 0.4 VDD + 0.3
V
VDD – 0.2 VDD + 0.2
V
CMOS schmitt input∗3 and PE0/INT0 pin
CMOS schmitt input∗7
TTL schmitt input∗4
EXTAL pin∗5, ∗8 TEX pin∗6, ∗8
0.3VDD
V
EXTAL pin∗5, ∗9 TEX pin∗6, ∗9
∗2, ∗8
0.2VDD
V
∗2, ∗9
0
0.2VDD
V
0
0.8
V
–0.3
0.4
V
–0.3
0.2
V
–20
+75
°C
0
VILS
VILTS
Topr
Unit
V
VIL
VILEX
Operating temperature
(Vss = 0V)
CMOS schmitt input∗3 and PE0/INT0 pin
TTL schmitt input∗4
EXTAL pin∗5, ∗8 TEX pin∗6, ∗8
EXTAL pin∗5, ∗9 TEX pin∗6, ∗9
AVDD and VDD should be set to a same voltage.
Normal input port (each pin of PC, PD, PF0 to PF3, PG, PI and PJ), MP pin.
Each pin of SCK0, RST, PE1/EC/INT2, PI1/RMC, PI4/INT1/NMI, PI5/SCK1 and PI7/SI1.
Each pin of PG4 and PG5 (When TTL schmitt input is selected with mask option)
It specifies only when the external clock is input.
It specifies only when the external event count clock is input.
Each pin of CS0, SI0, and PG (For PG4 and PG5, when CMOS schmitt input is selected with mask option.)
When the range of supply voltage (VDD) is within 4.5 to 5.5V.
When the range of supply voltage (VDD) is within 3.0 to 3.6V.
– 15 –
CXP87240A/87248A
Electrical Characteristics
DC Characteristics
Supply Voltage (VDD) 4.5 to 5.5V
Item
High level
output voltage
Low level
output voltage
Symbol
VOH
VOL
Pins
PA to PD,
PE2 to PE7,
PF4 to PF7,
PH (VOL only)
PI1 to PI7
PJ, SO0, SCK0
PD, PH
IIHE
IILE
Input current
EXTAL
IIHT
IILT
(Ta = –20 to +75°C, Vss = 0V)
TEX
Conditions
Min.
Typ.
Max.
Unit
VDD = 4.5V, IOH = –0.5mA
4.0
V
VDD = 4.5V, IOH = –1.2mA
3.5
V
VDD = 4.5V, IOL = 1.8mA
0.4
V
VDD = 4.5V, IOL = 3.6mA
0.6
V
VDD = 4.5V, IOL = 12.0mA
1.5
V
VDD = 5.5V, VIH = 5.5V
0.5
40
µA
VDD = 5.5V, VIL = 0.4V
–0.5
–40
µA
VDD = 5.5V, VIH = 5.5V
0.1
10
µA
–0.1
–10
µA
–1.5
–400
µA
IILR
RST∗1
VDD = 5.5V,
VIL = 0.4V
I/O leakage
current
IIZ
PA to PG,
PI, PJ, MP
AN0 to AN3,
CS0, SI0, SO0
SCK0, RST∗1
VDD=5.5V,
VI=0, 5.5V
±10
µA
Open drain
output leakage
current (N-CH
Tr OFF in state)
ILOH
PH
VDD = 5.5V
VOH = 12V
50
µA
28
45
mA
1.7
8
mA
40
100
µA
10
30
µA
10
µA
20
pF
16MHz crystal oscillation (C1 = C2 = 15pF)
IDD1
VDD = 5V ± 0.5V∗3
SLEEP mode
IDDS1
VDD = 5V ± 0.5V
Supply
current∗2
IDD2
IDDS2
32kHz crystal oscillation (C1 = C2 = 47pF)
VDD
VDD = 3V ± 0.3V
SLEEP mode
VDD = 3V ± 0.3V
IDDS3
STOP mode
(EXTAL and TEX pins oscillation stop)
VDD = 5V ± 0.5V
Input capacity
CIN
Other than VDD,
Clock 1MHz
Vss, AVDD, and
0V other than the measured pins
AVss
10
∗1 RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current
when non-resistor is selected.
∗2 When entire output pins are open.
∗3 When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to "00" and
operating in high speed mode (1/2 dividing clock).
– 16 –
CXP87240A/87248A
Supply Voltage (VDD) 3.0 to 3.6V
Item
High level
output voltage
Low level
output voltage
Symbol
VOH
VOL
Pins
PA to PD,
PE2 to PE7,
PF4 to PF7,
PH (VOL only)
PI1 to PI7
PJ, SO0, SCK0
PD, PH
Typ.
Max.
Unit
VDD = 3.0V, IOH = –0.15mA
2.7
V
VDD = 3.0V, IOH = –0.5mA
2.3
V
VDD = 3.0V, IOL = 1.2mA
0.3
V
VDD = 3.0V, IOL = 1.6mA
0.5
V
VDD = 3.0V, IOL = 5mA
1.0
V
20
µA
VDD = 3.6V, VIL = 0.3V
–0.3
–20
µA
VDD = 3.6V, VIH = 3.6V
0.1
10
µA
–10
µA
IILR
VDD = 3.6V,
VIL = 0.3V
–0.1
RST∗1
–0.9
–200
µA
IIZ
PA to PG,
PI, PJ, MP
AN0 to AN3,
CS0, SI0, SO0
SCK0, RST∗1
VDD = 3.6V,
VI = 0, 3.6V
±10
µA
PH
VDD = 3.6V,
VOH = 12V
50
µA
13
25
mA
0.8
2.5
mA
10
µA
20
pF
EXTAL
IIHT
IILT
Open drain
output leakage ILOH
current
TEX
12MHz crystal oscillation (C1 = C2 = 15pF)
IDD1
Supply
current∗2
Min.
0.3
IILE
I/O leakage
current
Conditions
VDD = 3.6V, VIH = 3.6V
IIHE
Input current
(Ta = –20 to +75°C, Vss = 0V)
IDDS1
IDDS3
VDD = 3.3V ± 0.3V∗3
SLEEP mode
VDD
VDD = 3.3V ± 0.3V
STOP mode
(EXTAL and TEX pins oscillation stop)
VDD = 3.3V ± 0.3V
Input
capacity
CIN
Clock 1MHz
Other than VDD,
Vss, AVDD, and AVss 0V other than the measured pins
10
∗1 RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current
when non-resistor is selected.
∗2 When entire output pins are open.
∗3 When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to "00" and
operating in high speed mode (1/2 dividing clock).
– 17 –
CXP87240A/87248A
AC Characteristics
(1) Clock timing
(Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V)
Item
Symbol
System clock frequency
fC
Pins
XTAL
EXTAL
Conditions
Fig. 1,
Fig. 2
tXL,
tXH
VDD = 4.5 to 5.5V
Fig. 1,
XTAL
EXTAL Fig. 2 (External clock drive)
System clock input rise
and fall times
XTAL
Fig. 1, Fig. 2
EXTAL (external clock drive)
Event count clock input rise
and fall times
tCR,
tCF
tEH,
tEL
tER,
tEF
System clock frequency
fC
Event count clock input
pulse width
tTL,
tTH
tTR,
tTF
Event count clock input rise
and fall times
Max.
1
16
1
12
VDD = 4.5 to 5.5V
System clock input
pulse width
Event count clock input
pulse width
Min.
28
ns
tsys × 4∗
Fig. 3
EC
Fig. 3
TEX
TX
Fig. 2 VDD = 2.7 to 5.5V
(32kHz clock spplied condition)
TEX
Fig. 3
TEX
Fig. 3
MHz
37.5
200
EC
Unit
ns
ns
20
ms
32.768
kHz
10
µs
20
ms
∗ tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2
bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Fig. 1. Clock timing
1/fc
VDD – 0.4V
EXTAL
0.4V
tCF
tXH
tXL
tCR
Fig. 2. Clock applied condition
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA AAAA AAAA
Crystal oscillation
Ceramic oscillation
EXTAL
External clock
EXTAL
XTAL
C1
C2
32kHz clock applied condition
crystal oscillation
TEX
XTAL
TX
C1
74HC04
C2
Fig. 3. Event count clock timing
0.8VDD
TEX
EC
0.2VDD
tEH
tEF
tEL
tER
tTH
tTF
tTL
tTR
– 18 –
CXP87240A/87248A
(2) Serial transfer (CH0)
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Symbol
Pins
Conditions
Min.
Max.
Unit
CS ↓ → SCK
delay time
tDCSK
SCK0
Chip select transfer mode
(SCK = output mode)
tsys + 200
ns
CS ↑ → SCK
floating delay time
tDCSKF SCK0
Chip select transfer mode
(SCK = output mode)
tsys + 200
ns
CS ↓ → SO
delay time
tDCSO
SO0
Chip select transfer mode
tsys + 200
ns
CS ↓ → SO
floating delay time
tDCSOF SO0
Chip select transfer mode
tsys + 200
ns
CS
high level width
tWHCS CS0
Chip select transfer mode
SCK
cycle time
tKCY
SCK0
SCK
high and low level widths
tKH
tKL
SCK0
SI input setup time
(against SCK ↑)
tSIK
SI0
SI input hold time
(against SCK ↑)
tKSI
SI0
SCK ↓ → SO delay time
tKSO
SO0
tsys+200
ns
2tsys + 200
ns
8000/fc
ns
Input mode
tsys + 100
ns
Output mode
8000/fc – 100
ns
SCK input mode
–tsys + 100
ns
200
ns
2tsys + 100
ns
100
ns
Input mode
Output mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
2tsys + 200
ns
100
ns
Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Note 2) CS, SCK, SI and SO means each pin of CS → CS0, SCK → SCK0, SI → SI0, and SO → SO0 respectively.
Note 3) The load of SCK output mode and SO output delay time is 50pF + 1TTL.
– 19 –
CXP87240A/87248A
(2) Serial transfer (CH0)
Item
(Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V)
Symbol
Pins
Conditions
Min.
Max.
Unit
CS ↓ → SCK
delay time
tDCSK
SCK0
Chip select transfer mode
(SCK = output mode)
tsys + 250
ns
CS ↑ → SCK
floating delay time
tDCSKF SCK0
Chip select transfer mode
(SCK = output mode)
tsys + 200
ns
CS ↓ → SO
delay time
tDCSO
SO0
Chip select transfer mode
tsys + 250
ns
CS ↓ → SO
floating delay time
tDCSOF SO0
Chip select transfer mode
tsys + 200
ns
CS
high level width
tWHCS CS0
Chip select transfer mode
tsys + 200
ns
SCK
cycle time
Input mode
SCK0
2tsys + 200
ns
tKCY
8000/fc
ns
SCK
high and low level widths
tKH
tKL
Input mode
tsys + 100
ns
SCK0
Output mode
8000/fc – 150
ns
SI input setup time
(against SCK ↑)
SCK input mode
SI0
–tsys + 100
ns
tSIK
200
ns
SI input hold time
(against SCK ↑)
SI0
2tsys + 100
ns
tKSI
100
ns
SCK ↓ → SO delay time
tKSO
SO0
Output mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
2tsys + 250
ns
125
ns
Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Note 2) CS, SCK, SI and SO means each pin of CS → CS0, SCK → SCK0, SI → SI0, and SO → SO0 respectively.
Note 3) The load of SCK output mode and SO output delay time is 50pF.
– 20 –
CXP87240A/87248A
Fig. 4. Serial transfer timing (CH0)
tWHCS
CS0
0.8VDD
0.2VDD
tKCY
tDCSK
tKL
tDCSKF
tKH
0.8VDD
0.8VDD
SCK0
0.2VDD
tSIK
tKSI
0.8VDD
SI0
Input data
0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD
SO0
Output data
0.2VDD
– 21 –
CXP87240A/87248A
Serial transfer (CH1) (SIO mode)
Item
Symbol
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Pins
Conditions
tKCY
SCK1
SCK1 high and low
level widths
tKH
tKL
SCK1
SI1 input setup time
(against SCK1 ↑)
tSIK
SI1
SI1 input hold time
(against SCK1 ↑)
tKSI
SI1
SCK1 ↓ → SO1 delay time
tKSO
SO1
Max.
Unit
2tsys + 200
ns
Output mode
16000/fc
ns
Input mode
tsys+100
ns
8000/fc – 50
ns
SCK1 input mode
100
ns
SCK1 output mode
200
ns
tsys + 200
ns
100
ns
Input mode
SCK1 cycle time
Min.
Output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
tsys + 200
ns
100
ns
Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.
Serial transfer (CH1) (SIO mode)
Item
Symbol
(Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V)
Pins
SCK1 cycle time
tKCY
SCK1
SCK1 high and low
level widths
tKH
tKL
SCK1
SI1 input setup time
(against SCK1 ↑)
tSIK
SI1
SI1 input hold time
(against SCK1 ↑)
tKSI
SI1
SCK1 ↓ → SO1 delay time
tKSO
SO1
Conditions
Min.
Max.
Unit
2tsys + 200
ns
16000/fc
ns
tsys + 100
ns
8000/fc – 150
ns
SCK1 input mode
100
ns
SCK1 output mode
200
ns
tsys + 200
ns
100
ns
Input mode
Output mode
Input mode
Output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
tsys + 250
ns
125
ns
Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF.
– 22 –
CXP87240A/87248A
Fig. 5. Serial transfer CH1 timing (SIO mode)
tKCY
tKL
tKH
SCK1
0.8VDD
0.2VDD
tSIK
tKSI
0.8VDD
SI1
Input data
0.2VDD
tKSO
0.8VDD
SO1
Output data
0.2VDD
– 23 –
CXP87240A/87248A
Serial transfer (CH1) (Special mode)
Item
Symbol
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Pins
Conditions
Min.
Typ.
Max.
Unit
SO1 cycle time
tLCY
SO1
SI1
SI1 data setup time
tLSU
tLHD
SI1
2
µs
SI1
2
µs
SI1 data hold time
Note 1)
104
Note 1)
µs
tLCY specifies only serial mode register (CH1) (SIOM1: Address 01FAH) lower 2 bits (SO1 clock
selection) has been set at 104µs.
Note 2) The load of SO1 pin is 50pF + 1TTL.
(Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V)
Serial transfer (CH1) (Special mode)
Item
Symbol
Pins
Conditions
Min.
Typ.
Max.
Unit
SO1 cycle time
tLCY
SO1
SI1
SI1 data setup time
tLSU
tLHD
SI1
2
µs
SI1
2
µs
SI1 data hold time
104
Note 1)
µs
tLCY specifies only serial mode register (CH1) (SIOM1: Address 01FAH) lower 2 bits (SO1 clock
selection) has been set at 104µs.
Note 2) The load of SO1 pin is 50pF.
Note 1)
Fig. 6. Serial transfer CH1 timing (Special mode)
tLCY
SO1
tLCY
Start bit
0.5VDD
Output data bit
tLCY/2
tLSU
tLHD
input
data bit
SI1
– 24 –
0.8VDD
0.2VDD
CXP87240A/87248A
(3) General purpose prescaler
Item
(Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V)
Symbol
Pins
External clock input frequency
fPCK
SYNC1
External clock input pulse width
tWH, tWL
tR,
tF
SYNC1
External clock input
rise and fall times
Conditions
Min.
SYNC1
Unit
12
MHz
ns
200
1/fPCK
SYNC1
Max.
33
Fig. 7. General purpose prescaler timing
tWH
Typ.
tF
0.8VDD
0.5VDD
0.2VDD
tWL
– 25 –
tR
ns
CXP87240A/87248A
(4) HSYNC counter
(Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V)
Item
Symbol
External clock input frequency
fHCK
Conditions
Min.
Typ.
SYNC1
tWH, tWL
tR
External clock input rise/fall time
tF
tHLH
HCOUT output delay time
(against SYNC1 ↑)
tHHL
tTLH
HCOUT output rise/fall time
tTHL
External clock input pulse width
Note 1)
Pins
SYNC1
Max.
unit
12
MHz
33
ns
SYNC1
200
ns
tsys + 130 tsys + 220 ns
tsys + 90 tsys + 150 ns
External clock input
HCOUT SYNC1 tR = tF = 6ns
External clock input
HCOUT SYNC1 tR = tF = 6ns
100
280
ns
30
70
ns
tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)
Note 2) The load of HCOUT pin is 50pF.
Fig. 8. HSYNC counter timing
1/fHCK
tWH
SYNC1
tF
0.8VDD
0.5VDD
0.2VDD
tWL
tHLH
tR
tHHL
0.8VDD
HCOUT
0.5VDD
0.2VDD
tTLH
tTHL
– 26 –
CXP87240A/87248A
(5) A/D converter characteristics
Item
(Ta = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V)
Symbol
Pins
Conditions
Min.
Typ.
Max.
Unit
8
Bits
±1
LSB
±2
LSB
Resolution
Ta = 25°C
VDD = AVDD = AVREF = 5.0V
VSS = AVSS = 0V
Linearity error
Absolute error
Conversion time
Sampling time
160/fADC∗
12/fADC∗
tCONV
tSAMP
Reference input voltage VREF
Analog input voltage
VIAN
IREFS
µs
VDD = AVDD = 4.5 to 5.5V AVDD – 0.5
AVREF
AVDD
0
AN0 to AN11
IREF
AVREF current
µs
V
0.6
Operating mode
SLEEP mode
STOP mode
32kHz operating mode
AVREF
V
1.0
mA
10
µA
(Ta = –20 to +75°C, VDD = AVDD = 3.0 to 3.6V, AVREF = 2.7 to AVDD, Vss = AVSS = 0V)
Item
Symbol
Pins
Conditions
Min.
Typ.
Max.
Unit
8
Bits
±1
LSB
±2
LSB
Resolution
Ta = 25°C
VDD = AVDD = AVREF =
5.0V
Linearity error
Absolute error
Conversion time
Sampling time
160/fADC∗
12/fADC∗
tCONV
tSAMP
Reference input voltage VREF
Analog input voltage
VIAN
µs
VDD = AVDD = 3.0 to 3.6V AVDD – 0.3
AVREF
Operating mode
SLEEP mode
STOP mode
32kHz operating mode
AVREF
IREFS
AVDD
0
AN0 to AN11
IREF
AVREF current
µs
V
0.4
0.7
mA
10
µA
Fig. 9. Definitions of A/D converter terms
Digital conversion value
FFH
FEH
∗ The value of fADC is as follows by selecting ADC
operation clock (MSC: Address 01FFH bit 0).
When PS2 is selected, fADC = fc/2
When PS1 is selected, fADC = fc
Linearity error
01H
00H
VFT
VZT
Analog input
– 27 –
V
CXP87240A/87248A
(6) Interruption, reset input
Item
(Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V)
Symbol
Pins
Conditions
External interruption
high and low level widths
tIH
tIL
INT0
INT1
INT2
NMI
PJ0 to PJ7
Reset input low level width
tRSL
RST
Min.
Max.
Unit
1
µs
32/fc
µs
Fig. 10. Interruption input timing
INT0
INT1
INT2
NMI
PJ0 to PJ7
(During standby release input)
(Falling edge)
tIH
tIL
0.8VDD
0.2VDD
Fig. 11. Reset input timing
tRSL
RST
0.2VDD
(7) Others
(Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V)
Item
Symbol
tCFH
tCFL
tDFH
DFG input
tDFL
high and low level widths
DPG minimum pulse width tDPW
CFG input
high and low level widths
DPG minimum
removal time
trem
PBCTL input
high and low level widths
tCTH
tCTL
tEIH
tEIL
EXI input
high and low level widths
Note)
Pins
Conditions
Min.
Max.
Unit
CFG
tFRC × 24 + 200
ns
DFG
tFRC × 16 + 200
ns
DPG
tFRC × 8 + 200
ns
DPG
tFRC × 16 + 200
ns
PBCTL
tsys = 2000/fc
tFRC × 8+200 + tsys
ns
EXI0
EXI1
tsys = 2000/fc
tFRC × 8+200 + tsys
ns
tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
tFRC = 1000/fc [ns]
– 28 –
CXP87240A/87248A
Fig. 12. Other timings
tCFH
tCFL
0.8VDD
CFG
0.2VDD
tDFH
DFG
tDFL
0.8VDD
0.2VDD
trem
tDPW
trem
0.8VDD
DPG
tCTH
tCTL
0.8VDD
PBCTL
0.2VDD
tEIH
EXI0
EXI1
tEIL
0.8VDD
0.2VDD
– 29 –
CXP87240A/87248A
Supplement
Fig. 13. Recommended oscillation circuit
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
(i)
EXTAL
(ii)
TEX
XTAL
Rd
Manufacturer
Rd
C2
C1
Model
HC-49/U03
fc (MHz)
C1 (pF)
C2 (pF)
10
10
10.00
12.00
5
5
8.00
16 (12)
16 (12)
10.00
16 (12)
16 (12)
12.00
12
12
16.00
12
12
32.768kHz
30
18
16.00
HC-49/U (-S)
KINSEKI LTD.
P3
C2
C1
8.00
RIVER
ELETEC
CO., LTD.
TX
Rd (Ω)
Circuit
example
0
(i)
0
(i)
470K
(ii)
Mask option table
Content
Item
Reset pin pull-up resistor
Input circuit format∗
Non-existent
Existent
C-MOS schmitt
TTL schmitt
∗ In PG4/SYNC0 pin and PG5/SYNC1 pin, the input circuit format can be selected to every pin.
However, TTL shmitt can not be selected when the supply voltage (VDD) ranges 3.0V to 5.5V.
– 30 –
CXP87240A/87248A
Characteristics Curve
IDD vs. VDD
IDD vs. VDD
(fc = 16MHz, Ta = 25°C, Typical)
(fc = 12MHz, Ta = 25°C, Typical)
1/2 dividing mode
1/4 dividing mode
1/2 dividing mode
10.0
10.0
1/4 dividing mode
1/16 dividing mode
5.0
5.0
1.0
0.5
32kHz mode
(instruction)
0.1
(100µA)
32kHz
SLEEP mode
IDD – Supply current [mA]
IDD – Supply current [mA]
1/16 dividing mode
SLEEP mode
SLEEP mode
1.0
0.5
0.1
(100µA)
0.05
(50µA)
0.05
(50µA)
0.01
(10µA)
0.01
(10µA)
3
4
5
6
3
VDD – Supply voltage [V]
5
6
IDD vs. fc
IDD vs. fc
(VDD = 5.0V, Ta = 25°C, Typical)
(VDD = 3.3V, Ta = 25°C, Typical)
30
30
1/2 dividing mode
20
1/4 dividing mode
10
IDD – Supply current [mA]
IDD – Supply current [mA]
4
VDD – Supply voltage [V]
20
1/2 dividing mode
10
1/4 dividing mode
1/16 dividing mode
1/16 dividing mode
SLEEP mode
0
1
5
10
15
0
16
fc – System clock [MHz]
SLEEP mode
1
5
10
fc – System clock [MHz]
– 31 –
15
16
CXP87240A/87248A
Unit: mm
100PIN QFP (PLASTIC)
+ 0.1
0.15 – 0.05
15.8 ± 0.4
+ 0.4
14.0 – 0.01
17.9 ± 0.4
23.9 ± 0.4
+ 0.4
20.0 – 0.1
A
0.65
+ 0.35
2.75 – 0.15
±0.12 M
0° to 15°
DETAIL A
0.8 ± 0.2
(16.3)
0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SOLDER PLATING
SONY CODE
QFP-100P-L01
LEAD TREATMENT
EIAJ CODE
∗QFP100-P-1420-A
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
1.4g
JEDEC CODE
100PIN LQFP (PLASTIC)
16.0 ± 0.2
∗
14.0 ± 0.1
75
51
76
(15.0)
50
0.5 ± 0.2
A
26 (0.22)
100
1
0.5 ± 0.08
+ 0.08
0.18 – 0.03
25
+ 0.2
1.5 – 0.1
+ 0.05
0.127 – 0.02
0.1
0.1 ± 0.1
0° to 10°
0.5 ± 0.2
Package Outline
DETAIL A
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY/PHENOL RESIN
SONY CODE
LQFP-100P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
∗QFP100-P-1414-A
LEAD MATERIAL
42 ALLOY
JEDEC CODE
PACKAGE WEIGHT
– 32 –
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