FUJITSU SEMICONDUCTOR DATA SHEET DS07-12505-3E 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89640 Series MB89643/645/646/647/P647/PV640 ■ DESCRIPTION The MB89640 series has been developed as a general-purpose version of the F2MC*-8L family consisting of proprietary 8-bit, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as dual-clock control system, five operating speed control stages, timers, a PWM timer, serial interface, an A/D converter, a D/A converter, an external interrupt, and a watch prescaler. *: F2MC stands for FUJITSU Flexible Microcontroller. ■ FEATURES • F2MC-8L family CPU core Instruction set optimized for controllers Multiplication and division instructions 16-bit arithmetic operations Test and branch instructions Bit manipulation instructions, etc. (Continued) ■ PACKAGE 80-pin Plastic QFP (FPT-80P-M11) 80-pin Plastic QFP 80-pin Ceramic MQFP (FPT-80P-M06) (MQP-80C-P01) MB89640 Series (Continued) • Six types of timers 8-bit PWM timer: 2 channels (also usable reload timer) 8-bit pulse width counter (continuous measurement capable and applicable to remote control) 16-bit timer/counter 21-bit time-base counter 15-bit watch prescaler • Two 8-bit serial I/O Swichable transfer direction allows communication with various equipment. • 8-bit A/D converter: 8 channels Sense mode function enabling comparison at 12 instructions Activation by external input capable • External interrupt 1, external interrupt 2: 9 channels • 8-bit D/A converter: 2 channels 8-bit R-2R type • Low-power consumption modes (stop mode, sleep mode, watch mode, subclock mode) • Bus interface functions Including hold and ready functions 2 MB89640 Series ■ PRODUCT LINEUP Part number Parameter MB89643 Classification ROM size RAM size CPU functions MB89645 MB89646 MB89P647 One-time evaluation product PROM product for evaluation and development 32 K × 8 bits 8 K × 8 bits 16 K × 8 bits 24 K × 8 bits 32 K × 8 bits (internal mask (internal mask (internal mask (internal mask (internal PROM, programming with ROM) ROM) ROM) ROM) general-purpose programmer) 256 × 8 bits 512 × 8 bits 768 × 8 bits Number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: 32 K × 8 bits (external ROM) 1 K × 8 bits 136 8 bits 1 to 3 bytes 1, 8, 16 bits 0.4 µs/10 MHz to 6.4 µs/10 MHz, or 61.0 µs/32.768 kHz 3.6 µs/10 MHz to 57.6 µs/10 MHz, or 562.5 µs/32.768 kHz Input ports (CMOS): Output ports (CMOS): I/O ports (CMOS): 9 (All also serve as a external interrupt.) 8 (All also serve as a bus control.) 24 (8 ports also serve as peripherals, 16 ports also serve as a bus control.) I/O ports (N-ch open-drain): 8 (All also serve as peripherals.) Output ports (N-ch open-drain): 16 (8 ports also serve as peripherals.) Total: 65 Clock timer 21 bits × 1 (in main clock mode), 15 bits × 1 (at 32.768 kHz) 8-bit PWM timer 8-bit reload timer operation × 2 channels 7/8-bit resolution PWM operation × 2 channels 8-bit PPG operation × 1 channel 8-bit pulse width counter MB89PV640 Piggyback/ Mass production products (mask ROM products) Interrupt processing time: Ports MB89647 8-bit timer operation (overflow output capable) 8-bit reload timer operation (toggled output capable) 8-bit pulse width measurement operation (Continuous measurement capable, measurement of “H” width/“L” width/from ↑ to ↓/from ↓ to ↑ capable) 16-bit timer/ counter 16-bit timer operation 16-bit event counter operation 8-bit serial I/O 8 bits × 2 channels LSB first/MSB first selectability One clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 0.8 µs, 3.2 µs, 12.8 µs) 8-bit A/D converter 8-bit resolution × 8 channels A/D conversion mode (conversion time: 44 instructions) Sense mode (conversion time: 12 instructions) Continuous activation by an external activation or an internal timer capable Reference voltage input (Continued) 3 MB89640 Series (Continued) Part number MB89643 Parameter 8-bit D/A converter MB89645 MB89646 MB89647 MB89P647 MB89PV640 8-bit resolution × 2 channels, R-2R type External interrupt 1, External interrupt 2 9 channels Standby modes Watch mode, subclock mode, sleep mode, and stop mode Process CMOS Operating voltage*1 2.2 V to 6.0 V EPROM for use 2.7 V to 6.0 V MBM27C256A -20TV *1: Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”) ■ PACKAGE AND CORRESPONDING PRODUCTS MB89643 MB89645 MB89646 MB89647 MB89P647 Package MB89PV640 FPT-80P-M11 × FPT-80P-M06 × MQP-80C-P01 : Available × × : Not available Note: For more information about each package, see section “■ External Dimensions.” 4 MB89640 Series ■ DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the piggyback product, verify its differences from the product that will actually be used. Take particular care on the following points: • On the MB89643 register banks 16 to 32 cannot be used. • On the MB89P647, the program area starts from address 8007H but on the MB89PV640 and MB89647 starts from 8000H. (On the MB89P647, addresses 8000H to 8006H comprise the option setting area, option settings can be read by reading these addresses. On the MB89PV640 and MB89647, addresses 8000H to 8006H could also be used as a program ROM. However, do not use these addresses in order to maintain compatibility of the MB89P647.) • The stack area, etc., is set at the upper limit of the RAM. • The external areas are used. 2. Current Consumption • In the case of the MB89PV640, add the current consumed by the EPROM which is connected to the top socket. • When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume more current than the product with a mask ROM. • However, the current consumption in sleep/stop modes is the same. (For more information, see sections “■ Electrical Characteristics” and “■ Example Characteristics.”) 3. Mask Options Functions that can be selected as options and how to designate these options vary by the product. Before using options check section “■ Mask Options.” Take particular care on the following points: • A pull-up resistor cannot be set for P40 to P47 and P50 to P57 on the MB89P647. • For all products, P60 to P67 are available for no pull-up resistor when an A/D converter is used. • For all products, P50 to P57 are available for no pull-up resistor when a D/A converter is used. • Options are fixed on the MB89PV640. 5 P21/HAK P20/BUFC P17/A15 P16/A14 P15/A13 P14/A12 P13/A11 P12/A10 P11/A09 P10/A08 P07/AD7 P06/AD6 P05/AD5 P04/AD4 P03/AD3 P02/AD2 P01/AD1 P00/AD0 P37/PTO1 P36/WTO 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P72/LI2 P73/LI3 P74/LI4 P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 AVSS AVRL AVRH AVCC DAVC P50/DA1 P51/DA2 P52/PWM P53/PTO2 MB89640 Series ■ PIN ASSIGNMENT (Top view) P71/LI1 P70/LI0 P83/INT3 P82/INT2 P81/INT1 P80/INT0 X0A X1A MOD0 MOD1 X0 X1 VSS RST P27/ALE P26/RD P25/WR P24/CLK P23/RDY P22/HRQ 6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 (FPT-80P-M11) P54/BZ P55/SCK2 P56/SO2 P57/SI2 VSS P40 P41 VCC P42 P43 P44 P45 P46 P47 P30/ADST P31/SCK1 P32/SO1 P33/SI1 P34/EC P35/PWC MB89640 Series 101 102 103 104 105 106 107 108 109 93 92 91 90 89 88 87 86 85 110 111 112 81 82 83 84 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Each pin inside the dashed line is for the MB89PV640 only. 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P52/PWM P53/PTO2 P54/BZ P55/SCK2 P56/SO2 P57/SI2 VSS P40 P41 VCC P42 P43 P44 P45 P46 P47 P30/ADST P31/SCK1 P32/SO1 P33/SI1 P34/EC P35/PWC P36/WTO P37/PTO1 P17/A15 P16/A14 P15/A13 P14/A12 P13/A11 P12/A10 P11/A09 P10/A08 P07/AD7 P06/AD6 P05/AD5 P04/AD4 P03/AD3 P02/AD2 P01/AD1 P00/AD0 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P73/LI3 P72/LI2 P71/LI1 P70/LI0 P83/INT3 P82/INT2 P81/INT1 P80/INT0 X0A X1A MOD0 MOD1 X0 X1 VSS RST P27/ALE P26/RD P25/WR P24/CLK P23/RDY P22/HRQ P21/HAK P20/BUFC 100 99 98 97 96 95 94 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 P74/LI4 P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 AVSS AVRL AVRH AVCC DAVC P50/DA1 P51/DA2 (Top view) (FPT-80P-M06) (MQP-80C-P01) • Pin assignment on package top (MB89PV640 only) Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name 81 N.C. 89 A2 97 N.C. 105 OE 82 VPP 90 A1 98 O4 106 N.C. 83 A12 91 A0 99 O5 107 A11 84 A7 92 N.C. 100 O6 108 A9 85 A6 93 O1 101 O7 109 A8 86 A5 94 O2 102 O8 110 A13 87 A4 95 O3 103 CE 111 A14 88 A3 96 VSS 104 A10 112 VCC N.C.: Internally connected. Do not use. 7 MB89640 Series ■ PIN DESCRIPTION Pin no. QFP*2 MQFP*3 11 13 X0 12 14 X1 9 11 MOD0 10 12 MOD1 14 16 38 to 31 Circuit type Function A Main clock crystal oscillator pins (Max. 10 MHz) C Operating mode selection pins Connect directly to VCC or VSS. RST D Reset I/O pin This pin is an N-ch open-drain output type with pull-up resistor, and a hysteresis input type. “L” is output from this pin by an internal reset source. The internal circuit is initialized by the input of “L”. 40 to 33 P00/AD0 to P07/AD7 E General-purpose I/O ports Also serve as multiplex pins of lower address output and data I/O. 30 to 23 32 to 25 P10/A08 to P17/A15 E General-purpose I/O ports Also serve as an upper address output. 22, 21, 18, 15 24, 23, 20, 17 P20/BUFC, P21/HAK, P24/CLK, P27/ALE G General-purpose output-only ports Also serve as a bus control signal output. 20, 19 22, 21 P22/HRQ, P23/RDY E General-purpose output-only ports Also serve as a bus control signal input. 17, 16 19, 18 P25/WR, P26/RD E General-purpose output-only ports Also serve as a bus control signal output. 46 48 P30/ADST F General-purpose I/O port Also serves as an A/D converter external activation. This port is a hysteresis input type. 45 47 P31/SCK1 F General-purpose I/O port Also serves as the clock I/O for the serial I/O 1. This port is a hysteresis input type. 44, 43 46, 45 P32/SO1, P33/SI1 F General-purpose I/O ports Also serve as the data output for the serial I/O 1. These ports are a hysteresis input type. 42 44 P34/EC F General-purpose I/O port Also serves as the external clock input for the 16-bit timer/ counter. This port is a hysteresis input type. *1: FPT-80P-M11 *2: FPT-80P-M06 *3: MQP-80C-P01 8 Pin name QFP*1 (Continued) MB89640 Series (Continued) Pin no. Circuit type Function P35/PWC F General-purpose I/O port Also serves as the measured pulse input for the 8-bit pulse width counter. This port is a hysteresis input type. 42 P36/WTO F General-purpose I/O port Also serves as the toggle output for the 8-bit pulse width counter. This port is a hysteresis input type. 39 41 P37/PTO1 F General-purpose I/O port Also serves as the toggle output for the 1-channel PWM timer. 55, 54, 52 to 47 57, 56, 54 to 49 P40 to P47 L N-ch medium-voltage open-drain output-only ports 64 66 P50/DA1 K N-ch open-drain I/O port Also serves as a D/A channel 1 output. This port is a hysteresis input type. 63 65 P51/DA2 K N-ch open-drain I/O port Also serves as a D/A channel 2 output. This port is a hysteresis input type. 62 64 P52/PWM H N-ch open-drain I/O port Also serves as the PWM output by the two PWM timers. This port is a hysteresis input type. 61 63 P53/PTO2 H N-ch open-drain I/O port Also serves as the toggle output for the 2-channel PWM timer. This port is a hysteresis input type. 60 62 P54/BZ H N-ch open-drain I/O port Also serves as a buzzer output. This port is a hysteresis input type. 59 61 P55/SCK2 H N-ch open-drain I/O port Also serves as the clock I/O for the serial I/O 2. This port is a hysteresis input type. 58 60 P56/SO2 H N-ch open-drain I/O port Also serves as the data output for the serial I/O 2. This port is a hysteresis input type. 57 59 P57/SI2 H N-ch open-drain I/O port Also serves as the data input for the serial I/O 2. This port is a hysteresis input type. 77 to 70 79 to 72 P60/AN0 to P67/AN7 I N-ch open-drain output-only ports Also serve as the analog input for the A/D converter. These ports are a hysteresis input type. 2, 1, 80 to 78 4 to 1, 80 P70/LI0 to P74/LI4 J Input-only ports Also serve as external interrupt 1 input. These ports are a hysteresis input type. QFP*1 QFP*2 MQFP*3 41 43 40 Pin name *1: FPT-80P-M11 *2: FPT-80P-M06 *3: MQP-80C-P01 9 MB89640 Series (Continued) Pin no. QFP*2 MQFP*3 7 9 X0A 8 10 X1A 53 55 13, 56 15, 58 66 68 67, 68 69, 70 65 Circuit type Function B Subclock oscillator pins (32.768 kHz) VCC Power supply pin VSS Power supply (GND) pin AVCC A/D converter power supply pin Use this pin at the same voltage as VCC. AVRH, AVRL A/D converter reference voltage input pins 67 DAVC D/A converter power supply pin Use this pin at the same voltage as VCC. 69 71 AVSS Analog circuit power supply pin Use this pin at the same voltage as VSS. 3 to 6 5 to 8 P83/INT3 to P80/INT0 J Input-only ports Also serve as an external interrupt 2 input. These ports are a hysteresis input type. *1: FPT-80P-M11 *2: FPT-80P-M06 *3: MQP-80C-P01 10 Pin name QFP*1 MB89640 Series • External EPROM pins (MB89PV640 only) Pin no. Pin name I/O Function 82 VPP O “H” level output pin 83 84 85 86 87 88 89 90 91 A12 A7 A6 A5 A4 A3 A2 A1 A0 O Address output pins 93 94 95 O1 O2 O3 I Data input pins 96 VSS O Power supply (GND) pin 98 99 100 101 102 O4 O5 O6 O7 O8 I Data input pins 103 CE O ROM chip enable pin Outputs “H” during standby. 104 A10 O Address output pin 105 OE O ROM output enable pin Outputs “L” at all times. 107 108 109 A11 A9 A8 O Address output pins 110 A13 O 111 A14 O 112 VCC O EPROM power supply pin 81 92 97 106 N.C. — Internally connected pins Be sure to leave them open. 11 MB89640 Series ■ I/O CIRCUIT TYPE Type A Circuit Remarks Main clock • At an oscillation feedback resistor of approximately 1 MΩ/5.0 V X1 X0 Standby control signal B Subclock • At an oscillation feedback resistor of approximately 4.5 MΩ/5.0 V X1A X0A Standby control signal C D R P-ch • At an output pull-up resistor (P-ch) of approximately 50 kΩ/5.0 V • Hysteresis input N-ch E • CMOS output • CMOS input R P-ch P-ch N-ch • Pull-up resistor optional (Continued) 12 MB89640 Series (Continued) Type Circuit Remarks F • CMOS output • Hysteresis input R P-ch P-ch N-ch • Pull-up resistor optional G • CMOS output R P-ch P-ch N-ch • Pull-up resistor optional H • N-ch open-drain output • Hysteresis input R P-ch N-ch • Pull-up resistor optional I • N-ch open-drain output • Analog input R P-ch P-ch N-ch Analog input J • Pull-up resistor optional • Hysteresis input R • Pull-up resistor optional (Continued) 13 MB89640 Series (Continued) Type Circuit Remarks K • N-ch open-drain output • Hysteresis input • Analog output R P-ch P-ch N-ch Analog output Enable L • Pull-up resistor optional • N-ch open-drain output • Medium voltage R P-ch N-ch • Pull-up resistor optional 14 MB89640 Series ■ HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC and AVRH) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. 3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters Connect to be AVCC = DAVC = VCC and AVSS = AVRH = VSS even if the A/D and D/A converters are not in use. 4. Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. 5. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 6. Precautions when Using an External Clock Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode. 15 MB89640 Series ■ PROGRAMMING TO THE EPROM ON THE MB89P647 The MB89P647 is an OTPROM version of the MB89640 series. 1. Features • 32-Kbyte PROM on chip • Options can be set using the EPROM programmer. • Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer) 2. Memory Space Memory space in each mode such as 32-Kbyte PROM, option area is diagrammed below. Address Single chip EPROM mode (Corresponding addresses on the EPROM programmer) 0000H I/O 0080H RAM 0180H Not available 8000H 0000H Not available 8007H Option area 0007H PROM 32 KB FFFFH EPROM 32 KB 7FFFH • Precautions (1) The program area of the MB89P647 is 7 bytes smaller than that of the MB89PV640 and MB89647 to provide an option area. Note this point during program development. (2) During normal operation, the option data is read when the option area is read from the CPU. 3. Programming to the EPROM In EPROM mode, the MB89P647 functions equivalent to the MBM27C256A. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. • Programming procedure (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0007H to 7FFFH (note that addresses 8007H to FFFFH while operating as internal ROM mode assign to 0007H to 7FFFH in EPROM mode). Load option data into addresses 0000H to 0006H of the EPROM programmer. (For information about each corresponding option, see “7. Setting OTPROM Options.”) (3) Program with the EPROM programmer. 16 MB89640 Series 4. Recommended Screening Conditions High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM microcomputer program. Program, verify Aging +150°C, 48 Hrs. Data verification Assembly 5. Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. 6. EPROM Programmer Socket Adapter Package Compatible socket adapter FPT-80P-M06 ROM-80QF-28DP-8L2 FPT-80P-M11 ROM-80QF2-28DP-8L Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760 Note: Depending on the EPROM programmer, inserting a capacitor of about 0.1 µF between VPP and VSS or VCC and VSS can stabilize programming operations. 17 MB89640 Series 7. Setting OTPROM Options The programming procedure is the same as that for the PROM. Options can be set by programming values at the addresses shown on the memory map. The relationship between bits and options is shown on the following bit map: • OTPROM option bit map Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 1 Bit 0 Readable and writable Single/dualclock system 1: Dual clock 2: Single clock Reset pin output 1: Yes 2: No Power-on reset 1: Yes 2: No 00: 24/FCH 01: 217/FCH 10: 214/FCH 11: 218/FCH P06 Pull-up 1: No 0: Yes P05 Pull-up 1: No 0: Yes P04 Pull-up 1: No 0: Yes P03 Pull-up 1: No 0: Yes P02 Pull-up 1: No 0: Yes P01 Pull-up 1: No 0: Yes P00 Pull-up 1: No 0: Yes 0002H P17 Pull-up 1: No 0: Yes P16 Pull-up 1: No 0: Yes P15 Pull-up 1: No 0: Yes P14 Pull-up 1: No 0: Yes P13 Pull-up 1: No 0: Yes P12 Pull-up 1: No 0: Yes P11 Pull-up 1: No 0: Yes P10 Pull-up 1: No 0: Yes 0003H P37 Pull-up 1: No 0: Yes P36 Pull-up 1: No 0: Yes P35 Pull-up 1: No 0: Yes P34 Pull-up 1: No 0: Yes P33 Pull-up 1: No 0: Yes P32 Pull-up 1: No 0: Yes P31 Pull-up 1: No 0: Yes P30 Pull-up 1: No 0: Yes 0004H P67 Pull-up 1: No 0: Yes P66 Pull-up 1: No 0: Yes P65 Pull-up 1: No 0: Yes P64 Pull-up 1: No 0: Yes P63 Pull-up 1: No 0: Yes P62 Pull-up 1: No 0: Yes P61 Pull-up 1: No 0: Yes P60 Pull-up 1: No 0: Yes Vacancy Vacancy Vacancy Readable and writable Readable and writable Readable and writable P74 Pull-up 1: No 0: Yes P73 Pull-up 1: No 0: Yes P72 Pull-up 1: No 0: Yes P71 Pull-up 1: No 0: Yes P70 Pull-up 1: No 0: Yes Vacancy Vacancy Vacancy Vacancy Readable and writable Readable and writable Readable and writable P83 Pull-up 1: No 0: Yes P82 Pull-up 1: No 0: Yes P81 Pull-up 1: No 0: Yes P80 Pull-up 1: No 0: Yes Vacancy Vacancy Vacancy Readable and writable 0001H P07 Pull-up 1: No 0: Yes 0000H Readable and writable 0005H 0006H Readable and writable Notes: • Set each bit to 1 to erase. • Do not write 0 to the vacant bit. The read value of the vacant bit is 1, unless 0 is written to it. 18 Bit 2 Oscillation stabilization time MB89640 Series ■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE 1. EPROM for Use MBM27C256A-20TV 2. Programming Socket Adapter To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato Co., Ltd.) listed below. Package LCC-32 (Rectangle) Adapter socket part number ROM-32LC-28DP-YG Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760 3. Memory Space Memory space in each mode, such as 32-Kbyte PROM is diagrammed below. Address Single chip Corresponding addresses on the EPROM programmer 0000 H I/O 0080 H RAM 0480 H Not available 8000 H 0000 H Not available 8007 H Not available 0007 H PROM 32 KB FFFFH EPROM 32 KB 7FFFH 4. Programming to the EPROM (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0007H to 7FFFH. (3) Program to 0000H to 7FFFH with the EPROM programmer. 19 MB89640 Series ■ BLOCK DIAGRAM Main clock oscillator CMOS I/O port Clock controller Port 3 X0 X1 8-bit pulse width counter Subclock oscillator (32.768 kHz) X0A X1A 16-bit timer/counter P34/EC Reset circuit Time-base timer Watch prescaler P33/SI1 P32/SO1 P31/SCK1 P30/ADST P37/PTO1 P52/PWM P53/PTO2 P57/SI2 P56/SO2 P55/SCK2 Serial I/O 1 Internal bus RST 2-channel 8-bit PWM timer Serial I/O 2 P10/A08 to P17/A15 8 CMOS I/O ports Port 5 8 P54/BZ 2-channel 8-bit D/A converter DAVC MOD0 MOD1 External bus interface Port 4 Medium-voltage N-ch open-drain output port P40 to P47 Port 2 N-ch open-drain output port 8 8-bit A/D converter CMOS output port ROM RAM Other pins V CC, V SS External interrupt 1 5 External interrupt 2 4 CMOS input port Port 7 CMOS input port CPU Port 8 F2MC-8L 20 P51/DA2 P50/DA1 N-ch open-drain I/O port Port 6 P00/AD0 to P07/AD7 Port 0 and port 1 Buzzer output P27/ALE P26/RD P25/WR P24/CLK P23/RDY P22/HRQ P21/HAK P20/BUFC P36/WTO P35/PWC P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 AVRH AVRL AV CC AV SS P74/LI4 P73/LI3 P72/LI2 P71/LI1 P70/LI0 P83/INT3 P82/INT2 P81/INT1 P80/INT0 MB89640 Series ■ CPU CORE 1. Memory Space The microcontrollers of the MB89640 series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89640 series is structured as illustrated below. Memory Space 0000 H MB89PV640 0000 H I/O 0080 H MB89643 I/O 0080 H RAM 1 KB 0100 H 0080 H MB89P647 MB89647 I/O 0080 H RAM 1 KB RAM 768 B 0100 H 0100 H 0200 H 0000 H I/O Register 0180 H MB89646 0080 H 0100 H Not available 0000 H RAM 512 B Register 0200 H MB89645 I/O RAM 256 B 0100 H Register 0000 H Register Register 0200 H 0200 H 0280 H 0280 H 0380 H 0480 H 0480 H External area External area External area External area External area 8000 H 8000 H Not available Not available 8007 H 8007 H A000 H External ROM 32 KB FFFF H C000 H C000 H E000 H FFFF H Not available ROM 8 KB ROM 16 KB FFFF H ROM 32 KB ROM 24 KB FFFF H FFFF H Note: Since addresses 8000H to 8006H for the MB89P647 comprise an option area, do not use this area for the MB89PV640 and MB89647. 21 MB89640 Series 2. Registers The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided: Program counter (PC): A 16-bit register for indicating instruction storage positions Accumulator (A): A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX): A 16-bit register for index modification Extra pointer (EP): A 16-bit pointer for indicating a memory address Stack pointer (SP): A 16-bit register for indicating a stack area Program status (PS): A 16-bit register for storing a register pointer, a condition code 16 bits Initial value FFFDH : Program counter PC A : Accumulator Undefined T : Temporary accumulator Undefined IX : Index register Undefined EP : Extra pointer Undefined SP : Stack pointer Undefined PS : Program status I-flag = 0, IL1, 0 = 11 Other bits are undefined. The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) Structure of the Program Status Register 15 PS 14 13 12 RP 10 9 8 Vacancy Vacancy Vacancy RP 22 11 7 6 H I 5 4 IL1, 0 3 2 1 0 N Z V C CCR MB89640 Series The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. Rule for Conversion of Actual Addresses of the General-purpose Register Area Lower OP codes RP “0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ b1 b0 ↓ ↓ Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared otherwise. This flag is for decimal adjustment instructions. I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0 when reset. IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 IL0 Interrupt level 0 0 0 1 1 0 2 1 1 3 1 High-low High Low = no interrupt N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0. Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise. V-flag: Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does not occur. C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise. Set to the shift-out value in the case of a shift instruction. 23 MB89640 Series The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers. Up to a total of 16 banks can be used on the MB89643 and a total of 32 banks can be used on the MB89645/646/647/P647/PV640. The bank currently in use is indicated by the register bank pointer (RP). Note: The number of register banks that can be used varies with the RAM size. Register Bank Configuration This address = 0100 H + 8 × (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area 24 MB89640 Series ■ I/O MAP Address Read/write Register name 00H (R/W) PDR0 Port 0 data register 01H (W) DDR0 Port 0 data direction register 02H (R/W) PDR1 Port 1 data register 03H (W) DDR1 Port 1 data direction register 04H (R/W) PDR2 Port 2 data register 05H (W) BCTR External bus control register 06H Register description Vacancy 07H (R/W) SYCC System clock control register 08H (R/W) STBC Standby control register 09H (R/W) WDTC Watchdog timer control register 0AH (R/W) TBCR Time-base timer control register 0BH (R/W) WPCR Watch prescaler control register 0CH (R/W) PDR3 Port 3 data register 0DH (W) DDR3 Port 3 data direction register 0EH (R/W) PDR4 Port 4 data register 0FH (R/W) BUZR Buzzer register 10H (R/W) PDR5 Port 5 data register 11H (R/W) PDR6 Port 6 data register 12H (R) PDR7 Port 7 data register 13H (R) PDR8 Port 8 data register 14H Vacancy 15H Vacancy 16H Vacancy 17H Vacancy 18H (R/W) TMCR 16-bit timer control register 19H (R/W) TCHR 16-bit timer count register (H) 1AH (R/W) TCLR 16-bit timer count register (L) Vacancy 1BH 1CH (R/W) SMR1 Serial 1 mode register 1DH (R/W) SDR1 Serial 1 data register 1EH (R/W) SMR2 Serial 2 mode register 1FH (R/W) SDR2 Serial 2 data register (Continued) 25 MB89640 Series (Continued) Address Read/write Register name 20H (R/W) ADC1 A/D converter control register 1 21H (R/W) ADC2 A/D converter control register 2 22H (R/W) ADCD A/D converter data register Vacancy 23H 24H (R/W) DACR D/A converter control register 25H (W) DADR1 D/A converter data register 1 26H (W) DADR2 D/A converter data register 2 27H Vacancy 28H (R/W) CNTR1 PWM timer control register 1 29H (R/W) CNTR2 PWM timer control register 2 2AH (R/W) CNTR3 PWM timer control register 3 2BH (W) COMR1 PWM timer compare register 1 2CH (W) COMR2 PWM timer compare register 2 2DH (R/W) PCR1 PWC pulse width control register 1 2EH (R/W) PCR2 PWC pulse width control register 2 2FH (R/W) RLBR PWC reload buffer register 30H Vacancy 31H (R/W) EIC1 External interrupt 1 control register 1 32H (R/W) EIC2 External interrupt 1 control register 2 33H (R/W) EIE2 External interrupt 2 enable register 34H (R/W) EIF2 External interrupt 2 flag register 35H to 7AH Vacancy 7BH Vacancy 7CH (W) ILR1 Interrupt level setting register 1 7DH (W) ILR2 Interrupt level setting register 2 7EH (W) ILR3 Interrupt level setting register 3 7FH Note: Do not use vacancies. 26 Register description Vacancy MB89640 Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (AVSS = VSS = 0.0 V) Parameter Symbol Value Unit Remarks Min. Max. VCC AVCC DAVC VSS – 0.3 VSS + 7.0 V * A/D converter reference input voltage AVRH VSS – 0.3 VSS + 7.0 V AVRH must not exceed AVCC + 0.3 V. AVRL VSS – 0.3 VSS + 7.0 V AVRL must not exceed AVRH. Program voltage VPP VSS – 0.3 13.0 V MOD1 pin on MB89P647 VI VSS – 0.3 VCC + 0.3 V P52 to P57 with a pull-up resistor and other input ports VI2 VSS – 0.3 VSS + 7.0 V P52 to P57 without a pull-up resistor VO VSS – 0.3 VCC + 0.3 V P40 to P47 and P52 to P57 with a pull-up resistor and other output ports VO2 VSS – 0.3 VSS + 17.0 V P40 to P47 without a pull-up resistor VO3 VSS – 0.3 VSS + 7.0 V P52 to P57 without a pull-up resistor “L” level maximum output current IOL 20 mA “L” level average output current IOLAV 4 mA Average value (operating current × operating rate) “L” level total average output current ∑IOLAV 40 mA Average value (operating current × operating rate) “L” level total maximum output current ∑IOL 100 mA “H” level maximum output current IOH –20 mA “H” level average output current IOHAV –4 mA Average value (operating current × operating rate) “H” level total average output current ∑IOHAV –20 mA Average value (operating current × operating rate) “H” level total maximum output current ∑IOH –50 mA Power consumption PD 500 mW Power supply voltage Input voltage Output voltage (Continued) 27 MB89640 Series (Continued) (AVSS = VSS = 0.0 V) Parameter Symbol Value Min. Max. Unit Operating temperature TA –40 +85 °C Storage temperature Tstg –55 +150 °C Remarks * : Use DAVC and AVCC and VCC set at the same voltage. Take care so that DAVC and AVCC does not exceed VCC, such as when power is turned on. Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Recommended Operating Conditions (AVSS = VSS = 0.0 V) Parameter Power supply voltage Symbol VCC AVCC DAVC Value Unit Remarks Min. Max. 2.2* 6.0* V Normal operation assurance range* (MB89643/645/646/647) 2.7* 6.0* V Normal operation assurance range* (MB89P647/PV640) 1.5 6.0 V Retains the RAM state in stop mode A/D converter reference input voltage AVRH 3.0 AVCC V AVRL 0.0 2.0 V Operating temperature TA –40 +85 °C * : These values vary with the operating frequency and analog assurance range. See Figure 1, “5. A/D Converter Electrical Characteristics,” and “6. D/A Converter Electrical Characteristics.” 28 MB89640 Series 6 5 Analog accuracy assured in the VCC = AVCC = DAVC = 3.5 V to 6.0 V range. Operating voltage (V) Operation assurance range 4 3 2 1 1.0 10.0 5.0 Main clock operating frequency (at an instruction cycle of 4/FCH) (MHz) 4.0 2.0 1.0 0.8 0.5 0.4 Minimum execution time (instruction cycle) (µs) Note: The shaded area is assured only for the MB89643/645/646/647. Figure 1 Operating Voltage vs. Main Clock Operating Frequency Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FCH. Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating speed is switched using a gear. 29 MB89640 Series 3. DC Characteristics (AVCC = DAVC = VCC = +5.0 V, AVSS = VSS = 0.0 V, FCH = 10 MHz, FCL = 32.768 kHz, TA = –40°C to +85°C) Parameter VIH “H” level input voltage*1 Pin Symbol VIHS Condition P00 to P07, P10 to P17, P22, P23 RST, P30 to P37, P50, P51, P70 to P74, P80 to P83 Value Unit Min. Typ. Max. 0.7 VCC VCC + 0.3 V 0.8 VCC VCC + 0.3 V With pull-up resistor P52 to P57 “L” level input voltage*1 Open-drain output pin application voltage “H” level output voltage “L” level output voltage Remarks Without pullup resistor 0.8 VCC VSS + 6.0 V VSS − 0.3 0.3 VCC V RST, P30 to P37, P50 to P57, P70 to P74, P80 to P83 VSS − 0.3 0.2 VCC V VD P40 to P47 VSS − 0.3 VSS + 15.0 V Without pullup resistor VD2 P52 to P57 VSS − 0.3 VSS + 6.0 V Without pullup resistor VSS − 0.3 VCC + 0.3 V VIHS2 P52 to P57 VIL P00 to P07, P10 to P17, P22, P23 VILS P60 to P67 VD3 P40 to P47, P52 to P57 VOH P00 to P07, P10 to P17, P20 to P27, P30 to P37 IOH = –2.0 mA 2.4 V VOL P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67 IOL = +1.8 mA 0.4 V VOL2 RST IOL = +4.0 mA 0.4 V ±5 µA Input leakage current (Hi-z output ILI1 leakage current) P00 to P07, P10 to P17, P20 to P27, P30 to P37, P50 to P57, P70 to P74, 0.45 V < VI < VCC P80 to P83, MOD0, MOD1 With pull-up resistor Without pullup resistor (Continued) 30 MB89640 Series (AVCC = DAVC = VCC = +5.0 V, AVSS = VSS = 0.0 V, FCH = 10 MHz, FCL = 32.768 kHz, TA = –40°C to +85°C) Parameter Pull-up resistance Power supply current Pin Remarks 100 kΩ Without pullup resistor 10 20 mA — 11 23 mA — 1.5 2 mA — 2.5 5 mA VCC = +5.0 V • Main clock sleep • High speed*2 — 3 7 mA ICS2 VCC = +3.0 V • Main clock sleep • Low speed*3 — 1 1.5 mA ICS3 VCC = +3.0 V Subclock sleep — 25 50 µA — — 10 µA — 50 100 µA — 1 3 mA Min. Typ. Max. VI = 0.0 V 25 50 — ICC1 VCC = +5.0 V • Main clock operation • High speed*2 ICC2 VCC = +3.0 V • Main clock operation • Low speed*3 ICS1 RPULL P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P64, P70 to P74, P80 to P83, RST VCC TA = +25°C ICCH Subclock stop VCC = +3.0 V Subclock operation (32.768 kHz) ICSB ICCT VCC VCC = +3.0 V Watch mode (32.768 kHz) — — 15 µA IA AVCC • Main clock operation • High speed*2 — 1 3 mA CIN Other than AVCC, AVSS, VCC, and VSS f = 1 MHz — 10 pF Power supply current Input capacitance Condition Value Unit Symbol MB89P647 only MB89P647 only MB89P647 only *1: Connect MOD0 and MOD1 to VCC or VSS. *2: High-speed operation is the operation when the system clock is set to the maximum speed by the system clock select bit at 10-MHz clock. *3: Low-speed operation is the operation when the system clock is set to the maximum speed by the system clock select bit at 10-MHz clock. 31 MB89640 Series 4. AC Characteristics (1) Reset Timing (VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Symbol Parameter RST “L” pulse width Value Condition tZLZH — Min. Max. 48 tXCYL — Unit Remarks ns * : tXCYL is the oscillation cycle (1/FCH) to input to the X0 pin. tZLZH RST 0.2 V CC 0.2 V CC (2) Power-on Reset (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Power supply rising time tR Power supply cut-off time tOFF Condition — Value Unit Min. Max. — 50 ms 1 — ms Remarks Due to repeated operation Note: Make sure that power supply rises within the selected oscillation stabilization time. For example, when the main clock is operating at 10 MHz (FCH) and the oscillation stabilization time select option has been set to 214/FCH, the oscillation stabilization delay time is 1.6 ms and accordingly the maximum value of power supply rising time is about 1.6 ms. Keep in mind that abrupt changes in power supply voltage may cause a power-on reset. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. tR tOFF 2.0 V VCC 0.2 V 32 0.2 V 0.2 V MB89640 Series (3) Clock Timing (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Symbol Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rising/falling time Pin Condition Value Min. Typ. Max. Unit FCH X0, X1 1 — 10 MHz FCL X0A, X1A — 32.768 — kHz tXCYL X0, X1 100 — 1000 ns tLXCYL X0A, X1A — 30.5 — µs PWH PWL X0 20 — — ns PWHL PWLL X0A — 30.5 — µs tCR tCF X0 — — 10 ns — Remarks External clock External clock X0 and X1 Timing and Conditions tXCYL PWH PWL tCR 0.8 VCC tCF 0.8 VCC X0 0.2 VCC 0.2 VCC 0.2 VCC Main Clock Conditions When a crystal or ceramic resonator is used. X0 X1 When an external clock is used. X0 X1 Open 33 MB89640 Series X0A and X1A Timing and Conditions tLXCYL PWHL PWLL tCR 0.8 VCC tCF 0.8 VCC X0A 0.2 VCC 0.2 VCC 0.2 VCC Subclock Conditions When a crystal or ceramic resonator is used. X0A When an external clock is used. X1A X0A X1A Open (4) Instruction Cycle Parameter Symbol Value (typical) Unit 4/FCH system clock selection 11 µs tinst = 0.4 µs when operating at FCH = 10 MHz 8/FCH system clock selection 10 µs tinst = 0.8 µs when operating at FCH = 10 MHz 16/FCH system clock selection 01 µs tinst = 1.6 µs when operating at FCH = 10 MHz 64/FCH system clock selection 00 µs tinst = 6.4 µs when operating at FCH = 10 MHz Instruction cycle tinst (minimum execution time) 34 Remarks MB89640 Series (5) Recommended Resonator Manufacturers Sample Application of Piezoelectric Resonator (FAR series) X0 X1 FAR* C1 C2 * : Fujitsu Acoustic Resonator C1 = C2 = 20 pF±8 pF (built-in FAR) FAR part number (built-in capacitor type) Frequency Initial deviation of FAR frequency (TA = +25°C) Temperature characteristic of FAR frequency (TA = –20°C to +60°C) FAR-C4CB-08000-M02 8.00 MHz ±0.5% ±0.5% FAR-C4CB-10000-M02 10.00 MHz ±0.5% ±0.5% Inquiry: FUJITSU LIMITED 35 MB89640 Series Sample Application of Ceramic Resonator X0 X1 * C1 Resonator manufacturer* Kyocera Corporation Murata Mfg. Co., Ltd. C2 Resonator Frequency C1 (pF) C2 (pF) R (kΩ) KBR-7.68MWS 7.68 MHz 33 33 KBR-8.0MWS 8.0 MHz 33 33 CSA8.00MTZ 8.0 MHz 30 30 Inquiry: Kyocera Corporation • AVX Corporation North American Sales Headquarters: TEL 1-803-448-9411 • AVX Limited European Sales Headquarters: TEL 44-1252-770000 • AVX/Kyocera H.K. Ltd. Asian Sales Headquarters: TEL 852-363-3303 Murata Mfg. Co., Ltd. • Murata Electronics North America, Inc.: TEL 1-404-436-1300 • Murata Europe Management GmbH: TEL 49-911-66870 • Murata Electronics Singapore (Pte.) Ltd.: TEL 65-758-4233 (6) Clock Output Timing (VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin Cycle time tCYC CLK CLK ↑→ CLK ↓ tCHCL CLK Condition Value Unit Max. 200 — ns tXCYL × 2 at 10 MHz oscillation 30 100 ns Approx. tCYL/2 at 10 MHz oscillation — tCYC tCHCL 2.4 V 2.4 V CLK 0.8 V 36 Remarks Min. MB89640 Series (7) Bus Read Timing (VCC = +5.0 V±10%, FCH = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin Value Condition Min. Max. Unit Remarks Valid address → RD ↓ time tAVRL RD, A15 to 08, AD7 to 0 1/4 tinst* – 64 ns — ns RD pulse width tRLRH RD 1/2 tinst* – 20 ns — ns Valid address → read data time tAVDV AD7 to 0, A15 to 08 1/2 tinst* 200 ns No wait RD ↓ → read data time tRLDV RD, AD7 to 0 1/2 tinst* – 80 ns 120 ns No wait RD ↑ → data hold time tRHDX AD7 to 0, RD 0 — ns RD ↑ → ALE ↑ time tRHLH RD, ALE 1/4 tinst* – 40 ns — ns RD ↑ → address invalid time tRHAX RD, A15 to 08 1/4 tinst* – 40 ns — ns RD ↓ → CLK ↑ time tRLCH RD, CLK 1/4 tinst* – 40 ns — ns CLK ↓ → RD ↑ time tCLRH RD, CLK 0 — ns RD ↓ → BUFC ↓ time tRLBL RD, BUFC –5 — ns BUFC ↑→ Valid address time tBHAV A15 to 08, AD7 to 0, BUFC 5 — ns — * : For information on tinst, see “(4) Instruction Cycle.” 2.4 V CLK 0.8 V tRHLH ALE 0.8 V AD 2.4 V 0.7 VCC 0.3 VCC 0.8 V tAVDV A 2.4 V 0.3 VCC 0.8 V tRHDX 2.4 V 2.4 V 0.8 V tAVRL 0.7 VCC 0.8 V tCLRH tRHAX tRLCH tRLDV 2.4 V 0.8 V tRLRH RD 2.4 V 0.8 V tRLBL tBHAV 2.4 V BUFC 0.8 V 37 MB89640 Series (8) Bus Write Timing (VCC = +5.0 V±10%, FCH = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin Value Condition Min. Max. Valid address → ALE ↓ time tAVLL AD7 to 0, ALE, A15 to 08 1/4 tinst*1 – 64 ns*2 — ns ALE ↓ → address invalid time tLLAX AD7 to 0, ALE, A15 to 08 5 — ns Valid address → WR ↓ time tAVWL WR, ALE 1/4 tinst*1 – 60 ns — ns WR pulse width tWLWH WR Write data → WR ↑ time tDVWH AD7 to 0, WR inst*1 – 20 ns — ns inst*1 – 60 ns — ns inst*1 – 40 ns — ns inst*1 – 40 ns — ns inst*1 – 40 ns — ns inst*1 – 40 ns — ns 1/2 t WR ↑ → address invalid time tWHAX WR, A15 to 08 WR ↑ → data hold time tWHDX AD7 to 0, WR WR ↑ → ALE ↑ time tWHLH WR, ALE WR ↓ → CLK ↑ time tWLCH WR, CLK CLK ↓ → WR ↑ time tCLWH WR, CLK ALE pulse width tLHLL ALE ALE ↓ → CLK ↑ time tLLCH ALE, CLK 1/2 t — 1/4 t 1/4 t 1/4 t 1/4 t 0 1/4 t inst*1 1/4 t inst*1 — ns – 35 ns *2 — ns – 30 ns *2 — ns *1: For information on tinst, see “(4) Instruction Cycle.” *2: These characteristics are also applicable to the bus read timing. 2.4 V CLK 0.8 V tLHLL ALE AD tLLCH tWHLH 2.4 V 0.8 V tAVLL 0.8 V tLLAX 2.4 V 2.4 V 2.4 V 2.4 V 0.8 V 0.8 V 0.8 V 0.8 V tDVWH A tWHDX 2.4 V 2.4 V 0.8 V tAVWL 0.8 V tCLWH tWHAX tWLCH tWLWH WR 2.4 V 0.8 V 38 Unit Remarks *2 MB89640 Series (9) Ready Input Timing (VCC = +5.0 V±10%, FCH = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin RDY valid → CLK ↑ time tYVCH RDY, CLK CLK ↑ → RDY invalid time tCHYX RDY, CLK Condition — Value Unit Remarks Min. Max. 60 — ns * 0 — ns * * : These characteristics are also applicable to the read cycle. 2.4 V CLK 2.4 V ALE AD Address Data A WR tYVCH tCHYX RDY tYVCH tCHYX Note: The bus cycle is also extended in the read cycle in the same manner. 39 MB89640 Series (10) Serial I/O Timing (VCC = +5.0 V±10%, FCH = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin Value Min. Max. Unit Serial clock cycle time tSCYC SCK1, SCK2 2 tinst* — µs SCK1 ↓ → SO1 time SCK2 ↓ → SO2 time tSLOV SCK1, SO1 SCK2, SO2 –200 200 ns Valid SI1 → SCK1 ↑ Valid SI2 → SCK2 ↑ tIVSH SI1, SCK1 SI2, SCK2 1/2 tinst* — µs SCK1 ↑ → valid SI1 hold time SCK2 ↑ → valid SI2 hold time tSHIX SCK1, SI1 SCK2, SI2 1/2 tinst* — µs Serial clock “H” pulse width tSHSL SCK1, SCK2 1 tinst* — µs Serial clock “L” pulse width tSLSH SCK1, SCK2 1 tinst* — µs SCK1 ↓ → SO1 time SCK2 ↓ → SO2 time tSLOV SCK1, SO1 SCK2, SO2 0 200 ns Valid SI1 → SCK1 ↑ Valid SI2 → SCK2 ↑ tIVSH SI1, SCK1 SI2, SCK2 1/2 tinst* — µs SCK1 ↑ → valid SI1 hold time SCK2 ↑ → valid SI2 hold time tSHIX SCK1, SI1 SCK2, SI2 1/2 tinst* — µs * : For information on tinst, see “(4) Instruction Cycle.” 40 Condition Internal shift clock mode External shift clock mode Remarks MB89640 Series Internal Shift Clock Mode tSCYC SCK1 SCK2 2.4 V 0.8 V 0.8 V tSLOV 2.4 V SO1 SO2 0.8 V tIVSH SI1 SI2 tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC External Shift Clock Mode tSLSH SCK1 SCK2 tSHSL 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tSLOV SO1 SO2 2.4 V 0.8 V tIVSH SI1 SI2 tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 41 MB89640 Series (11) Peripheral Input Timing (VCC = +5.0 V±10%, FCH = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin tILIH1 PWC, EC, INT0 to INT3 Peripheral input pulse “L” width 1 tIHIL1 PWC, EC, INT0 to INT3 Peripheral input pulse “H” width 2 tILIH2 ADST Peripheral input pulse “L” width 2 tIHIL2 ADST Peripheral input pulse “H” width 2 tILIH2 ADST Peripheral input pulse “L” width 2 tIHIL2 Peripheral input pulse “H” width 1 Condition Value Max. 2 tinst* — µs 2 tinst* — µs 32 tinst* — µs 32 tinst* — µs 8 tinst* — µs 8 tinst* — µs — A/D mode Sense mode ADST * : For information on tinst, see “(4) Instruction Cycle.” tIHIL1 PWC EC INT0 to 3 tILIH1 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tIHIL2 tILIH2 0.8 VCC ADST 0.2 VCC 42 Unit Min. 0.2 VCC 0.8 VCC Remarks MB89640 Series 5. A/D Converter Electrical Characteristics (AVCC = VCC = +3.5 V to +6.0 V, FCH = 10 MHz, AVSS = VSS = AVRL = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin Resolution Condition Typ. Max. — — 8 bit — — ±3.0 LSB — — ±1.0 LSB — — ±0.9 LSB –1.0 +0.5 +2.0 LSB AVRH – 4.5 AVRH – 1.5 AVRH + 1.5 LSB — — 0.5 LSB — 44 — tinst* — 12 — tinst* — — 10 µA 0 — AVRH V 0 — AVCC V When A/D conversion is activated AVRH = 5.0 V — 100 µA When A/D conversion is stopped AVRH = 5.0 V — — 1 µA Total error — Differential linearity error Zero transition voltage Full-scale transition voltage AVRH = AVCC VOT Remarks — VFST Interchannel disparity A/D mode conversion time — Sense mode conversion time Analog port input current Unit Min. — Linearity error Value — IAIN Analog input voltage — Reference voltage — AN0 to AN7 IR AVRH Reference voltage supply current IRH * : For information on tinst, see “(4) Instruction Cycle.” 43 MB89640 Series (1) A/D Glossary • Resolution Analog changes that are identifiable with the A/D converter. When the number of bits is 8, analog voltage can be divided into 28 = 256. • Linearity error (unit: LSB) The deviation of the straight line connecting the zero transition point (“0000 0000” ↔ “0000 0001”) with the full-scale transition point (“1111 1111” ↔ “1111 1110”) from actual conversion characteristics • Differential linearity error (unit: LSB) The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value • Total error (unit: LSB) The difference between theoretical and actual conversion values Digital output 1111 1111 1111 • 1110 0000 0000 0000 • • • • • • • • • • • • • • • • • • • Theoretical conversion value Actual conversion value (1 LSB × N + VOT) 1 LSB = AVRH – AVRL 256 Linearity error = Linearity error Differential linearity error = Total error = VNT – (1 LSB × N + VOT) 1 LSB V( N + 1 ) T – VNT – 1 1 LSB VNT – (1 LSB × N + 1 LSB) 1 LSB 0010 0001 0000 VOT VNT V(N + 1)T VFST Analog input (2) Precautions • Input impedance of the analog input pins The A/D converter used for the MB89640 series contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for eight instruction cycles after activating A/D conversion. For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output impedance of the external circuit low (below 10 kΩ). Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about 0.1 µF for the analog input pin. 44 MB89640 Series Analog Input Equivalent Circuit Sample hold circuit . C =. 33 pF Analog input pin Comparator If the analog input impedance is higher than 10 kΩ, it is recommended to contact an external capacitor of about 0.1 µF. . R =. 6 kΩ Close for 8 instruction cycles after activating A/D conversion. Analog channel selector • Error The smaller the | AVRH – AVRL |, the greater the error would become relatively. 6. D/A Converter Electrical Characteristics (DAVC = VCC = +3.5 V to +6.0 V, FCH=10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Differential linearity error Remarks Typ. Max. — — 8 bit — — ±1.0 LSB — — ±0.9 LSB — 20 — kΩ IDINA — 0.1 mA At no load and conversion cycle of 5 µs IDINS — 0.1 — µA During power down — Output impedance D/A analog power supply current (for one channel) Unit Min. Resolution Linearity error Value DAVC = VCC = 5.0 V 45 MB89640 Series ■ EXAMPLES CHARACTERISTICS (1) “L” Level Output Voltage (P00 to P07, P10 to P17, P20 to P27, P30 to P37, P50 to P57, P60 to P67) VOL vs. IOL VOL (V) 0.6 VCC = 2.5 V TA = +25°C 0.5 VCC = 3.0 V 0.4 VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V 0.3 0.2 VCC–VOH vs. IOH VCC = 2.5 V TA = +25°C 0.8 0.7 0.6 VCC = 3.0 V 0.5 VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V 0.4 0.2 0.1 0 1 2 3 4 5 6 7 8 9 10 IOL (mA) (3) “L” Level Output Voltage (P40 to P47) VOL vs. IOL VOL (mV) 1500 TA = +25°C 1400 1300 VCC = 5 V 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 IOL (mA) 46 VCC–VOH (V) 1.0 0.9 0.3 0.1 0.0 (2) “H” Level Output Voltage (P00 to P07, P10 to P17, P20 to P27, P30 to P37) 0.0 0.0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 IOH (mA) (4) “H” Level Input Voltage/“L” Level Input Voltage (CMOS Input) VIN vs. VCC VIN (V) 5.0 TA = +25°C 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 1 2 3 4 5 6 7 VCC (V) MB89640 Series (5) “H” Level Input Voltage/“L” Level Input Voltage (Hysteresis Input) VIN vs. VCC VIN (V) 5.0 TA = +25°C 4.5 4.0 3.5 VIHS 3.0 2.5 VILS 2.0 1.5 1.0 0.5 0.0 0 1 2 3 4 5 6 7 VCC (V) VIHS: Threshold when input voltage in hysteresis characteristics is set to “H” level VILS: Threshold when input voltage in hysteresis characteristics is set to “L” level (6) Power Supply Current (External Clock) ICC vs. VCC Main clock operation mode (64/FCH instruction) ICC vs. VCC Main clock operation mode (4/FCH instruction) ICC (mA) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2 TA = +25°C ICC (mA) XTAL 10 MHz 3 XTAL TA = +25°C 8 MHz 10 MHz 2 6 MHz 8 MHz 6 MHz 4 MHz 4 MHz 1 2 MHz 1 MHz 3 4 5 6 VCC (V) 2 MHz 1 MHz 0 2 3 4 5 6 VCC (V) (Continued) 47 MB89640 Series (Continued) ICS1 vs. VCC Main clock sleep mode (4/FCH instruction) ICS2 vs. VCC Main clock sleep mode (64/FCH instruction) ICS1 (mA) 4 XTAL 10 MHz TA = +25°C ICS2 (µA) 1,500 TA = +25°C XTAL 10 MHz 8 MHz 8 MHz 3 6 MHz 1,000 6 MHz 2 4 MHz 4 MHz 500 0 2 2 MHz 1 MHz 2 MHz 1 MHz 1 0 3 4 5 6 2 3 4 VCC (V) ICS3 vs. VCC Subclock mode ICS3 (µA) 120 TA = +25°C Operation 100 80 60 Sleep 40 20 Watch 0 2 3 4 5 6 VCC (V) (7) Pull-up Resistance RPULL vs. VCC RPULL (kΩ) 1000 TA = +25°C 100 10 1 48 2 3 4 5 6 VCC (V) 5 6 VCC (V) MB89640 Series ■ INSTRUCTIONS Execution instructions can be divided into the following four groups: • • • • Transfer Arithmetic operation Branch Others Table 1 lists symbols used for notation of instructions. Table 1 Instruction Symbols Symbol Meaning dir Direct address (8 bits) off Offset (8 bits) ext Extended address (16 bits) #vct Vector table number (3 bits) #d8 Immediate data (8 bits) #d16 Immediate data (16 bits) dir: b Bit direct address (8:3 bits) rel Branch relative address (8 bits) @ Register indirect (Example: @A, @IX, @EP) A Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) AH Upper 8 bits of accumulator A (8 bits) AL Lower 8 bits of accumulator A (8 bits) T Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) TH Upper 8 bits of temporary accumulator T (8 bits) TL Lower 8 bits of temporary accumulator T (8 bits) IX Index register IX (16 bits) (Continued) 49 MB89640 Series (Continued) Symbol Meaning EP Extra pointer EP (16 bits) PC Program counter PC (16 bits) SP Stack pointer SP (16 bits) PS Program status PS (16 bits) dr Accumulator A or index register IX (16 bits) CCR Condition code register CCR (8 bits) RP Register bank pointer RP (5 bits) Ri General-purpose register Ri (8 bits, i = 0 to 7) × Indicates that the very × is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) (×) Indicates that the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) (( × )) The address indicated by the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Columns indicate the following: Mnemonic: Assembler notation of an instruction ~: Number of instructions #: Number of bytes Operation: Operation of an instruction TL, TH, AH: A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: • “–” indicates no change. • dH is the 8 upper bits of operation description data. • AL and AH must become the contents of AL and AH immediately before the instruction is executed. • 00 becomes 00. N, Z, V, C: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. OP code: Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F ← This indicates 48, 49, ... 4F. 50 MB89640 Series Table 2 Transfer Instructions (48 instructions) Mnemonic ~ # Operation TL TH AH NZVC OP code MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 – – – – – AL AL AL AL AL AL AL – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –––– –––– –––– –––– –––– ++–– ++–– ++–– ++–– ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 MOVW ext,A MOVW @EP,A MOVW EP,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off 5 4 2 3 4 5 3 1 1 3 2 2 – – – AL AL AL – – – AH AH AH – – – dH dH dH –––– –––– –––– ++–– ++–– ++–– D4 D7 E3 E4 C5 C6 MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP,#d16 MOVW IX,A MOVW A,IX MOVW SP,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ← (A) ( (IX) +off ) ← (A) (ext) ← (A) ( (EP) ) ← (A) (Ri) ← (A) (A) ← d8 (A) ← (dir) (A) ← ( (IX) +off) (A) ← (ext) (A) ← ( (A) ) (A) ← ( (EP) ) (A) ← (Ri) (dir) ← d8 ( (IX) +off ) ← d8 ( (EP) ) ← d8 (Ri) ← d8 (dir) ← (AH),(dir + 1) ← (AL) ( (IX) +off) ← (AH), ( (IX) +off + 1) ← (AL) (ext) ← (AH), (ext + 1) ← (AL) ( (EP) ) ← (AH),( (EP) + 1) ← (AL) (EP) ← (A) (A) ← d16 (AH) ← (dir), (AL) ← (dir + 1) (AH) ← ( (IX) +off), (AL) ← ( (IX) +off + 1) (AH) ← (ext), (AL) ← (ext + 1) (AH) ← ( (A) ), (AL) ← ( (A) ) + 1) (AH) ← ( (EP) ), (AL) ← ( (EP) + 1) (A) ← (EP) (EP) ← d16 (IX) ← (A) (A) ← (IX) (SP) ← (A) (A) ← (SP) ( (A) ) ← (T) ( (A) ) ← (TH),( (A) + 1) ← (TL) (IX) ← d16 (A) ← (PS) (PS) ← (A) (SP) ← d16 (AH) ↔ (AL) (dir): b ← 1 (dir): b ← 0 (AL) ↔ (TL) (A) ↔ (T) (A) ↔ (EP) (A) ↔ (IX) (A) ↔ (SP) (A) ← (PC) AL AL AL – – – – – – – – – – – – – – – AL AL – – – – AH AH AH – – – – – – – – – – – – – – – – AH – – – – dH dH dH dH – – dH – dH – – – dH – – AL – – – dH dH dH dH dH ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– ++++ –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0 Notes: • During byte transfer to A, T ← A is restricted to low bytes. • Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family) 51 MB89640 Series Table 3 Mnemonic ~ # ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ROLC A 2 1 CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Arithmetic Operation Instructions (62 instructions) Operation TL TH AH NZVC OP code (A) ← (A) + (Ri) + C (A) ← (A) + d8 + C (A) ← (A) + (dir) + C (A) ← (A) + ( (IX) +off) + C (A) ← (A) + ( (EP) ) + C (A) ← (A) + (T) + C (AL) ← (AL) + (TL) + C (A) ← (A) − (Ri) − C (A) ← (A) − d8 − C (A) ← (A) − (dir) − C (A) ← (A) − ( (IX) +off) − C (A) ← (A) − ( (EP) ) − C (A) ← (T) − (A) − C (AL) ← (TL) − (AL) − C (Ri) ← (Ri) + 1 (EP) ← (EP) + 1 (IX) ← (IX) + 1 (A) ← (A) + 1 (Ri) ← (Ri) − 1 (EP) ← (EP) − 1 (IX) ← (IX) − 1 (A) ← (A) − 1 (A) ← (AL) × (TL) (A) ← (T) / (AL),MOD → (T) (A) ← (A) ∧ (T) (A) ← (A) ∨ (T) (A) ← (A) ∀ (T) (TL) − (AL) (T) − (A) → C→A – – – – – – – – – – – – – – – – – – – – – – – dL – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 00 – – – – – – – – – – – dH – – – – – – dH – – – – dH – – – dH dH 00 dH dH dH – – – ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++– –––– –––– ++–– +++– –––– –––– ++–– –––– –––– ++R– ++R– ++R– ++++ ++++ ++–+ 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 C ← A← – – – ++–+ 02 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65 (A) − d8 (A) − (dir) (A) − ( (EP) ) (A) − ( (IX) +off) (A) − (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) ← (AL) ∀ (TL) (A) ← (AL) ∀ d8 (A) ← (AL) ∀ (dir) (A) ← (AL) ∀ ( (EP) ) (A) ← (AL) ∀ ( (IX) +off) (A) ← (AL) ∀ (Ri) (A) ← (AL) ∧ (TL) (A) ← (AL) ∧ d8 (A) ← (AL) ∧ (dir) (Continued) 52 MB89640 Series (Continued) Mnemonic ~ # AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 Operation (A) ← (AL) ∧ ( (EP) ) (A) ← (AL) ∧ ( (IX) +off) (A) ← (AL) ∧ (Ri) (A) ← (AL) ∨ (TL) (A) ← (AL) ∨ d8 (A) ← (AL) ∨ (dir) (A) ← (AL) ∨ ( (EP) ) (A) ← (AL) ∨ ( (IX) +off) (A) ← (AL) ∨ (Ri) (dir) – d8 ( (EP) ) – d8 ( (IX) + off) – d8 (Ri) – d8 (SP) ← (SP) + 1 (SP) ← (SP) – 1 Table 4 Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI ~ # 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI ~ # 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++++ ++++ ++++ ++++ –––– –––– 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1 Branch Instructions (17 instructions) Operation If Z = 1 then PC ← PC + rel If Z = 0 then PC ← PC + rel If C = 1 then PC ← PC + rel If C = 0 then PC ← PC + rel If N = 1 then PC ← PC + rel If N = 0 then PC ← PC + rel If V ∀ N = 1 then PC ← PC + rel If V ∀ N = 0 then PC ← PC + reI If (dir: b) = 0 then PC ← PC + rel If (dir: b) = 1 then PC ← PC + rel (PC) ← (A) (PC) ← ext Vector call Subroutine call (PC) ← (A),(A) ← (PC) + 1 Return from subrountine Return form interrupt Table 5 TL TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – dH – – –––– –––– –––– –––– –––– –––– –––– –––– –+–– –+–– –––– –––– –––– –––– –––– –––– Restore FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30 Other Instructions (9 instructions) Operation TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – dH – – – – – – – –––– –––– –––– –––– –––– –––R –––S –––– –––– 40 50 41 51 00 81 91 80 90 53 L 54 C D E F MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP,#d16 A,SP MOVW MOVW CLRB BBC MOVW XCHW dir: 6 dir: 6,rel A,@IX +d @IX +d,A IX,#d16 A,IX MOV CMP MOV CMP ADDC SUBC MOV @IX XOR AND OR A,@IX +d A,@IX +d A,@IX +d A,@IX +d +d,A A,@IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8 MOV CMP MOV CMP ADDC SUBC MOV XOR AND OR CLRB BBC MOVW MOVW MOVW XCHW A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP @EP,#d8 @EP,#d8 dir: 7 dir: 7,rel A,@EP @EP,A EP,#d16 A,EP MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BNC A,R0 A,R0 A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel R0 R0 #0 rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BC A,R1 A,R1 A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel R1 R1 #1 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BP A,R2 A,R2 A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel R2 R2 #2 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BN A,R3 A,R3 A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel R3 R3 #3 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BNZ A,R4 A,R4 A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel R4 R4 #4 rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BZ A,R5 A,R5 A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel R5 R5 #5 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BGE A,R6 A,R6 A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel R6 R6 #6 rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BLT A,R7 A,R7 A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel R7 R7 #7 rel 6 7 8 9 A B C D E F A ADDC A SUBC A XCH XOR AND OR A, T A A A MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX XOR AND OR DAA A,#d8 A,#d8 A,#d8 DAS rel rel rel rel CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC MOVW MOVW CLRB BBC INCW DECW MOVW MOVW CMPW ADDCW SUBCW XCHW XORW ANDW ORW A A A, T A A A @A,T A,@A dir: 3 dir: 3,rel EP EP EP,A A,EP A CMP CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP,A A,SP 5 A A SETC MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8 CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC B 4 SETI MOV MOVW CLRI A,ext A,PS A RORC A PUSHW POPW JMP CALL MOV MOVW CLRC IX IX addr16 addr16 ext,A PS,A POPW 9 7 8 6 3 A A 5 ROLC DIVU PUSHW 4 2 A RETI 3 MULU RET 2 1 SWAP 1 NOP 0 0 H MB89640 Series ■ INSTRUCTION MAP MB89640 Series ■ MASK OPTIONS Part number MB89643 MB89645 MB89646 MB89647 MB89P647 MB89PV640 Specifying procedure Specify when ordering masking Set with EPROM programmer Setting not possible Selectable per pin (P60 to P67 must be set to without a pull-up resistor when an A/D converter is used. P51 and P50 are must be set to without a pull-up resistor when a D/A converter is used.) Can be set per pin (Only P40 to P47 and P50 to P57 are without a pullup resistor.) Fixed to without pull-up resistor No. 1 Pull-up resistors P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P74, P80 to P83 2 Power-on reset With power-on reset Without power-on reset Selectable Setting possible Fixed to with power-on reset 3 Main clock oscillation stabilization time selection (when operating at 10 MHz) Approx. 218/FCH (Approx. 26.2 ms) Approx. 217/FCH (Approx. 13.1 ms) Approx. 214/FCH (Approx. 1.6 ms) Approx. 24/FCH (Approx. 0 ms) FCH: Main clock frequency Selectable Setting possible Fixed to approx. 218/FCH (Approx. 26.2 ms) 4 Reset pin output With reset output Without reset output Selectable Setting possible Fixed to with reset output 5 Selection either single- or dual-clock system Single clock Dual clock Selectable Setting possible Fixed to dualclock system ■ ORDERING INFORMATION Part number Package MB89647PFM MB89646PFM MB89645PFM MB89643PFM MB89P647PFM 80-pin Plastic QFP (FPT-80P-M11) MB89647PF MB89646PF MB89645PF MB89643PF MB89P647PF 80-pin Plastic QFP (FPT-80P-M06) MB89PV640CF Remarks 80-pin Ceramic MQFP (MQP-80C-P01) 55 MB89640 Series ■ PACKAGE DIMENSIONS 80-pin Plastic QFP (FPT-80P-M11) +0.20 16.00±0.20(.630±.008)SQ 14.00±0.10(.551±.004)SQ 60 1.50 –0.10 +.008 .059 –.004 41 61 40 12.35 15.00 (.486) (.591) REF NOM 1 PIN INDEX 80 LEAD No. 21 1 0.65(.0256)TYP 0.30±0.10 (.012±.004) 0.13(.005) 0.10(.004) C Details of "A" part "A" 20 M 0.127 .005 0.10±0.10 (STAND OFF) (.004±.004) +0.05 –0.02 +.002 –.001 0 10° 0.50±0.20 (.020±.008) 1994 FUJITSU LIMITED F80016S-1C-2 Dimensions in mm (inches) 56 MB89640 Series 80-pin Plastic QFP (FPT-80P-M06) 23.90±0.40(.941±.016) 64 20.00±0.20(.787±.008) 3.35(.132)MAX 0.05(.002)MIN (STAND OFF) 41 65 40 14.00±0.20 (.551±.008) 17.90±0.40 (.705±.016) 12.00(.472) REF 16.30±0.40 (.642±.016) INDEX 80 25 "A" LEAD No. 1 24 0.80(.0315)TYP 0.35±0.10 (.014±.004) 0.16(.006) 0.15±0.05(.006±.002) M Details of "A" part Details of "B" part 0.25(.010) "B" 0.10(.004) 18.40(.724)REF 22.30±0.40(.878±.016) C 0.30(.012) 0.18(.007)MAX 0.58(.023)MAX 0 10° 0.80±0.20 (.031±.008) 1994 FUJITSU LIMITED F80010S-3C-2 Dimensions in mm (inches) 57 MB89640 Series 80-pin Ceramic MQFP (MQP-80C-P01) 18.70(.736)TYP 12.00(.472)TYP INDEX AREA 16.30±0.33 (.642±.013) 15.58±0.20 (.613±.008) 1.50(.059)TYP 1.00(.040)TYP 4.50(.177) TYP 1.27±0.13 (.050±.005) 22.30±0.33 (.878±.013) 24.70(.972) TYP 0.30(.012) TYP 0.80±0.25 (.0315±.010) 0.80±0.25 (.0315±.010) +0.40 1.20 –0.20 +.016 .047 –.008 INDEX AREA 18.12±0.20 12.02(.473) (.713±.008) TYP 10.16(.400) 14.22(.560) TYP TYP 18.40(.724) REF INDEX 1.27±0.13 (.050±.005) 6.00(.236) TYP 0.30(.012)TYP 7.62(.300)TYP 9.48(.373)TYP 11.68(.460)TYP 0.40±0.10 (.016±.004) 1.50(.059) TYP 1.00(.040) TYP 0.40±0.10 (.016±.004) +0.40 1.20 –0.20 +.016 .047 –.008 0.15±0.05 8.70(.343) (.006±.002) MAX C 1994 FUJITSU LIMITED M80001SC-4-2 Dimensions in mm (inches) 58 MB89640 Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8588, Japan Tel: +81-44-754-3763 Fax: +81-44-754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. 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CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan. F0005 FUJITSU LIMITED Printed in Japan 59