FUJITSU SEMICONDUCTOR DATA SHEET DS07-12533-1E 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89610R Series MB89613R/615R ■ DESCRIPTION MB89610R series has been developed as a general-purpose version of the F2MC*-8L family of proprietary 8-bit, single-chip microcontrollers. In addition to the F2MC-8L CPU core which can operate at low voltage but at high speed, the microcontrollers contain peripheral resources such as timers, serial interfaces, and an external interrupt. The MB89610R series is applicable to a wide range of application from welfare products to industrial equipment, including portable devices. *: F2MC stands for FUJITSU Flexible Microcontroller. ■ FEATURES • Various package options Three types of QFP packages (0.5-mm, 0.65-mm, 1-mm pitch) SDIP package • High-speed processing at low voltages Minimum execution time: 0.4 µs/3.5 V and 0.8 µs/2.7 V • F2MC-8L family CPU core Instruction set optimized for controllers Multiplication and dividion instructions 16-bit arithmetic operations Test and branch instructions Bit manipulation instructions, etc. (Continued) ■ PACKAGES 64-pin Plastic SH-DIP (DIP-64P-M01) 64-pin Plastic SQFP (FPT-64P-M03) 64-pin Plastic QFP (FPT-64P-M06) 64-pin Plastic QFP (FPT-64P-M09) MB89610R Series (Continued) • Four types of timers 8-bit PWM timer (also usable a reload timer) 8-bit pulse-width count timer (Continuous measurement capable, applicable to remote control, etc) 16-bit timer/counter 20-bit time-base timer • Two serial interfaces Switchable transfer direction allows communication with various equipment. • External interrupt: 4 channels Four channels are independent and capable of wake-up from low-power consumption modes (with an edge detection function). • Low-power consumption modes Stop mode (Oscillation stops to minimize the current consumption.) Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.) • Bus interface function Including hold and ready functions ■ PRODUCT LINEUP Part number MB89613R MB89615R MB89P625/W625*1 MB89PV620*1 Parameter Classification ROM size RAM size One-time PROM product/EPROM product Mass production product (mask ROM products) 16 K × 8 bits (internal PROM, 8 K × 8 bits 16 K × 8 bits programming with (internal mask ROM) (internal mask ROM) general-purpose EPROM programmer) 256 × 8 bits 512 × 8 bits Pggyback/evaluation product (for evaluation and development) 32 K × 8 bits (external ROM) 1 K × 8 bits CPU functions Number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Interrupt processing time: 136 8 bits 1 to 3 bytes 1, 8, 16 bits 0.4 µs/10 MHz 3.6 µs/10 MHz Ports Input ports: Output ports (N-ch open-drain): I/O ports (N-ch open-drain): Output ports (CMOS): I/O ports (CMOS): Total: 5 (4 ports also serve as peripherals) 8 8 (4 ports also serve as peripherals) 8 (All also serve as bus control pins) 24 (All also serve as bus pins or peripherals) 53 8-bit PWM timer 8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 µs to 3.3 ms) 8-bit resolution PWM operation (conversion cycle: 10 µs to 839 ms) (Continued) 2 MB89610R Series (Continued) Part number MB89613R Parameter Pulse width count timer MB89615R MB89P625/W625*1 MB89PV620*1 8-bit timer operation (overflow output capable, operating clock cycle: 0.4 µs to 12.8 µs) 8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 µs to 12.8 µs) 8-bit pulse width measurement operation (continuous measurement capable: “H” pulse width/“L” pulse width/from ↑ to ↑/from ↓ to ↓) 16-bit timer operation (operating clock cycle: 0.4 µs) 16-bit event counter operation (rising edge/falling edge/both edges selectability) 16-bit timer/ counter 8-bit Serial I/O 1 8-bit Serial I/O 2 8 bits LSB first/MSB first selectability One clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 0.8 µs, 3.2 µs, 12.8 µs) External interrupt Four independent channels (edge selection, interrupt vector, and interrupt source flag) Rising edge/falling edge selectability Used also for wake-up from stop/sleep mode (edge detection is also permitted in stop mode) Standby mode Sleep mode and stop mode Process CMOS Operating voltage*2 2.2 V to 6.0 V EPROM for use 2.7 V to 6.0 V MBM27C256A-20CZ MBM27C256A-20TV — *1: One-time PROM product/EPROM product, and piggyback/evaluation product are applicable to the MB89620 series. *2: Varies with conditions such as the operating frequency (See section “■ Electrical Characteristics.”) In the case of the MB89PV620, the voltage varies with the restrictions the ICE or EPROM for use. ■ PACKAGE AND CORRESPONDING PRODUCTS Package MB89613R MB89615R MB89P625 DIP-64P-M01 DIP-64C-A06 × MB89W625 MB89PV620 × × × ×* × ×* ×* FPT64P-M06 × × FPT-64P-M09 ×* ×* FPT-64P-M03 MDP-64C-P02 × × × MQF-64C-P01 × × × : Available × : Not available * : Lead pitch converter sockets (manufacturer: Sun Hayato Co., Ltd.) are available. 64SD-64SQF-8L: For conversion from DIP-64P-M01 or DIP-64C-A06 to FPT-64P-M03 64SD-64QF2-8L: For conversion from DIP-64P-M01 or DIP-64C-A06 to FPT-64P-M09 Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760 Notes: • For more information about each package, see section “■ Package Dimensions.” • One-time PROM product/EPROM product, and piggyback/evaluation product are applicable to the MB89620 series. 3 MB89610R Series ■ DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the piggyback product, verify its differences from the product that will actually be used. Take particular care on the following points: • On the MB89613R, the upper half of the register bank cannot be used. • The stack area, etc., is set at the upper limit of the RAM. • External area is used. 2. Current Consumption • In the case of the MB89PV620, add the current consumed by the EPROM which is connected to the top socket. • When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume more current than a product with a mask ROM. • However, the current consumption in sleep/stop modes is the same. (For more information, see sections “■ Electrical Characteristics” and “■ Example Characteristics.” 3. Mask Options Functions that can be selected as options and how to designate these options vary by the product. Before using options check section “■ Mask Options.” Take particular care on the following points: • Pull-up resistor cannot be set for P40 to P47 on the MB89P625 and MB89W625. • Options are fixed on the MB89PV620. 4. Differences between the MB89610 and MB89610R Series • Memory access area Memory access area of both the MB89615 and MB89615R is the same. The access area of the MB89613 is different from that of the MB89613R when using in external bus mode. See below. Memory area Address MB89613 MB89613R 0000H to 007FH I/O area I/O area 0080H to 017FH RAM area RAM area 0180H to 027FH 0280H to BFFFH Access prohibited External area C000H to DFFFH E000H to FFFFH External area Access prohibited ROM area ROM area • Other specifications Both the MB89610 and MB89610R is the same. • Electrical specifications/electrical characteristics Electrical specifications of the MB89610R series are the same with that of the MB89610 series. For electrical characteristics, refer to the MB89620R series data sheet. 4 MB89610R Series ■ CORRESPONDENCE BETWEEN THE MB89610 AND MB89610R SERIES • The MB89610R series is the reduction version of the MB89610 series. • The MB89610 and MB89610R series consist of the following products: MB89610 series MB89613 MB89615 MB89610R series MB89613R MB89615R 5 MB89610R Series ■ PIN ASSIGNMENT (Top view) P36/WTO P37/PTO P40 P41 P42 P43 P44/BZ P45/SCK2 P46/SO2 P47/SI2 P50 P51 P52 P53 P54 P55 P56 P57 VCC N.C. VSS P60/INT0 P61/INT1 P62/INT2 P63/INT3 P64 RST MOD0 MOD1 X0 X1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VCC P35/PWC P34/EC P33/SI1 P32/SO1 P31/SCK1 P30 VSS P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/A08 P11/A09 P12/A10 P13/A11 P14/A12 P15/A13 P16/A14 P17/A15 P20/BUFC P21/HAK P22/HRQ P23/RDY P24/CLK P25/WR P26/RD P27/ALE (DIP-64P-M01) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P45/SCK2 P44/BZ P43 P42 P41 P40 P37/PTO P36/WTO VCC P35/PWC P34/EC P33/SI1 P32/SO1 P31/SCK1 P30 VSS (Top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P63/INT3 P64 RST MOD0 MOD1 X0 X1 VSS P27/ALE P26/RD P25/WR P24/CLK P23/RDY P22/HRQ P21/HAK P20/BUFC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P46/SO2 P47/SI2 P50 P51 P52 P53 P54 P55 P56 P57 VCC N.C. VSS P60/INT0 P61/INT1 P62/INT2 (FPT-64P-M03) (FPT-64P-M09) 6 P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/A08 P11/A09 P12/A10 P13/A11 P14/A12 P15/A13 P16/A14 P17/A15 MB89610R Series 64 63 62 61 60 59 58 57 56 55 54 53 52 P44/BZ P43 P42 P41 P40 P37/PTO P36/WTO VCC P35/PWC P34/EC P33/SI1 P32/SO1 P31/SCK1 (Top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 P30 VSS P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/A08 P11/A09 P12/A10 P13/A11 P14/A12 P15/A13 P16/A14 P17/A15 P20/BUFC 20 21 22 23 24 25 26 27 28 29 30 31 32 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RST MOD0 MOD1 X0 X1 VSS P27/ALE P26/RD P25/WR P24/CLK P23/RDY P22/HRQ P21/HAK P45/SCK2 P46/SO2 P47/SI2 P50 P51 P52 P53 P54 P55 P56 P57 VCC N.C. VSS P60/INT0 P61/INT1 P62/INT2 P63/INT3 P64 (FPT-64P-M06) 7 MB89610R Series ■ PIN DESCRIPTION Pin no. SHDIP*1, MDIP*2 QFP1*3 MQFP*4 SQFP*5 QFP2*6 30 23 22 X0 31 24 23 X1 28 21 20 MOD0 29 22 21 MOD1 27 20 19 RST 56 to 49 49 to 42 48 to 41 41 to 34 40 33 32 39 32 38 Circuit type Function A Crystal oscillator pins B Operating mode selection pins Connected directly to VCC or VSS. C Reset I/O pin This pin is an N-ch open-drain output type with a pull-up resistor, and a hysteresis input type. “L” is output from this pin by an internal reset source. The internal circuit is initialized by the input of “L”. 48 to 41 P00/AD0 to P07/AD7 D General-purpose I/O ports When an external bus is used, these ports function as multiplex pins of lower addresses output and data I/O. 40 to 33 P10/A08 to P17/A15 D General-purpose I/O ports When an external bus is used, these ports function as upper addresses output. P20/BUFC F General-purpose output-only port When an external bus is used, this port can also be used as a buffer control output by setting of BCTR. 31 P21/HAK F General-purpose output-only port When an external bus is used, this port can also be used as a hold acknowledge output by setting of BCTR. 31 30 P22/HRQ D General-purpose output-only port When an external bus is used, this port can also be used as a hold request input by setting of BCTR. 37 30 29 P23/RDY D General-purpose output-only port When an external bus is used, this port functions as a ready input. 36 29 28 P24/CLK F General-purpose output-only port When an external bus is used, this port functions as a clock output. 35 28 27 P25/WR F General-purpose output-only port When an external bus is used, this port functions as a write signal output. 34 27 26 P26/RD F General-purpose output-only port When an external bus is used, this port functions as a read signal output. 33 26 25 P27/ALE F General-purpose output-only port When an external bus is used, this port functions as an address latch signal output. *1: DIP-64P-M01, DIP-64C-A06 *2: MDP-64C-P02 *3: FPT-64P-M06 8 Pin name *4: MQP-64C-P01 *5: FPT-64P-M03 *6: FPT64P-M09 (Continued) MB89610R Series (Continued) Pin no. Circuit type SHDIP*1, MDIP*2 QFP1*3 MQFP*4 SQFP*5 QFP2*6 58 51 50 P30 E General-purpose I/O port This port is a hysteresis input type. 59 52 51 P31/SCK1 E General-purpose I/O port Also serves as the clock I/O for the 8-bit serial I/O 1. This port is a hysteresis input type. 60 53 52 P32/SO1 E General-purpose I/O port Also serves as the data output for the 8-bit serial I/O 1. This port is a hysteresis input type. 61 54 53 P33/SI1 E General-purpose I/O port Also serves as the data input for the 8-bit serial I/O 1. This port is a hysteresis input type. 62 55 54 P34/EC E General-purpose I/O port Also serves as the external clock input for the 16-bit timer/counter. This port is a hysteresis input type. 63 56 55 P35/PWC E General-purpose I/O port Also serves as the measured pulse input for the 8-bit pulse width count timer. This port is a hysteresis input type. 1 58 57 P36/WTO E General-purpose I/O port Also serves as the toggle output for the 8-bit pulse width count timer. This port is a hysteresis input type. 2 59 58 P37/PTO E General-purpose I/O port Also serves as the toggle output for the 8-bit PWM timer. This port is a hysteresis input type. 3 to 6 60 to 63 G N-ch open-drain I/O ports This port is a hysteresis input type. 7 64 63 P44/BZ G N-ch open-drain I/O port Also serves as the buzzer output. This port is a hysteresis input type. 8 1 64 P45/SCK2 G N-ch open-drain I/O port Also serves as the clock I/O for the 8-bit serial I/O 2. This port is a hysteresis input type. 9 2 1 P46/SO2 G N-ch open-drain I/O port Also serves as the data output for the 8-bit serial I/O 2. This port is a hysteresis input type. 10 3 2 P47/SI2 G N-ch open-drain I/O port Also serves as the data input for the 8-bit serial I/O 2. This port is a hysteresis input type. 11 to 18 4 to 11 3 to 10 P50 to P57 H N-ch open-drain output-only ports Pin name 59 to 62 P40 to P43 *1: DIP-64P-M01, DIP-64C-A06 *2: MDP-64C-P02 *3: FPT-64P-M06 Function *4: MQP-64C-P01 *5: FPT-64P-M03 *6: FPT64P-M09 (Continued) 9 MB89610R Series (Continued) Pin no. SHDIP*1, MDIP*2 QFP1*3 MQFP*4 SQFP*5 QFP2*6 22 to 25 15 to 18 14 to 17 P60/INT0 to P63/INT3 26 19 18 19, 64 12, 57 21, 32, 57 20 Circuit type Function I General-purpose input-only ports Also serve as external interrupt input. This port is a hysteresis input type. P64 I General-purpose input-only ports This port is a hysteresis input type. 11, 56 VCC — Power supply pin 14, 25, 50 13, 24, 49 VSS — Power supply (GND) pin 13 12 N.C. — Internally connected pin Be sure to leave it open. *1: DIP-64P-M01, DIP-64C-A06 *2: MDP-64C-P02 *3: FPT-64P-M06 10 Pin name *4: MQP-64C-P01 *5: FPT-64P-M03 *6: FPT64P-M09 MB89610R Series ■ I/O CIRCUIT TYPE Type Circuit A Remarks • At oscillation feedback resistor of approximately 1 MΩ/5.0 V X1 X0 Standby control signal B C • At oscillation feedback resistor of approximately 50 kΩ/5.0 V • CMOS hysteresis input R P-ch N-ch D R • CMOS output • CMOS input P-ch N-ch • Pull-up resistor optional (except P22 and P23) E R P-ch • CMOS output • Hysteresis input N-ch • Pull-up resistor optional F • CMOS output P-ch N-ch (Continued) 11 MB89610R Series (Continued) Type Circuit Remarks G • N-ch open-drain output • Hysteresis input R P-ch N-ch • Pull-up resistor optional H • N-ch open-drain output R P-ch N-ch Analog input • Pull-up resistor optional I • Hysteresis input R • Pull-up resistor optional 12 MB89610R Series ■ HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. 3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use. 4. Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. 5. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 6. Precautions when Using an External Clock Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode. 13 MB89610R Series ■ BLOCK DIAGRAM X0 X1 Oscillator 20-bit time-base timer Clock controller 8-bit PWM timer P37/PTO 8-bit pulse width count timer P 3 6 / WT O Reset circuit (WDT) 8 P10 /A08 to P1 7/A1 5 8 Port 3 P 3 5 / P WC CMOS I/O port P34/EC 16-bit timer/counter MOD0 MOD1 External bus interface Internal bus P00 /AD0 to P0 7/AD 7 Port 0 and port 1 RS T P33/SI1 P32/SO1 P31/SCK1 8-bit serial I/O 1 P30 Port 2 CMOS I/O port P47/SI2 P46/SO2 P45/SCK2 8-bit serial I/O 2 CMOS output port Port 4 P2 7/AL E P2 6/RD P2 5/WR P2 4/CL K P2 3/RD Y P2 2/HR Q P2 1/HA K P2 0/BU FC Buzzer output P44/BZ 4 P40 to P43 N-ch open-drain I/O port 8 CPU External interrupt F 2 M C- 8L Input port RO M 14 P50 to P57 N-ch open-drain output port 4 4 Port 6 RAM P60/INT0 to P63/INT3 P64 MB89610R Series ■ CPU CORE 1. Memory Space The microcontrollers of the MB89610 series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89610 series is structured as illustrated below. Memory Space 0000H MB89PV620 0000H I/O 0080H 0100H MB89613 Register I/O I/O 0080H RAM 1 KB 0000H 0080H RAM 512 B RAM 256 B 0100H 0100H Register Register 0180H 0200H MB89615 MB89P625 MB89W625 *2 0200H 0280H 0480H External area External area 8000H C000H C000H External ROM*1 32 KB External area *2 ROM*1 16 KB E000H ROM* 8 KB FFFFH FFFFH FFFFH *1: The ROM area is an external area depending on the mode. *2: Access to this area is prohibited in external bus mode. 15 MB89610R Series 2. Registers The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided: Program counter (PC): A 16-bit register for indicating instruction storage positions Accumulator (A): A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX): A 16-bit register for index modification Extra pointer (EP): A 16-bit pointer for indicating a memory address Stack pointer (SP): A 16-bit register for indicating a stack area Program status (PS): A 16-bit register for storing a register pointer, a condition code Initial value 16 bits : Program counter PC FFFDH A : Accumulator Undefined T : Temporary accumulator Undefined IX : Index register Undefined EP : Extra pointer Undefined SP : Stack pointer Undefined PS : Program status I-flag = 0, IL1, IL0 = 11 Other bits are undefined. The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) Structure of the Program Status Register 15 PS 14 13 12 RP 10 9 8 Vacancy Vacancy Vacancy RP 16 11 7 6 H I 5 4 IL1, 0 3 2 1 0 N Z V C CCR MB89610R Series The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. Rule for Conversion of Actual Addresses of the General-purpose Register Area RP Lower OP codes “0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ b1 b0 ↓ ↓ Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared otherwise. This flag is for decimal adjustment instructions. I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0 when reset. IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 IL0 Interrupt level 0 0 0 1 1 0 2 1 1 3 1 High-low High Low = no interrupt N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0. Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise. V-flag: Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does not occur. C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise. Set to the shift-out value in the case of a shift instruction. 17 MB89610R Series The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 32 banks can be used on the MB89610. In the MB89613, there are 16 banks in internal RAM. The remaining 16 banks can be extended externally by allocating an external RAM to addresses 0180H to 01FFH using an external circuit. The bank currently being in use is indicated by the register bank pointer (RP). Note: The number of register banks that can be used varies with the RAM size. Up to a total of 32 banks can be used on other than the MB89615. Register Bank Configuration This address = 0100H + 8 × (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area 18 MB89610R Series ■ I/O MAP Address Read/write Register name Register description 00H (R/W) PDR0 Port 0 data register 01H (W) DDR0 Port 0 data direction register 02H (R/W) PDR1 Port 1 data register 03H (W) DDR1 Port 1 data direction register 04H (R/W) PDR2 Port 2 data register 05H (R/W) BCTR External bus control register 06H Vacancy 07H Vacancy 08H (R/W) STBC 09H (R/W) WDTC Watchdog timer control register 0AH (R/W) TBTC Time-base timer control register 0BH 0CH Standby control register Vacancy (R/W) PDR3 Port 3 data register 0DH (W) DDR3 Port 3 data direction register 0EH (R/W) PDR4 Port 4 data register 0FH (R/W) BZCR Buzzer register 10H (R/W) PDR5 Port 5 data register 11H (R) PDR6 Port 6 data register 12H (R/W) CNTR PWM control register 13H (W) COMR PWM compare register 14H (R/W) PCR1 PWC pulse width control register 1 15H (R/W) PCR2 PWC pulse width control register 2 16H (R/W) RLBR PWM reload buffer register 17H Vacancy 18H (R/W) TMCR 19H (R/W) TCHR 16-bit timer count resister (H) 1AH (R/W) TCLR 16-bit timer count register (L) 1BH 16-bit timer control register Vacancy 1CH (R/W) 1DH (R/W) SDR1 Serial I/O 1 data register 1EH (R/W) SMR2 Serial I/O 2 mode register 1FH (R/W) SDR2 Serial I/O 2 data register SMR1 20H to 23H Serial I/O 1 mode register Vacancy 21H (R/W) EIC1 External interrupt control register 1 25H (R/W) EIC2 External interrupt control register 2 26H to 7BH Vacancy 7CH (W) ILR1 Interrupt level setting register 1 7DH (W) ILR2 Interrupt level setting register 2 7EH (W) ILR3 Interrupt level setting register 3 7FH Vacancy Note: Do not use vacancies. 19 MB89610R Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Rating (VSS = 0.0 V) Parameter Symbol Value Unit Remarks Min. Max. VCC VSS – 0.3 VSS + 7.0 V VI VSS – 0.3 VCC + 0.3 V Except P40 to P47* VI2 VSS – 0.3 VSS + 7.0 V P40 to P47 VO VSS – 0.3 VCC + 0.3 V Except P40 to P47* VO2 VSS – 0.3 VSS + 7.0 V P40 to P47 “L” level maximum output current IOL — 20 mA “L” level average output current IOLAV — 4 mA “L” level total maximum output current ΣIOL — 100 mA “L” level total average output current ΣIOLAV — 40 mA “H” level maximum output current IOH — –20 mA “H” level average output current IOHAV — –4 mA “H” level total maximum output current ΣIOH — –50 mA “H” level total average output current ΣIOHAV — –20 mA Power consumption PD — 300 mW Operating temperature TA –40 +85 °C Storage temperature Tstg –55 +150 °C Power supply voltage Input voltage Output voltage Average value (operating current × operating rate) Average value (operating current × operating rate) Average value (operating current × operating rate) Average value (operating current × operating rate) * : VI and VO must not exceed VCC + 0.3 V. Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 20 MB89610R Series 2. Recommended Operating Conditions (VSS = 0.0 V) Parameter Value Symbol Power supply voltage Unit Max. 2.2* 6.0* V Normal operation assurance range* MB89613R/615R 1.5 6.0 V Retains the RAM state in stop mode –40 +85 °C VCC Operating temperature TA Remarks Min. * : These values vary with the operating frequency. See Figure 1. 6 Operating voltage (V) 5 Operation assurance range 4 3 2 1 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 Clock operating frequency (when instruction cycle = 4/FC) (MHz) 4.0 2.0 1.3 1.0 0.8 0.66 0.57 0.5 0.44 0.4 Minimum execution time (instruction cycle) (µs) Note: The shaded area is assured only for the MB89613R/615R. Figure 1 Operating Voltage vs. Clock Operating Frequency Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FC. 21 MB89610R Series 3. DC Characteristics Parameter “H” level input voltage Symbol Pin Condition VIH P00 to P07, P10 to P17, P22, P23 — 0.7 VCC — VCC + 0.3 V VIHS RST, MOD0, MOD1, P30 to P37, P60 to P64 — 0.8 VCC — VCC + 0.3 V VIH2 P40 to P47 — 0.8 VCC — VSS + 6.0 V VIL P00 to P07, P10 to P17, P22 to P23 — VSS – 0.3 — 0.3 VCC V VILS RST, MOD0, MOD1, P30 to P37, P40 to P47, P60 to P64 — VSS – 0.3 — 0.2 VCC V VD P50 to P57 — VSS – 0.3 — VCC + 0.3 V VD2 P40 to P47 — VSS – 0.3 — VSS + 6.0 V VOH P00 to P07, P10 to P17, P20 to P27, P30 to P37 4.0 — — V VOL P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57 — — 0.4 V VOL2 RST — — 0.4 V 0.0 V < VI < VCC — — ±5 µA VI = 0.0 V 25 50 100 kΩ “L” level input voltage Open-drain output pin application voltage “H” level output voltage “L” level output voltage Input leakage current (Hi-z output leakage current) (VCC = +5.0 V, VSS = 0.0 V, TA = –40°C to +85°C) Value Unit Remarks Min. Typ. Max. ILI1 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P60 to P64, IOH = –2.0 mA IOL = +4.0 mA Without pullup resistor MOD0, MOD1 Pull-up resistance RPULL P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P64, RST (Continued) 22 MB89610R Series (Continued) (VCC = +5.0 V, VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin Value Unit Remarks 15 mA MB89613R/615R 3 4 mA — — 1 µA — 10 — pF Min. Typ. Max. FC = 10 MHz tinst*2 = 0.4 µs Normal operation mode — 9 ICCS FC = 10 MHz tinst*2 = 0.4 µs Sleep mode — ICCH TA = +25°C Stop mode f = 1 MHz ICC Power supply voltage*1 Condition VCC Input capacitance CIN Other than VCC and VSS *1: In the case of the MB89PV620, the current consumed by the connected EPROM and ICE is not included. The power supply current is measured at the external clock. *2: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.” 23 MB89610R Series 3. AC Characteristics (1) Reset Timing Parameter RST “L” pulse width Symbol (VCC = +5.0 V ±10%, VSS = 0.0 V, TA = –40°C to +85°C) Value Condition Unit Remarks Min. Max. tZLZH — 16 tXCYL* — ns * : tXCYL is the oscillation cycle (1/FC) to input to the X0 pin. tZLZH RST 0.2 VCC 0.2 VCC (2) Power-on Reset (VCC = +5.0 V ±10%, VSS = 0.0 V, TA = –40°C to +85°C) Parameter Power supply rising time Symbol Condition tR Value Unit Max. — 50 ms Power-on reset function only 1 — ms Due to repeated operation — Power supply cut-off time tOFF Remarks Min. Note: Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. tR tOFF 2.0 V VCC 24 0.2 V 0.2 V 0.2 V MB89610R Series (3) Clock Timing (VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin Condition Value Min. Max. Unit Remarks Clock frequency FC X0, X1 — 1 10 MHz Clock cycle time tXCYL X0, X1 — 100 1000 ns Input clock pulse width PWH PWL X0 — 20 — ns External clock Input clock rising/falling time tCR tCF X0 — — 10 ns External clock X0 and X1 Timing and Conditions tXCYL PWL PWH tCR 0.8 VCC tCF 0.8 VCC X0 0.2 VCC 0.2 VCC 0.2 VCC Clock Conditions When a crystal or ceramic oscillator is used X0 When an external clock is used X1 X0 X1 Open (4) Instruction Cycle Parameter Instruction cycle (minimum execution time) Symbol tinst Value (typical) Unit 4/FC µs Remarks tinst = 0.4 µs when operating at FC = 10 MHz 25 MB89610R Series (5) Clock Output Timing Parameter Symbol Cycle time tCYC CLK ↑ → CLK ↓ tCHCL Pin Condition CLK (VCC = +5.0 V±10%, VSS = 0.0 V, TA = –40°C to +85°C) Values Unit Remarks Min. Max. 200 — ns tXCYL × 2 at 10 MHz oscillation 30 100 ns Approx. tCYC/2 at 10 MHz oscillation — tCYC tCHCL 2.4 V 2.4 V CLK 0.8 V 26 MB89610R Series (6) Bus Read Timing Parameter (VCC = +5.0 V±10%, FC = 10 MHz, VSS = 0.0 V, TA = –40°C to +85°C) Value Pin Condition Unit Remarks Min. Max. Symbol Valid address → RD ↓ tAVRL time RD, A15 to 08 AD7 to 0 1/4 tinst* – 64 ns — µs RD pulse width tRLRH RD 1/2 tinst* – 20 ns — µs Valid address → read data time tAVDV AD7 to 0, A15 to 08 — 1/2 tinst* µs No wait RD ↓ → read data time tRLDV RD, AD7 to 0 — 1/2 tinst* – 80 ns µs No wait RD ↑ → data hold time tRHDX AD7 to 0, RD 0 — ns RD ↑ → ALE ↑ time tRHLH RD, ALE 1/4 tinst* – 40 ns — µs RD ↑ → address invalid time tRHAX RD, A15 to 08 1/4 tinst* – 40 ns — µs RD ↓ → CLK ↑ time tRLCH 1/4 tinst* – 40 ns — µs CLK ↓ → RD ↑ time tCLRH 0 — ns RD ↓ → BUFC ↓ time tRLBL RD, BUFC –5 — µs BUFC ↑ → valid address time tBHAV A15 to 08, AD7 to 0, BUFC 5 — µs — RD, CLK * : For information on tinst, see “(4), Instruction Cycle.” 2.4 V CLK 0.8 V tRHLH ALE 0.8 V 2.4 V 0.7 VCC 0.7 VCC 2.4 V 0.8 V 0.3 VCC 0.3 VCC 0.8 V AD tRHDX tAVDV 2.4 V A 2.4 V tCLRH 0.8 V tRLCH 0.8 V tAVRL tRLDV 2.4 V 0.8 V tRHAX tRLRH 2.4 V RD 0.8 V tRLBL tRHAV 2.4 V BUFC 0.8 V 27 MB89610R Series (7) Bus Write Timing (VCC = +5.0 V±10%, FC = 10 MHz, VSS = 0.0 V, TA = –40°C) Parameter Symbol Pin Value Condition Valid address → ALE ↓ time tAVLL ALE ↓ time → address invalid time tLLAX AD7 to 0, ALE, A15 to 08 Valid address → WR ↓ time tAVWL WR, ALE WR pulse width tWLWH Write data → WR ↑ time Max. 1/4 tinst* – 64 ns*2 — µs 5*2 — ns 1/4 tinst* – 60 ns*2 — µs WR 1/2 t *2 — µs tDVWH AD7 to 0, WR 1/2 tinst* – 60 ns*2 — µs WR ↑ → address invalid time tWHAX WR, A15 to 08 1/4 tinst* – 40 ns*2 — µs WR ↑ → data hold time tWHDX AD7 to 0, WR 1/4 tinst* – 40 ns*2 — µs WR ↑ → ALE ↑ time tWHLH WR, ALE 1/4 tinst* – 40 ns*2 — µs WR ↓ → CLK ↑ time tWLCH WR, CLK 1/4 tinst* – 40 ns*2 — µs CLK ↓ → WR ↑ time tCLWH WR, CLK 0 ALE pulse width tLHLL ALE ALE ↓ → CLK ↑ time tLLCH ALE, CLK — inst* 1/4 t inst* 1/4 t inst* – 20 ns — ns – 35 ns *2 — µs – 30 ns *2 — µs *1: For information on tinst, see “(4) Instruction Cycle.” *2: These characteristics are also applicable to the bus read timing. 2.4 V CLK tLHLL ALE tLLCH tWHLH 2.4 V 0.8 V 0.8 V tLLAX tAVLL 2.4 V 2.4 V 2.4 V 2.4 V 0.8 V 0.8 V 0.8 V 0.8 V AD tDVWH 2.4 V A tWHDX 2.4 V tCLWH 0.8 V tWLCH 0.8 V tAVWL tWHAX tWLWH 2.4 V WR 0.8 V 28 Unit Min. Remarks MB89610R Series (8) Ready Input Timing (VCC = +5.0 V±10%, FC = 10 MHz, VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol RDY valid → CLK ↑ time tYVCH CLK ↑ → RDY invalid time tCHYX Pin Values Condition RDY, CLK — Unit Remarks Min. Max. 60 — ns * 0 — ns * * : These characteristics are also applicable to the read cycle. 2.4 V CLK 2.4 V ALE AD Data Address A WR tYVCH tCHYX 2.4 V 2.4 V RDY 0.8 V 0.8 V tYVCH tCHYX Note: The bus cycle is also extended in the read cycle in the same manner. 29 MB89610R Series (9) Serial I/O Timing (VCC = +5.0 V±10%, FC = 10 MHz, VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin Value Min. Max. Unit Serial clock cycle time tSCYC SCK1, SCK2 2 tinst* — µs SCK1 ↓ → SO1 time SCK2 ↓ → SO2 time tSLOV SCK1, SO1 SCK2, SO2 –200 200 ns 1/2 tinst* — µs 1/2 tinst* — µs 1 tinst* — µs 1 tinst* — µs 0 200 ns SCK1 ↑ → valid SI1 hold time tSHIX SCK2 ↑ → valid SI2 hold time SCK1, SI1 SCK2, SI2 Valid SI1 → SCK1 ↑ Valid SI2 → SCK2 ↑ tIVSH SI1, SCK1 SI2, SCK2 Serial clock “H” pulse width tSHSL Serial clock “L” pulse width tSLSH SCK ↓ → SO1 time SCK2 ↓ → SO2 time tSLOV Internal shift clock mode SCK1, SCK2 SCK1, SO1 SCK2, SO2 External shift clock mode SCK1 ↑ → valid SI1 hold time tSHIX SCK2 ↑ → valid SI2 hold time SCK1, SI1 SCK2, SI2 1/2 tinst* — µs Valid SI1 → SCK1 ↑ Valid SI2 → SCK2 ↑ SI1, SCK1 SI2, SCK2 1/2 tinst* — µs tIVSH * : For information on tinst, see “(4) Instruction Cycle.” 30 Condition Remarks MB89610R Series Internal Shift Clock Mode tSCYC 2.4 V SCK1 SCK2 0.8 V 0.8 V tSLOV 2.4 V SO1 SO2 0.8 V t IVSH SI1 SI2 tSHIX 0.8 Vcc 0.8 Vcc 0.2 Vcc 0.2 Vcc External Shift Clock Mode tSLSH tSHSL SCK2 0.8 VCC 0.8 VCC SCK1 0.2 VCC 0.2 VCC tSLOV SO1 SO2 2.4 V 0.8 V tIVSH SI1 SI2 tSHLX 0.8 VCC 0. 8 VCC 0.2 VCC 0.2 VCC 31 MB89610R Series (10) Peripheral Input Timing (VCC = +5.0 V ±10%, VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Peripheral input “H” level pulse width 1 tILIH1 Peripheral input “L” level pulse width 2 tIHIL1 Pin PWC, EC, INT0 to INT3 Condition Value Max. 2 tinst* — µs 2 tinst* — µs — * : For information on tinst, see “(4) Instruction Cycle.” tIHIL1 PWC, EC, INT0 to 3 32 tILIH1 0.8 VCC 0.2 VCC Unit Min. 0.2 VCC 0.8 VCC Remarks MB89610R Series ■ EXAMPLE CHARACTERISTICS (1) “L” Level Output Voltage (2) VOL vs. IOL VOL (V) VCC = 2.5 V TA = +25°C 0.5 “H” Level Output Voltage VCC – VOH vs. IOH VCC – VOH (V) 1.0 0.9 VCC = 2.5 V TA = +25°C 0.8 VCC = 3.0 V 0.7 0.4 0.3 VCC = 3.0 V 0.6 VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V 0.5 VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V 0.4 0.2 0.3 0.2 0.1 0.1 0.0 (3) 0 1 2 3 4 5 6 7 8 9 0.0 0.0 10 IOL (mA) “H” Level Input Voltage/“L” Level Input Voltage (CMOS Input) (4) –0.5 4.5 TA = +25°C 4.0 3.5 3.5 3.0 3.0 2.5 2.5 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 1 2 3 4 5 6 7 VCC (V) –2.0 –2.5 –3.0 IOH (mA) VIN vs. VCC VIN (V) 5.0 4.5 4.0 0 –1.5 “H” level Input Voltage/“L” Level Input Voltage (Hysteresis Input) VIN vs. VCC VIN (V) 5.0 0.0 –1.0 0.0 TA = +25°C VIHS VILS 0 1 2 3 4 5 6 7 VCC (V) VIHS: Threshold when input voltage in hysteresis characteristics is set to “H” level VILS: Threshold when input voltage in hysteresis characteristics is set to “L” level 33 MB89610R Series (5) Power Supply Current (External Clock) ICCS vs. VCC ICC vs. VCC ICC (mA) 16 ICCS (mA) 5 TA = +25°C TA = +25°C 14 FC = 10 MHz 12 FC = 8 MHz 10 FC = 10 MHz 4 FC = 8 MHz 3 8 FC = 4 MHz 6 2 FC = 4 MHz 4 1 FC = 1 MHz 2 FC = 1 MHz 0 0 1 3 2 4 5 6 7 VCC (V) (6) Pull-up Resistance RPULL vs. VCC RPULL (kΩ) 1000 TA = +25°C 100 10 34 1 2 3 4 5 6 VCC (V) 1 2 3 4 5 6 7 VCC (V) MB89610R Series ■ INSTRUCTIONS Execution instructions can be divided into the following four groups: • • • • Transfer Arithmetic operation Branch Others Table 1 lists symbols used for notation of instructions. Table 1 Instruction Symbols Symbol Meaning dir Direct address (8 bits) off Offset (8 bits) ext Extended address (16 bits) #vct Vector table number (3 bits) #d8 Immediate data (8 bits) #d16 Immediate data (16 bits) dir: b Bit direct address (8:3 bits) rel Branch relative address (8 bits) @ Register indirect (Example: @A, @IX, @EP) A Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) AH Upper 8 bits of accumulator A (8 bits) AL Lower 8 bits of accumulator A (8 bits) T Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) TH Upper 8 bits of temporary accumulator T (8 bits) TL Lower 8 bits of temporary accumulator T (8 bits) IX Index register IX (16 bits) (Continued) 35 MB89610R Series (Continued) Symbol Meaning EP Extra pointer EP (16 bits) PC Program counter PC (16 bits) SP Stack pointer SP (16 bits) PS Program status PS (16 bits) dr Accumulator A or index register IX (16 bits) CCR Condition code register CCR (8 bits) RP Register bank pointer RP (5 bits) Ri General-purpose register Ri (8 bits, i = 0 to 7) × Indicates that the very × is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) (×) Indicates that the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) (( × )) The address indicated by the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Columns indicate the following: Mnemonic: Assembler notation of an instruction ~: Number of instructions #: Number of bytes Operation: Operation of an instruction TL, TH, AH: A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: • “–” indicates no change. • dH is the 8 upper bits of operation description data. • AL and AH must become the contents of AL and AH immediately before the instruction is executed. • 00 becomes 00. N, Z, V, C: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. OP code: Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F ← This indicates 48, 49, ... 4F. 36 MB89610R Series Table 2 Transfer Instructions (48 instructions) Mnemonic ~ # Operation TL TH AH NZVC OP code MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 – – – – – AL AL AL AL AL AL AL – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –––– –––– –––– –––– –––– ++–– ++–– ++–– ++–– ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 MOVW ext,A MOVW @EP,A MOVW EP,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off 5 4 2 3 4 5 3 1 1 3 2 2 – – – AL AL AL – – – AH AH AH – – – dH dH dH –––– –––– –––– ++–– ++–– ++–– D4 D7 E3 E4 C5 C6 MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP,#d16 MOVW IX,A MOVW A,IX MOVW SP,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ← (A) ( (IX) +off ) ← (A) (ext) ← (A) ( (EP) ) ← (A) (Ri) ← (A) (A) ← d8 (A) ← (dir) (A) ← ( (IX) +off) (A) ← (ext) (A) ← ( (A) ) (A) ← ( (EP) ) (A) ← (Ri) (dir) ← d8 ( (IX) +off ) ← d8 ( (EP) ) ← d8 (Ri) ← d8 (dir) ← (AH),(dir + 1) ← (AL) ( (IX) +off) ← (AH), ( (IX) +off + 1) ← (AL) (ext) ← (AH), (ext + 1) ← (AL) ( (EP) ) ← (AH),( (EP) + 1) ← (AL) (EP) ← (A) (A) ← d16 (AH) ← (dir), (AL) ← (dir + 1) (AH) ← ( (IX) +off), (AL) ← ( (IX) +off + 1) (AH) ← (ext), (AL) ← (ext + 1) (AH) ← ( (A) ), (AL) ← ( (A) ) + 1) (AH) ← ( (EP) ), (AL) ← ( (EP) + 1) (A) ← (EP) (EP) ← d16 (IX) ← (A) (A) ← (IX) (SP) ← (A) (A) ← (SP) ( (A) ) ← (T) ( (A) ) ← (TH),( (A) + 1) ← (TL) (IX) ← d16 (A) ← (PS) (PS) ← (A) (SP) ← d16 (AH) ↔ (AL) (dir): b ← 1 (dir): b ← 0 (AL) ↔ (TL) (A) ↔ (T) (A) ↔ (EP) (A) ↔ (IX) (A) ↔ (SP) (A) ← (PC) AL AL AL – – – – – – – – – – – – – – – AL AL – – – – AH AH AH – – – – – – – – – – – – – – – – AH – – – – dH dH dH dH – – dH – dH – – – dH – – AL – – – dH dH dH dH dH ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– ++++ –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0 Notes: • During byte transfer to A, T ← A is restricted to low bytes. • Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family) 37 MB89610R Series Table 3 Mnemonic ~ # ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ROLC A 2 1 CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Arithmetic Operation Instructions (62 instructions) Operation TL TH AH NZVC OP code (A) ← (A) + (Ri) + C (A) ← (A) + d8 + C (A) ← (A) + (dir) + C (A) ← (A) + ( (IX) +off) + C (A) ← (A) + ( (EP) ) + C (A) ← (A) + (T) + C (AL) ← (AL) + (TL) + C (A) ← (A) − (Ri) − C (A) ← (A) − d8 − C (A) ← (A) − (dir) − C (A) ← (A) − ( (IX) +off) − C (A) ← (A) − ( (EP) ) − C (A) ← (T) − (A) − C (AL) ← (TL) − (AL) − C (Ri) ← (Ri) + 1 (EP) ← (EP) + 1 (IX) ← (IX) + 1 (A) ← (A) + 1 (Ri) ← (Ri) − 1 (EP) ← (EP) − 1 (IX) ← (IX) − 1 (A) ← (A) − 1 (A) ← (AL) × (TL) (A) ← (T) / (AL),MOD → (T) (A) ← (A) ∧ (T) (A) ← (A) ∨ (T) (A) ← (A) ∀ (T) (TL) − (AL) (T) − (A) → C→A – – – – – – – – – – – – – – – – – – – – – – – dL – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 00 – – – – – – – – – – – dH – – – – – – dH – – – – dH – – – dH dH 00 dH dH dH – – – ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++– –––– –––– ++–– +++– –––– –––– ++–– –––– –––– ++R– ++R– ++R– ++++ ++++ ++–+ 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 C ← A← – – – ++–+ 02 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65 (A) − d8 (A) − (dir) (A) − ( (EP) ) (A) − ( (IX) +off) (A) − (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) ← (AL) ∀ (TL) (A) ← (AL) ∀ d8 (A) ← (AL) ∀ (dir) (A) ← (AL) ∀ ( (EP) ) (A) ← (AL) ∀ ( (IX) +off) (A) ← (AL) ∀ (Ri) (A) ← (AL) ∧ (TL) (A) ← (AL) ∧ d8 (A) ← (AL) ∧ (dir) (Continued) 38 MB89610R Series (Continued) Mnemonic ~ # AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 Operation (A) ← (AL) ∧ ( (EP) ) (A) ← (AL) ∧ ( (IX) +off) (A) ← (AL) ∧ (Ri) (A) ← (AL) ∨ (TL) (A) ← (AL) ∨ d8 (A) ← (AL) ∨ (dir) (A) ← (AL) ∨ ( (EP) ) (A) ← (AL) ∨ ( (IX) +off) (A) ← (AL) ∨ (Ri) (dir) – d8 ( (EP) ) – d8 ( (IX) + off) – d8 (Ri) – d8 (SP) ← (SP) + 1 (SP) ← (SP) – 1 TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++++ ++++ ++++ ++++ –––– –––– 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1 Table 4 Branch Instructions (17 instructions) Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI ~ # 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 Operation If Z = 1 then PC ← PC + rel If Z = 0 then PC ← PC + rel If C = 1 then PC ← PC + rel If C = 0 then PC ← PC + rel If N = 1 then PC ← PC + rel If N = 0 then PC ← PC + rel If V ∀ N = 1 then PC ← PC + rel If V ∀ N = 0 then PC ← PC + reI If (dir: b) = 0 then PC ← PC + rel If (dir: b) = 1 then PC ← PC + rel (PC) ← (A) (PC) ← ext Vector call Subroutine call (PC) ← (A),(A) ← (PC) + 1 Return from subrountine Return form interrupt TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – dH – – –––– –––– –––– –––– –––– –––– –––– –––– –+–– –+–– –––– –––– –––– –––– –––– –––– Restore FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30 TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – dH – – – – – – – –––– –––– –––– –––– –––– –––R –––S –––– –––– 40 50 41 51 00 81 91 80 90 Table 5 Other Instructions (9 instructions) Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI ~ # 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Operation 39 L 40 B C D E F MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP,#d16 A,SP 5 ADDC A SUBC A XCH XOR AND OR A, T A A A MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP,A A,SP MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BNZ A,R4 A,R4 A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel R4 R4 #4 rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BZ A,R5 A,R5 A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel R5 R5 #5 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BGE A,R6 A,R6 A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel R6 R6 #6 rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BLT A,R7 A,R7 A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel R7 R7 #7 rel D E F rel rel rel rel CLRB BBC MOVW MOVW MOVW XCHW dir: 7 dir: 7,rel A,@EP @EP,A EP,#d16 A,EP C CMP @EP,#d8 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BN A,R3 A,R3 A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel R3 R3 #3 MOVW XCHW IX,#d16 A,IX B MOVW MOVW A,@IX +d @IX +d,A MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BP A,R2 A,R2 A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel R2 R2 #2 CLRB BBC dir: 6 dir: 6,rel A MOV @EP,#d8 MOV CMP @IX +d,#d8 @IX +d,#d8 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BC A,R1 A,R1 A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel R1 R1 #1 OR A,@IX +d 9 XOR AND A,@IX +d A,@IX +d MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BNC A,R0 A,R0 A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel R0 R0 #0 rel MOV @IX +d,A 8 SUBC A,@IX +d MOV CMP ADDC SUBC MOV XOR AND OR A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP ADDC A,@IX +d 7 CMP A,@IX +d CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC MOV A,@IX +d DAS 6 XOR AND OR DAA A,#d8 A,#d8 A,#d8 MOVW MOVW CLRB BBC INCW DECW MOVW MOVW CMPW ADDCW SUBCW XCHW XORW ANDW ORW A A A, T A A A @A,T A,@A dir: 3 dir: 3,rel EP EP EP,A A,EP A A SETC 4 A CMP PUSHW POPW MOV MOVW CLRC JMP CALL IX IX ext,A PS,A addr16 addr16 RORC A DIVU 3 CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC A ROLC A SETI 7 PUSHW POPW MOV MOVW CLRI A A A,ext A,PS 6 9 5 8 4 2 A RETI 3 MULU RET 2 1 SWAP 1 NOP 0 0 H MB89610R Series ■ INSTRUCTION MAP MB89610R Series ■ MASK OPTIONS Part number MB89613R MB89615R MB89P625 MB89W625 MB89PV620 Specifying procedure Specify when ordering masking Set with EPROM programmer Setting not possible No. Selectable per pin Can be set per pin. (P40 to P47 are available only for without pull-up resistor.) Fixed to without pullup resistor Power-on reset selection With power-on reset Without power-on reset Selectable Setting possible Fixed to with poweron reset 3 Oscillation stabilization time Selection Crystal oscillator (218/FC(s)) Ceramic oscillator (214/FC(s)) Selectable Setting possible Crystal oscillator (218/FC(s)) 4 Reset pin output With reset output Without reset output Selectable Setting possible Fixed to with reset output 1 Pull-up resistors P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P64 2 ■ ORDERING INFORMATION Part number MB89613RP-SH MB89615RP-SH Package Remarks 64-pin Plastic SH-DIP (DIP-64P-M01) MB89613RPF MB89615RPF 64-pin Plastic QFP (FPT-64P-M06) Lead pitch: 1.0 mm MB89613RPFM MB89615RPFM 64-pin Plastic QFP (FPT-64P-M09) Lead pitch: 0.65 mm MB89613RPFV MB89615RPFV 64-pin Plastic SQFP (FPT-64P-M03) Lead pitch: 0.5 mm 41 MB89610R Series ■ PACKAGE DIMENSIONS 64-pin Plastic SH-DIP (DIP-64P-M01) +0.22 58.00 –0.55 +.008 2.283 –.022 INDEX-1 17.00±0.25 (.669±.010) INDEX-2 5.65(.222)MAX 0.25±0.05 (.010±.002) 3.00(.118)MIN +0.50 1.00 –0 +.020 .039 –0 0.51(.020)MIN 0.45±0.10 (.018±.004) 15°MAX 19.05(.750) TYP 1.778±0.18 (.070±.007) 55.118(2.170)REF 1.778(.070) MAX C 1994 FUJITSU LIMITED D64001S-3C-4 Dimensions in mm (inches) 64-pin Plastic QFP (FPT-64P-M06) 24.70±0.40(.972±.016) 3.35(.132)MAX 20.00±0.20(.787±.008) 51 0.05(.002)MIN (STAND OFF) 33 52 32 14.00±0.20 (.551±.008) 18.70±0.40 (.736±.016) 12.00(.472) REF 16.30±0.40 (.642±.016) INDEX 20 64 "A" LEAD No. 1 19 1.00(.0394) TYP 0.40±0.10 (.016±.004) 0.15±0.05(.006±.002) 0.20(.008) M Details of "A" part 0.25(.010) Details of "B" part "B" 0.10(.004) 18.00(.709)REF 22.30±0.40(.878±.016) C 1994 FUJITSU LIMITED F64013S-3C-2 0.30(.012) 0.18(.007)MAX 0.63(.025)MAX 0 10° 1.20±0.20 (.047±.008) Dimensions in mm (inches) 43 MB89610R Series 64-pin Plastic QFP (FPT-64P-M09) 14.00±0.20(.551±.008)SQ 48 33 12.00±0.10(.472±.004)SQ 49 +0.20 1.50 –0.10 +.008 .059 –.004 32 9.75 (.384) REF 13.00 (.512) NOM 1 PIN INDEX 64 17 LEAD No. 1 Details of "A" part 16 0.65(.0256)TYP 0.30±0.10 (.012±.004) "A" 0.13(.005) M +0.05 0.127 –0.02 +.002 .005 –.001 0.10±0.10 (STAND OFF) (.004±.004) 0.10(.004) 0 C 1994 FUJITSU LIMITED F64018S-1C-2 10° 0.50±0.20 (.020±.008) Dimensions in mm (inches) 64-pin Plastic SQFP (FPT-64P-M03) +0.20 1.50 –0.10 +.008 .059 –.004 12.00±0.20(.472±.008)SQ 10.00±0.10(.394±.004)SQ 48 33 49 32 7.50 (.295) REF 11.00 (.433) NOM INDEX 64 LEAD No. Details of "A" part 17 1 16 0.50±0.08 (.0197±.0031) "A" +0.08 0.18 –0.03 +.003 .007 –.001 +0.05 0.127 –0.02 +.002 .005 –.001 0.10±0.10 (STAND OFF) (.004±.004) 0.50±0.20 (.020±.008) 0.10(.004) C 44 1994 FUJITSU LIMITED F64009S-2C-4 0 10° Dimensions in mm (inches) MB89610R Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3753 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281 0770 Fax: (65) 281 0220 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan. F9703 FUJITSU LIMITED 48 Printed in Japan