ISSI IS62LV256AL-45JI 32k x 8 low voltage cmos static ram Datasheet

IS65LV256AL
IS62LV256AL
ISSI
®
32K x 8 LOW VOLTAGE
CMOS STATIC RAM
MARCH 2006
FEATURES
• High-speed access time: 20, 45 ns
• Automatic power-down when chip is deselected
• CMOS low power operation
— 17 µW (typical) CMOS standby
— 50 mW (typical) operating
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three-state outputs
• Industrial and Automotive temperatures available
• Lead-free available
DESCRIPTION
The ISSI IS62/65LV256AL is a very high-speed, low
power, 32,768-word by 8-bit static RAM. It is fabricated
using ISSI's high-performance CMOS technology. This
highly reliable process coupled with innovative circuit
design techniques, yields access times as fast as 15 ns
maximum.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation is reduced to
150 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using an active
LOW Chip Enable (CE). The active LOW Write Enable
(WE) controls both writing and reading of the memory.
The IS62/65LV256AL is available in the JEDEC standard
28-pin SOJ, 28-pin SOP, and the 28-pin 450-mil TSOP
package.
FUNCTIONAL BLOCK DIAGRAM
A0-A14
DECODER
32K x 8
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VDD
GND
I/O0-I/O7
CE
OE
WE
CONTROL
CIRCUIT
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
03/17/06
1
IS65LV256AL
IS62LV256AL
ISSI
PIN CONFIGURATION
PIN CONFIGURATION
28-Pin SOJ/ 28-pin SOP
28-Pin TSOP
A14
1
28
VDD
A12
2
27
WE
A7
3
26
A13
A6
4
25
A8
A5
5
24
A9
A4
6
23
A11
A3
7
22
OE
A2
8
21
A10
A1
9
20
CE
A0
10
19
I/O7
I/O0
11
18
I/O6
I/O1
12
17
I/O5
I/O2
13
16
I/O4
GND
14
15
I/O3
PIN DESCRIPTIONS
OE
A11
A9
A8
A13
WE
VDD
A14
A12
A7
A6
A5
A4
A3
21
20
19
18
17
16
15
14
13
12
11
10
9
8
22
23
24
25
26
27
28
1
2
3
4
5
6
7
®
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
TRUTH TABLE
A0-A14
Address Inputs
Mode
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Input/Output
Not Selected
(Power-down)
Output Disabled
Read
Write
VDD
Power
GND
Ground
WE
CE
OE
I/O Operation
VDD Current
X
H
X
High-Z
ISB1, ISB2
H
H
L
L
L
L
H
L
X
High-Z
DOUT
DIN
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TBIAS
TSTG
PT
IOUT
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–0.5 to +4.6
–55 to +125
–65 to +150
0.5
20
Unit
V
°C
°C
W
mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
03/17/06
IS65LV256AL
IS62LV256AL
ISSI
®
OPERATING RANGE
Part No.
IS62LV256AL
IS62LV256AL
IS65LV256AL
Range
Commercial
Industrial
Automotive
Ambient Temperature
0°C to +70°C
–40°C to +85°C
–40°C to +125°C
VDD
3.3V +10%
3.3V ± 10%
3.3V ± 10%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
VDD = Min., IOH = –2.0 mA
2.4
—
V
VOL
Output LOW Voltage
VDD = Min., IOL = 4.0 mA
—
0.4
V
VIH
Input HIGH Voltage
2.2
VDD + 0.3
V
–0.3
0.8
V
(1)
VIL
Input LOW Voltage
ILI
Input Leakage
GND ≤ VIN ≤ VDD
Com.
Ind.
Auto.
–1
–2
–10
1
2
10
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VDD, Outputs Disabled
Com.
Ind.
Auto.
–1
–2
–10
1
2
10
µA
Notes:
1. VIL = –3.0V for pulse width less than 10 ns.
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
03/17/06
3
IS65LV256AL
IS62LV256AL
ISSI
®
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-20 ns
Min. Max.
-45 ns
Min. Max.
Symbol Parameter
Test Conditions
ICC1
VDD Operating
Supply Current
VDD = Max., CE = VIL
IOUT = 0 mA, f = 1 MHz
Com.
Ind.
Auto.
—
—
—
4
5
—
—
—
—
4
5
8
mA
ICC2
VDD Dynamic Operating
Supply Current
VDD = Max., CE = VIL
IOUT = 0 mA, f = fMAX
Com.
Ind.
Auto.
typ.(2)
—
—
—
20
25
—
—
—
—
10
12
20
mA
15
Unit
7
ISB1
TTL Standby Current
(TTL Inputs)
VDD = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = 0
Com.
Ind.
Auto.
—
—
—
1.5
1.8
—
—
—
—
1.5
1.8
2
mA
ISB2
CMOS Standby
Current (CMOS Inputs)
VDD = Max.,
CE ≤ VDD – 0.2V,
VIN > VDD – 0.2V, or
VIN ≤ 0.2V, f = 0
Com.
Ind.
Auto.
typ.(2)
—
—
—
15
20
—
—
—
—
15
20
50
µA
2
2
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD = 3.3V, TA = 25oC and not 100% tested.
CAPACITANCE(1,2)
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Conditions
Max.
Unit
VIN = 0V
6
pF
VOUT = 0V
5
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
03/17/06
IS65LV256AL
IS62LV256AL
ISSI
®
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
-20 ns
Min. Max.
Parameter
-45 ns
Min. Max.
Unit
tRC
Read Cycle Time
20
—
45
—
ns
tAA
Address Access Time
—
20
—
45
ns
tOHA
Output Hold Time
2
—
2
—
ns
tACE
CE Access Time
—
20
—
45
ns
OE Access Time
—
10
—
25
ns
tDOE
OE to Low-Z Output
0
—
0
—
ns
(2)
tHZOE
OE to High-Z Output
—
9
0
20
ns
(2)
tLZCE
CE to Low-Z Output
3
—
3
—
ns
tHZCE(2)
CE to High-Z Output
—
9
0
20
ns
tPU
CE to Power-Up
0
—
0
—
ns
tPD
CE to Power-Down
—
18
—
30
ns
tLZOE
(2)
(3)
(3)
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
635 Ω
635 Ω
3.3V
3.3V
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
Figure 1.
702 Ω
5 pF
Including
jig and
scope
Figure 2.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
03/17/06
702 Ω
5
IS65LV256AL
IS62LV256AL
ISSI
®
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
tRC
ADDRESS
tAA
tOHA
tOHA
DOUT
DATA VALID
READ CYCLE NO. 2(1,3)
tRC
ADDRESS
tAA
tOHA
OE
tDOE
CE
tLZOE
tACE
tLZCE
DOUT
tHZCE
HIGH-Z
DATA VALID
tPU
SUPPLY
CURRENT
tHZOE
tPD
50%
ICC
50%
ISB
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
03/17/06
IS65LV256AL
IS62LV256AL
ISSI
®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
Symbol
-20 ns
Min.
Max.
Parameter
-45 ns
Min.
Max.
Unit
tWC
Write Cycle Time
20
—
45
—
ns
tSCE
CE to Write End
15
—
35
—
ns
tAW
Address Setup Time to Write End
14
—
25
—
ns
tHA
Address Hold from Write End
0
—
0
—
ns
Address Setup Time
0
—
0
—
ns
tPWE
WE Pulse Width
14
—
25
—
ns
tSD
Data Setup to Write End
13
—
20
—
ns
tHD
Data Hold from Write End
0
—
0
—
ns
tHZWE(2)
WE LOW to High-Z Output
—
8
—
20
ns
tLZWE
WE HIGH to Low-Z Output
0
—
0
—
ns
tSA
(4)
(2)
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
4. Tested with OE HIGH.
AC WAVEFORMS
WE Controlled)(1,2)
WRITE CYCLE NO. 1 (WE
tWC
ADDRESS
tHA
tSCE
CE
tAW
tPWE
WE
tSA
DOUT
tHZWE
DATA UNDEFINED
tLZWE
HIGH-Z
tSD
DIN
DATA-IN VALID
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
03/17/06
tHD
7
IS65LV256AL
IS62LV256AL
ISSI
®
CE Controlled)(1,2)
WRITE CYCLE NO. 2 (CE
tWC
ADDRESS
tSA
tHA
tSCE
CE
tAW
tPWE
WE
tHZWE
DOUT
DATA UNDEFINED
tLZWE
HIGH-Z
tSD
DIN
tHD
DATA-IN VALID
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE ≥ VIH.
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
03/17/06
IS65LV256AL
IS62LV256AL
ISSI
®
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter
Test Condition
Min.
2.0
VDR
VDD for Data Retention
See Data Retention Waveform
IDR
Data Retention Current
VDD = 2.0V, CE ≥ VDD – 0.2V
VIN ≥ VDD – 0.2V, or VIN ≤ VSS + 0.2V
tSDR
Data Retention Setup Time See Data Retention Waveform
tRDR
Recovery Time
Com.
Ind.
Auto.
typ.(1)
See Data Retention Waveform
Max.
Unit
3.6
V
15
20
50
µA
0
—
ns
tRC
—
ns
—
—
—
Typ.
—
—
—
2
Note:
1. Typical Values are measured at VDD = 3.3V, TA = 25oC and not 100% tested.
CE Controlled)
DATA RETENTION WAVEFORM (CE
tSDR
Data Retention Mode
tRDR
VDD
VDR
CE
GND
CE ≥ VDD - 0.2V
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
03/17/06
9
IS65LV256AL
IS62LV256AL
ISSI
®
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns)
Order Part No.
Package
20
IS62LV256AL-20T
IS62LV256AL-20TL
IS62LV256AL-20J
IS62LV256AL-20JL
450-mil
450-mil
300-mil
300-mil
45
IS62LV256AL-45T
IS62LV256AL-45TL
IS62LV256AL-45J
450-mil TSOP
450-mil TSOP, Lead-free
300-mil Plastic SOJ
TSOP
TSOP, Lead-free
Plastic SOJ
Plastic SOJ, Lead-free
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part No.
Package
20
IS62LV256AL-20TI
IS62LV256AL-20TLI
IS62LV256AL-20JI
IS62LV256AL-20JLI
450-mil
450-mil
300-mil
300-mil
45
IS62LV256AL-45TI
IS62LV256AL-45TLI
IS62LV256AL-45JI
IS62LV256AL-45UI
IS62LV256AL-45ULI
450-mil TSOP
450-mil TSOP, Lead-free
300-mil Plastic SOJ
330-mil Plastic SOP
330-mil Plastic SOP, Lead-free
TSOP
TSOP, Lead-free
Plastic SOJ
Plastic SOJ, Lead-free
Automotive Range: –40°C to +125°C
Speed (ns)
45
10
Order Part No.
Package
IS65LV256AL-45TA3
IS65LV256AL-45TLA3
IS65LV256AL-45UA3
IS65LV256AL-45ULA3
450-mil
450-mil
330-mil
330-mil
TSOP
TSOP, Lead-free
Plastic SOP
Plastic SOP, Lead-free
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
03/17/06
ISSI
PACKAGING INFORMATION
Plastic TSOP - 28-pins
Package Code: T (Type I)
1
E
H
N
D
SEATING PLANE
A
S
B
e
Symbol
Ref. Std.
No. Leads
A
A1
B
C
D
E
H
e
L
α
α
C
Plastic TSOP (T—Type I)
Millimeters
Inches
Min
Max
Min
Max
28
1.00
1.20
0.05
0.20
0.16
0.27
0.10
0.20
7.90
8.10
11.70
11.90
13.20
13.60
0.55 BSC
0.30
0.70
0°
5°
Integrated Silicon Solution, Inc.
PK13197T28
L
A1
Rev. B 01/31/97
0.037
0.047
0.002
0.008
0.006
0.011
0.004
0.008
0.308
0.316
0.456
0.465
0.515
0.531
0.022 BSC
0.011
0.027
0°
5°
Notes:
1. Controlling dimension: millimeters, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold flash protrusions and
should be measured from the bottom of the package.
4. Formed leads shall be planar with respect to one another within
0.004 inches at the seating plane.
®
ISSI
PACKAGING INFORMATION
®
300-mil Plastic SOJ
Package Code: J
N
E1
E
1
SEATING PLANE
D
A
B
e
A2
C
b
A1
E2
MILLIMETERS
INCHES
Sym.
Min. Typ. Max.
Min. Typ. Max.
N0.
Leads
24/26
A
—
—
3.56
—
A1
0.64
—
—
0.025
—
—
A2
2.41
—
2.67
0.095
—
0.105
b
0.41
—
0.51
0.016
—
0.020
B
0.66
—
0.81
0.026
—
0.032
— 0.140
C
0.20
—
0.25
0.008
—
0.010
D
17.02
—
17.27
0.670
—
0.680
E
8.26
—
8.76
0.325
—
0.345
E1
7.49
—
7.75
0.295
—
0.305
E2
6.27
—
7.29
0.247
—
0.287
e
1.27 BSC
Notes:
1. Controlling dimension: inches, unless otherwise
specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash
protrusions and should be measured from the bottom of
the package.
4. Formed leads shall be planar with respect to one
another within 0.004 inches at the seating plane.
0.050 BSC
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
02/25/03
ISSI
PACKAGING INFORMATION
®
300-mil Plastic SOJ
Package Code: J
MILLIMETERS
INCHES
Sym.
Min. Typ. Max.
Min. Typ. Max.
N0.
Leads
28
MILLIMETERS
INCHES
Sym.
Min. Typ. Max.
Min. Typ. Max.
N0.
Leads
32
A
—
—
3.56
—
—
0.140
A
—
—
3.56
—
—
0.140
A1
0.64
—
—
0.025
—
—
A1
0.64
—
—
0.025
—
—
A2
2.41
—
2.67
0.095
—
0.105
A2
2.41
—
2.67
0.095
—
0.105
b
0.41
—
0.51
0.016
—
0.020
b
0.41
—
0.51
0.016
—
0.020
B
0.66
—
0.81
0.026
—
0.032
B
0.66
—
0.81
0.026
—
0.032
C
0.20
—
0.25
0.008
—
0.010
C
0.20
—
0.25
0.008
—
0.010
D
18.29
—
18.54
0.720
—
0.730
D
20.83
—
21.08
0.820
—
0.830
E
8.26
—
8.76
0.325
—
0.345
E
8.26
—
8.76
0.325
—
0.345
E1
7.49
—
7.75
0.295
—
0.305
E1
7.49
—
7.75
0.295
—
0.305
E2
6.27
—
7.29
0.247
—
0.287
E2
6.27
—
7.29
0.247
—
0.287
e
2
1.27 BSC
0.050 BSC
e
1.27 BSC
0.050 BSC
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
02/25/03
ISSI
®
PACKAGING INFORMATION
330-mil Plastic SOP
Package Code: U (28-pin)
N
E1
E
1
D
SEATING PLANE
A
S
L
B
e
A1
MILLIMETERS
Sym.
Min.
No. Leads
Max.
h x 45o
INCHES
Min.
28
Max.
28
A
—
2.84
—
0.112
A1
0.10
—
0.004
—
B
0.36
0.51
0.014
0.020
C
0.25
—
0.010
—
D
17.98
18.24
0.708
0.718
E
11.51
12.12
0.453
0.477
E1
8.28
8.53
0.326
0.336
e
1.27 BSC
0.30
0.51
0.012
0.020
L
0.71
1.14
0.028
0.045
α
0
8
0
8o
S
0.58
1.19
0.023
0.047
o
C
Notes:
1. Controlling dimension: inches, unless
otherwise specified.
2. BSC = Basic lead spacing between
centers.
3. Dimensions D and E1 do not include
mold flash protrusions and should be
measured from the bottom of the
package.
4. Formed leads shall be planar with
respect to one another within 0.004
inches at the seating plane.
0.050 BSC
h
o
α
o
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
02/26/03
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