IDT IDT71342SA25JI High speed 4k x 8 dual-port static ram with semaphore Datasheet

HIGH SPEED
4K X 8 DUAL-PORT
STATIC RAM
WITH SEMAPHORE
IDT71342SA/LA
Features
◆
◆
◆
High-speed access
– Commercial: 20/25/35/45/55/70ns (max.)
– Industrial: 25/35/55ns (max.)
Low-power operation
– IDT71342SA
Active: 700mW (typ.)
Standby: 5mW (typ.)
– IDT71342LA
Active: 700mW (typ.)
Standby: 1mW (typ.)
◆
◆
◆
◆
◆
Fully asynchronous operation from either port
Full on-chip hardware support of semaphore signalling between ports
Battery backup operation—2V data retention (LA only)
TTL-compatible; single 5V (±10%) power supply
Available in plastic packages
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Functional Block Diagram
R/WL
CEL
R/WR
CER
OEL
OER
I/O0L- I/O7L
I/O
CONTROL
I/O
CONTROL
I/O0R - I/O7R
MEMORY
ARRAY
SEMAPHORE
LOGIC
SEMR
SEML
A0L- A11L
ADDRESS
DECODER
ADDRESS
DECODER
A0R- A11R
2721 drw 01
JANUARY 2001
1
©2000 Integrated Device Technology, Inc.
DSC 2621/12
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
Description
The IDT71342 is a high-speed 4K x 8 Dual-Port Static RAM with full
on-chip hardware support of semaphore signalling between the two
ports.
The IDT71342 provides two independent ports with separate
control, address, and I/O pins that permit independent, asynchronous
access for reads or writes to any location in memory. To assist in
arbitrating between ports, a fully independent semaphore logic block
is provided. This block contains unassigned flags which can be
accessed by either side; however, only one side can control the flag at any
time. An automatic power down feature, controlled by CE and SEM,
permits the on-chip circuitry of each port to enter a very low standby power
mode (both CE and SEM HIGH).
Fabricated using IDT’s CMOS high-performance technology, this
device typically operates on only 700mW of power. Low-power (LA)
versions offer battery backup data retention capability, with each port
typically consuming 200µW from a 2V battery. The device is packaged
in either a 64-pin TQFP or a 52-pin PLCC.
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
R/WR
SEMR
A11R
52 51 50 49 48 47
1
11
12
13
IDT71342J
J52-1(4)
14
15
52-Pin PLCC
Top View(5)
A10R
VCC
CER
SEML
2
8
9
10
16
17
18
19
20
46
OER
45
44
A0R
A1R
43
42
A2R
A3R
41
40
A4R
A5R
39
38
A6R
A7R
37
36
A8R
A9R
N/C
35
34
I/O6R
I/O4R
I/O5R
I/O3R
I/O2R
I/O0R
I/O1R
N/C
GND
I/O6L
I/O7L
I/O5L
I/O4L
21 22 23 24 25 26 27 28 29 30 31 32 33
I/O7R
N/C
N/C
A10L
A11L
SEML
R/WL
CEL
VCC
N/C
CER
R/WR
SEM R
A11R
A10R
N/C
N/C
A2L
A3L
4 3
R/WL
CEL
7 6 5
A1L
A11L
INDEX
OEL
A10L
A0L
Pin Configurations(1,2,3)
2721 drw 02
71342PF
PN64-1(4)
64-Pin TQFP
Top View(5)
6.42
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I/O3L
N/C
I/O4L
I/O5L
I/O6L
I/O7L
N/C
N/C
GND
I/O0R
I/O1R
I/O2R
I/O3R
N/C
I/O4R
I/O5R
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J52 package body is approximately .79 in x .79 in x .17 in.
PN64 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
OEL
A0L
A1L
A2L
A3L
A4L
A5L
A6L
N/C
A7L
A8L
A9L
N/C
I/O0L
I/O1L
I/O2L
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
INDEX
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
N/C
A7R
A8R
A9R
N/C
N/C
I/O7R
I/O6R
2721 drw 03
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Symbol
VTERM(2)
Rating
Terminal Voltage
with Respect
to GND
Commercial
& Industrial
Unit
-0.5 to +7.0
V
TBIAS
Temperature
Under Bias
-55 to +125
o
TSTG
Storage
Temperature
-65 to +150
o
PT(3)
Power
Dissipation
1.5
W
IOUT
DC Output
Current
50
mA
C
C
Maximum Operating
Temperature and Supply Voltage(1,2)
COUT
Input Capacitance
Output Capacitance
Vcc
Commercial
0OC to +70OC
0V
5.0V + 10%
0V
5.0V + 10%
O
O
-40 C to +85 C
Conditions(2)
Max.
Unit
V IN = 3dV
9
pF
V OUT = 3dV
10
2721 tbl 03
Recommended DC Operating
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
4.5
5.0
5.5
V
0
0
0
V
V
VCC
Supply Voltage
GND
Ground
VIH
Input High Voltage
2.2
____
6.0(2)
VIL
Input Low Voltage
-0.5(1)
____
0.8
V
2721 tbl 04
NOTES:
1. VIL (min.) > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
Capacitance(1) (TA = +25°C, f = 1.0MHz)
CIN
GND
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
2721 tbl 01
Parameter
Ambient
Temperature
Industrial
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10 ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc +10%.
Symbol
Grade
pF
2721 tbl 02
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dv references the interpolated capacitance when the input and output signals
switch from 0V to 3V and from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage (VCC = 5V ± 10%)
71342SA
Symbol
Parameter
|ILI|
(1)
Input Leakage Current
|ILO|
Output Leakage Current
VOL
VOH
Output Low Voltage
Output High Voltage
Test Conditions
71342LA
Min.
Max.
Min.
Max.
Unit
VCC = 5.5V, VIN = 0V to V CC
___
10
___
5
µA
CE = VIH, VOUT = 0V to V CC
___
10
___
5
µA
IOL = 6mA
___
0.4
___
0.4
V
IOL = 8mA
___
0.5
___
0.5
V
2.4
___
2.4
___
V
IOH = -4mA
2721 tbl 05
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
3
6.42
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VCC = 5.0V ± 10%)
71342X20
Com'l Only
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Operating Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current (Both
Ports CMOS Level Inputs)
Full Standby Current
(One Port CMOS Level Inputs)
Test Condition
Version
CE = VIL,
Outputs Disabled
SEM = Don't Care
f = fMAX(3)
CEL and CER = VIH
SEML = SEMR > VIH
f = fMAX(3)
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
f=fMAX(3)
Both Ports CEL and
CER > VCC - 0.2V,
VIN > VCC - 0.2V or V IN < 0.2V
SEML = SEMR > VCC - 0.2V
f = 0(3)
One Port CE"A" or
CE"B" > VCC - 0.2V
VIN > VCC - 0.2V or V IN < 0.2V
SEML = SEMR > VCC - 0.2V
Active Port Outputs Disabled,
f = fMAX(3)
71342X25
Com'l & Ind
71342X35
Com'l & Ind
Typ. (2)
Max.
Typ. (2)
Max.
Typ. (2)
Max.
Unit
COM'L
SA
LA
170
170
280
240
160
160
280
240
150
150
260
200
mA
IND
SA
LA
____
____
____
____
160
160
310
260
150
150
300
250
COM'L
SA
LA
25
25
80
80
25
25
80
50
25
25
75
45
IND
SA
LA
____
____
____
____
25
25
100
80
25
25
75
55
COM'L
SA
LA
105
105
180
150
95
95
180
150
85
85
170
140
IND
SA
LA
____
____
____
____
95
95
210
170
85
85
200
160
COM'L
SA
LA
1.0
0.2
15
4.5
1.0
0.2
15
4.0
1.0
0.2
15
4.0
IND
SA
LA
____
____
____
____
1.0
0.2
30
10
1.0
0.2
30
10
COM'L
SA
LA
105
105
170
130
95
95
170
120
85
85
150
110
IND
SA
LA
____
____
____
____
95
95
210
190
85
85
190
130
mA
mA
mA
mA
2721 tbl 06a
71342X45
Com'l Only
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Operating Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current (Both
Ports CMOS Level Inputs)
Full Standby Current
(One Port CMOS Level Inputs)
71342X55
Com'l & Ind
71342X70
Com'l Only
Typ. (2)
Max.
Typ. (2)
Max.
Typ. (2)
Max.
Unit
CE = VIL,
Outputs Disabled
SEM = Don't Care
f = fMAX(3)
COM'L
SA
LA
140
140
240
200
140
140
240
200
140
140
240
200
mA
IND
SA
LA
____
____
270
220
____
____
140
140
____
____
____
____
CEL and CER = VIH
SEML = SEMR > VIH
f = fMAX(3)
COM'L
SA
LA
25
25
70
40
25
25
70
40
25
25
70
40
IND
SA
LA
____
____
70
50
____
____
25
25
____
____
____
____
COM'L
SA
LA
75
75
160
130
75
75
160
130
75
75
160
130
IND
SA
LA
____
____
180
150
____
____
75
75
____
____
____
____
Test Condition
Version
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
f=fMAX(3)
Both Ports CEL and
CER > VCC - 0.2V,
VIN > VCC - 0.2V or V IN < 0.2V
SEML = SEMR > VCC - 0.2V
f = 0(3)
COM'L
SA
LA
1.0
0.2
15
4.0
1.0
0.2
15
4.0
1.0
0.2
15
4.0
IND
SA
LA
____
____
30
10
____
____
1.0
2.0
____
____
____
____
One Port CE"A" or
CE"B" > VCC - 0.2V
VIN > VCC - 0.2V or V IN < 0.2V
SEML = SEMR > VCC - 0.2V
Active Port Outputs Disabled,
f = fMAX(3)
COM'L
SA
LA
75
75
150
100
75
75
150
100
75
75
150
100
IND
SA
LA
____
____
170
120
____
____
75
75
____
____
____
____
mA
mA
mA
mA
2721 tbl 06b
NOTES:
1. 'X' in part number indicates power rating (SA or LA).
2. VCC = 5V, TA = +25°C for typical, and parameters are not production tested.
3. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except Output Enable). f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby ISB3.
6.42
4
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
Data Retention Characteristics
(LA Version Only) VLC = 0.2V, VHC = VCC - 0.2V
Symbol
Parameter
Test Condition
___
VDR
VCC for Data Retention
ICCDR
Data Retention Current
VCC = 2V, CE > VHC
tCDR(3)
Chip Deselect to Data Retention Time
SEM > VHC
(3)
tR
Operation Recovery Time
Typ.(1)
Min.
2.0
COM'L. & IND.
Unit
___
V
___
100
1500
µA
0
___
___
ns
___
___
ns
(2)
VIN > VHC or < VLC
Max.
tRC
2721 tbl 07
NOTES:
1. VCC = 2V, TA = +25°C, and are not production tested.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization, but is not production tested.
Data Rention Waveform
DATA RETENTION MODE
VCC
4.5V
4.5V
VDR > 2V
tCDR
CE
tR
VDR
VIH
VIH
2721 drw 04
AC Test Conditions
GND to 3.0V
Input Pulse Levels
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Figures 1 and 2
Output Load
2721 tbl 08
+5V
+5V
1250Ω
1250Ω
DATAOUT
DATAOUT
775Ω
775Ω
30pF
2721 drw 05
,
Figure 1. AC Output Test Load
5pF *
,
2721 drw 06
Figure 2. Output Test Load
(for t LZ, tHZ, t WZ, tOW)
*Including scope and jig
5
6.42
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(5)
71342X20
Com'l Only
Symbol
Parameter
71342X25
Com'l & Ind
71342X35
Com'l & Ind
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
20
____
25
____
35
____
ns
tAA
Address Access Time
____
20
____
25
____
35
ns
tACE
Chip Enable Access Time (3)
____
20
____
25
____
35
ns
tAOE
Output Enable Access Time
____
15
____
15
____
20
ns
0
____
0
____
0
____
ns
0
____
0
____
0
____
ns
____
15
____
15
____
20
ns
0
____
0
____
0
____
ns
____
50
____
50
____
50
ns
10
____
10
____
15
____
ns
____
40
____
50
____
60
ns
____
30
____
30
____
35
ns
____
____
____
25
____
35
ns
tOH
Output Hold from Address Change
Output Low-Z Time
tLZ
(1,2)
(1,2)
tHZ
Output High-Z Time
tPU
Chip Enable to Power Up Time (2)
tPD
Chip Disable to Power Down Time(2)
tSOP
SEM Flag Update Pulse (OE or SEM)
tWDD
Write Pulse to Data Delay
(4)
tDDD
Write Data Valid to Read Data Delay
tSAA
Semaphore Address Access Time
(4)
2721 tbl 09a
71342X45
Com'l Only
Symbol
Parameter
71342X55
Com'l & Ind
71342X70
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
45
____
55
____
70
____
ns
Address Access Time
____
READ CYCLE
tRC
45
____
55
____
70
ns
tACE
Chip Enable Access Time
(3)
____
45
____
55
____
70
ns
tAOE
Output Enable Access Time
____
25
____
30
____
40
ns
tOH
Output Hold from Address Change
0
____
0
____
0
____
ns
tLZ
Output Low-Z Time(1,2)
5
____
5
____
5
____
ns
tHZ
(1,2)
____
20
____
25
____
30
ns
0
____
0
____
0
____
ns
____
50
____
50
____
50
ns
tAA
tPU
Output High-Z Time
Chip Enable to Power Up Time
(2)
(2)
tPD
Chip Disable to Power Down Time
tSOP
SEM Flag Update Pulse (OE or SEM)
15
____
20
____
20
____
ns
tWDD
Write Pulse to Data Delay (4)
____
70
____
80
____
90
ns
45
____
55
____
70
ns
45
____
55
____
70
ns
tDDD
tSAA
Write Data Valid to Read Data Delay
(4)
____
____
Semaphore Address Access Time
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Ouput Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access SRAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, and SEM = VIL.
4. 'X' in part number indicates power rating (SA or LA).
5. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”.
6.42
6
2721 tbl 09b
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side(1,2,4)
tRC
ADDRESS
tAA
or tSAA
tOH
tOH
PREVIOUS DATA VALID
DATAOUT
DATA VALID
2721 drw 07
Timing Waveform of Read Cycle No. 2, Either Side(1,3)
tSOP
CE or SEM
tACE
(5)
tAOE(4)
tSOP
tHZ
(2)
OE
tLZ
(1)
tHZ
VALID DATA
DATAOUT
tLZ
(2)
(4)
(1)
tPU
tPD
ICC
CURRENT
50%
50%
ISB
2721 drw 08
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, OE or CE.
3. R/W = VIH and OE = VIL, unless otherwise noted.
4. Start of valid data depends on which timing becomes effective last; tAOE, tACE , or tAA
5. To access SRAM, CE = VIL and SEM = V IH. To access semaphore, CE = VIH and SEM = VIL. tAA is for SRAM Address Access and t SAA is for Semaphore Address Access.
Timing Waveform of Write with Port-to-Port Read(2,3)
tWC
ADDR "A"
MATCH
tWP
R/W "A"
(1)
tDH
tDW
DATAIN "A"
VALID
ADDR "B"
MATCH
tWDD
VALID
DATAOUT "B"
tDDD
NOTES:
1. Write cycle parameters should be adhered to, in order to ensure proper writing.
2. CEL = CER = VIL. CE"B" = VIL.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
7
6.42
2721 drw 09
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage(5)
71342X20
Com'l Only
Symbol
Parameter
71342X25
Com'l & Ind
71342X35
Com'l & Ind
Min.
Max.
Min.
Max.
Min.
Max.
Unit
20
____
25
____
35
____
ns
15
____
20
____
30
____
ns
15
____
20
____
30
____
ns
0
____
0
____
ns
WRITE CYCLE
tWC
tEW
tAW
Write Cycle Time
Chip Enable to End-of-Write
(3)
Address Valid to End-of-Write
tAS
Address Set-up Time
0
____
tWP
Write Pulse Width
15
____
20
____
25
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
ns
tDW
Data Valid to End-of-Write
15
____
15
____
20
____
ns
tHZ
Output High-Z Time (1,2)
____
15
____
15
____
20
ns
0
____
0
____
3
____
ns
____
15
____
15
____
20
ns
3
____
3
____
3
____
ns
10
____
10
____
ns
10
____
10
____
ns
Data Hold Time
tDH
(4)
(1,2)
tWZ
Write Enable to Output in High-Z
(1,2,4)
tOW
Output Active from End-of-Write
tSWR
SEM Flag Write to Read Time
10
____
tSPS
SEM Flag Contention Window
10
____
2721 tbl 10a
71342X45
Com'l Only
Symbol
Parameter
71342X55
Com'l & Ind
71342X70
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Unit
45
____
55
____
70
____
ns
tEW
Chip Enable to End-of-Write
(3)
40
____
50
____
60
____
ns
tAW
Address Valid to End-of-Write
40
____
50
____
60
____
ns
tAS
Address Set-up Time
0
____
0
____
0
____
ns
tWP
Write Pulse Width
40
____
50
____
60
____
ns
0
____
0
____
0
____
ns
20
____
25
____
30
____
ns
____
20
____
25
____
30
ns
3
____
3
____
3
____
ns
25
____
30
ns
WRITE CYCLE
tWC
tWR
tDW
tHZ
tDH
tWZ
Write Cycle Time
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time
Data Hold Time
(1,2)
(4)
(1,2)
____
20
____
(1,2,4)
3
____
3
____
3
____
ns
ns
Write Enable to Output in High-Z
tOW
Output Active from End-of-Write
tSWR
SEM Flag Write to Read Time
10
____
10
____
10
____
tSPS
SEM Flag Contention Window
10
____
10
____
10
____
ns
2721 tbl 10b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but is not production tested.
3. To access SRAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part number indicates power rating (SA or LA).
6.42
8
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
W CONTROLLED TIMING(1,5,8)
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W
tWC
ADDRESS
tAS (6)
OE
tAW
CE or SEM
tWR
(3)
(9)
tHZ
tWP (2)
(7)
R/W
tWZ (7)
tLZ
tHZ (7)
tOW
(4)
(4)
DATAOUT
tDH
tDW
DATAIN
2721 drw 10
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1, 5)
tWC
ADDRESS
tAW
CE or SEM
(9)
(6)
tAS
tEW
(2)
tWR
(3)
R/W
tDW
tDH
DATAIN
2721 drw 11
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of either CE or SEM = VIL and R/W = VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end-of-write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus
for the required t DW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP .
9. To access SRAM, CE =V IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
9
6.42
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read After Write Timing, Either Side(1)
tSAA
A0 - A2
VALID ADDRESS
tAW
tOH
VALID ADDRESS
tWR
tACE
tEW
SEM
tDW
DATA0
tSOP
DATAOUT
VALID
DATAIN VALID
tAS
tWP
tDH
R/W
tSWRD
OE
tAOE
tSOP
Test Cycle
(Read Cycle)
Write Cycle
2721 drw 12
NOTE:
1. CE = VIH for the duration of the above timing (both write and read cycle).
Timing Waveform of Semaphore Condition(1,3,4)
A0"A" - A2"A"
SIDE(2) "A"
MATCH
R/W"A"
SEM"A"
tSPS
A0"B" - A2"B"
SIDE(2) "B"
MATCH
R/W"B"
SEM"B"
2721 drw 13
NOTES:
1. D0R = D0L = VIL, CER = CE L = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
3. This parameter is measured from the point where R/W "A" or SEM "A" goes HIGH until R/W " B" or SEM " B" goes HIGH.
4. If tSPS is violated, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
6.42
10
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
FUNCTIONAL DESCRIPTION
The IDT71342 is an extremely fast Dual-Port 4K x 8 CMOS Static
RAM with an additional 8 address locations dedicated to binary
semaphore flags. These flags allow either processor on the left or right
side of the Dual-Port RAM to claim a privilege over the other processor
for functions defined by the system designer’s software. As an example,
the semaphore can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared
resource.
The Dual-Port RAM features a fast access time, and both ports are
completely independent of each other. This means that the activity on
the left port in no way slows the access time of the right port. Both ports
are identical in function to standard CMOS Static RAMs and can be
read from or written to at the same time, with the only possible conflict
arising from the simultaneous writing of, or a simultaneous READ/
WRITE of, a non-semaphore location. Semaphores are protected
against such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion of the
Dual-Port SRAM. These devices have an automatic power-down
feature controlled by CE, the Dual-Port SRAM enable, and SEM, the
semaphore enable. The CE and SEM pins control on-chip power down
circuitry that permits the respective port to go into standby mode when
not selected. This is the condition which is shown in Truth Table I
where CE and SEM are both HIGH.
Systems which can best use the IDT71342 contain multiple
processors or controllers and are typically very high-speed systems
which are software controlled or software intensive. These systems
can benefit from a performance increase offered by the IDT71342’s
hardware semaphores, which provide a lockout mechanism without
requiring complex programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in
varying configurations. The IDT71342 does not use its semaphore
flags to control any resources through hardware, thus allowing the
system designer total flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are independent
of the Dual-Port RAM. These latches can be used to pass a flag, or
token, from one port to the other to indicate that a shared resource is
in use. The semaphores provide a hardware assist for a use assignment
method called “Token Passing Allocation.” In this method, the state of
a semaphore latch is used as a token indicating that a shared resource
is in use. If the left processor wants to use this resource, it requests the
token by setting the latch. This processor then verifies its success in
setting the latch by reading it. If it was successful, it proceeds to
assume control over the shared resource. If it was not successful in
setting the latch, it determines that the right side processor had set the
latch first, has the token and is using the shared resource. The left
processor can then either repeatedly request that semaphore’s status
or remove its request for that semaphore to perform another task and
occasionally attempt again to gain control of the token via the set and
test sequence. Once the right side has relinquished the token, the left
side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by
writing a zero into a semaphore latch and is released when the same
side writes a one to that latch.
The eight semaphore flags reside within the IDT71342 in a separate
memory space from the Dual-Port RAM. This address space is
accessed by placing a LOW input on the SEM pin (which acts as a chip
select for the semaphore flags) and using the other control pins
(Address, OE, and R/W) as they would be used in accessing
a standard Static RAM. Each of the flags has a unique address
which can be accessed by either side through the address pins A0–A2.
When accessing the semaphores, none of the other address pins has
any effect.
When writing to a semaphore, only data pin D0 is used. If a LOW
level is written into an unused semaphore location, that flag will be set
to a zero on that side and a one on the other (see Truth Table II). That
semaphore can now only be modified by the side showing the zero.
When a one is written into the same location from the same side, the
flag will be set to a one for both sides (unless a semaphore request
from the other side is pending) and then can be written to by both sides.
The fact that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what makes
semaphore flags useful in interprocessor communications. (A thorough
discussion on the use of this feature follows shortly.) A zero written into
the same location from the other side will be stored in the semaphore
request latch for that side until the semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into all data bits
so that a flag that is a one reads as a one in all data bits and a flag
containing a zero reads as all zeros. The read value is latched into one
side’s output register when that side’s semaphore select (SEM) and
output enable (OE) signals go active. This serves to disallow the
semaphore from changing state in the middle of a read cycle due to a
write cycle from the other side. Because of this latch, a repeated read
of a semaphore in a test loop must cause either signal (SEM or OE) to
go inactive or the output will never change.
A sequence of WRITE/READ must be used by the semaphore in
order to guarantee that no system level contention will occur. A
processor requests access to shared resources by attempting to write
a zero into a semaphore location. If the semaphore is already in use,
the semaphore request latch will contain a zero, yet the semaphore
flag will appear as a one, a fact which the processor will verify by the
subsequent read (see Truth Table II). As an example, assume a
processor writes a zero in the left port at a free semaphore location. On
a subsequent read, the processor will verify that it has written
successfully to that location and will assume control over the resource
in question. Meanwhile, if a processor on the right side attempts to
write a zero to the same semaphore flag it will fail, as will be verified
by the fact that a one will be read from that semaphore on the right side
during a subsequent read. Had a sequence of READ/WRITE been
used instead, system contention problems could have occurred during
the gap between the read and write cycles.
It is important to note that a failed semaphore request must be
followed by either repeated reads or by writing a one into the same
location. The reason for this is easily understood by looking at the
simple logic diagram of the semaphore flag in Figure 3. Two semaphore
11
6.42
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
request latches feed into a semaphore flag. Whichever latch is first to
present a zero to the semaphore flag will force its side of the
semaphore flag LOW and the other side HIGH. This condition will
continue until a one is written to the same semaphore request latch.
Should the other side’s semaphore request latch have been written to
a zero in the meantime, the semaphore flag will now stay LOW until its
semaphore request latch is written to a one. From this it is easy to
understand that, if a semaphore is requested and the processor which
requested it no longer needs the resource, the entire can hang up until
a one is written into that semaphore request latch.
The critical case of semaphore timing is when both sides request
a single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If
simultaneous requests are made, the logic guarantees that only one
side receives the token. If one side is earlier than the other in making
the request, the first side to make the request will receive the token. If
both requests arrive at the same time, the assignment will be arbitrarily
made to one port or the other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to
a resource is secure. As with any powerful programming technique, if
semaphores are misused or misinterpreted, a software error can
easily happen. Code integrity is of the utmost importance when
semaphores are used instead of slower, more restrictive hardware
intensive schemes.
Initialization of the semaphores is not automatic and must be
handled via the initialization program at power up. Since any semaphore
request flag which contains a zero must be reset to a one, all
Truth Table I — Non-Contention Read/Write Control(2)
Left or Right Port(1)
R/W
CE
SEM
OE
D0-7
X
H
H
X
Z
Port Disabled and in Power Down Mode
H
H
L
L
DATAOUT
Data in Semaphore Flag Output on Port
X
X
X
H
Z
↑
H
L
X
DATAIN
H
L
H
L
DATAOUT
L
L
H
X
DATAIN
X
____
X
L
L
Function
Output Disabled
Port Data Bit D0 Written Into Semaphore Flag
Data in Memory Output on Port
Data on Port Written Into Memory
Not Allowed
2721 tbl 11
NOTE:
1. AOL = A11L ¹ A0R - A11R.
2. "H" = VIH, "L" = VIL, "X" = Don’t Care, "Z" = High-Impedance.
Truth Table II — Example Semaphore Procurement Sequence(1,2,3)
Functions
D0 - D15 Left
D0 - D15 Right
Status
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
NOTE:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT71342.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's. These eight semaphores are addressed by A0-A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the semaphore Read/Write Control Truth Table.
6.42
12
2721 tbl 12
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
semaphores on both sides should have a one written into them at
initialization from both sides to assure that they will be free when
needed.
Using Semaphores–Some
examples
Perhaps the simplest application of semaphores is their application
as resource markers for the IDT71342’s Dual-Port RAM. Say the 4K
x 8 RAM was to be divided into two 2K x 8 blocks which were to be
dedicated at any one time to servicing either the left or right port.
Semaphore 0 could be used to indicate the side which would control
the lower section of memory, and Semaphore 1 could be defined as the
indicator for the upper section of the memory.
To take a resource, in this example the lower 2K of Dual-Port RAM,
the processor on the left port could write and then read a zero into
Semaphore 0. If this task were successfully completed (a zero was
read back rather than a one), the left processor would assume control
of the lower 2K. Meanwhile, the right processor would attempt to
perform the same function. Since this processor was attempting to
gain control of the resource after the left processor, it would read back
a one in response to the zero it had attempted to write into Semaphore
0. At this point, the software could choose to try and gain control of the
second 2K section by writing, then reading a zero into Semaphore 1.
If it succeeded in gaining control, it would lock out the left side.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could
undo its semaphore request and perform other tasks until it was able
to write, then read a zero into Semaphore 1. If the right processor
performs a similar task with Semaphore 0, this protocol would allow the
two processors to swap 2K blocks of Dual-Port RAM with each other.
The blocks do not have to by any particular size and can even be
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the
Dual-Port RAM or other shared resources into eight parts. Semaphores
can even be assigned different meanings on different sides rather than
being given a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory
during a transfer and the I/O device cannot tolerate any wait states.
With the use of semaphores, once the two devices had determined
which memory area was “off limits” to the CPU, both the CPU and the
I/O devices could access their assigned portions of memory continuously
without any wait states.
Semaphores are also useful in applications where no memory
“WAIT” state is available on one or both sides. Once a semaphore
handshake has been performed, both processors can access their
assigned RAM segments at full speed.
Another application is in the area of complex data structures. In this
case, block arbitration is very important. For this application one
processor may be responsible for building and updating a data
structure. The other processor then reads and interprets that data
structure. If the interpreting processor reads an incomplete data
structure, a major error condition may exist. Therefore, some sort of
arbitration must be used between the two different processors. The
building processor arbitrates for the block, locks it and then is able to
go in and update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting processor
to come back and read the complete data structure, thereby
guaranteeing a consistent data structure.
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
D0
D
SEMAPHORE
REQUEST FLIP FLOP
Q
Q
D
D0
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
Figure 3. IDT71342 Semaphore Logic
13
6.42
2721 drw 14
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
Ordering Information
IDT
XXXX
Device Type
A
Power
999
Speed
A
Package
A
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
J
PF
52-pin PLCC (J52-1)
64-pin TQFP (PN64-1)
20
25
35
45
55
70
Commercial Only
Commercial & Industrial
Commercial & Industrial
Commercial Only
Commercial & Industrial
Commercial Only
SA
LA
Standard Power
Low Power
71342
32K (4K x 8-Bit) Dual-Port RAM w/ Semaphore
Speed in nanoseconds
2721 drw 15
Datasheet Document History
1/12/99:
6/9/99:
10/1/99:
11/10/99:
12/22/99:
6/26/00:
1/12/00:
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Added additional notes to pin configurations
Changed drawing format
Added Industrial Temperature Ranges and removed corresponding notes
Replaced IDT logo
Page 1 Made corrections to drawing
Page 3 Increased storage temperature parameters
Clarified TA parameter
Page 4 DC Electrical parameters–changed wording from "open" to "disabled"
Changed ±500mV to 0mV in notes
Pages 1 and 2 Moved "Description" to page 2 and adjusted page layouts
Page 1 Added "(LA only)" to paragraph
Page 2 Fixed J52 package description in notes
Page 8 Replaced bottom table with correct 10b table
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6.42
14
for Tech Support:
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