FUJITSU SEMICONDUCTOR Data Sheet (Advance Information) Advance Information 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90495 Series MB90497/F497 1. OUTLINE The MB90495-series with FULL-CAN interface and FLASH ROM is especially designed for automotive and industrial applications. Its main feature is the on-chip CAN Interface, which conforms to V2.0 Part A and Part B, while supporting a very flexible message buffer scheme, including 8 message buffers, and so offering more functions than a normal full CAN approach. With the new 0.5 mm CMOS technology, Fujitsu now also offers on-chip FLASH-ROM program memory. An internal voltage booster removes the necessity for a second programming voltage. An on-chip voltage regulator provides 3V to the internal MCU core. This creates a major advantage in terms of EMI and power consumption. The internal PLL clock frequency multiplier provides an internal 62.5 nsec instruction cycle time from an external 4 MHz clock. A 32kHz Subsystem clock has been included for power saving modes and real time measurement. There are 2 on-chip UART’s, which also provide synchronous communication modes. Furthermore the MCU features an 8 channel ADC, 8 channel External interrupt controller, two 16 bit PPG channels, 4 channel Input Capture Unit and a 16-bit free running I/O-timer. MB90495 Series Data Sheet (Advance Information) 1 / 40 FME EMDC June 19, 2000 MB90495 Series 2. FEATURES • 16-bit core CPU; 4MHz external clock (16 MHz internal, 62.5 ns instruction cycle time) • 32kHz Subsystem Clock • 0.5 mm CMOS Technology • Internal voltage regulator supports 3V MCU core, offering low EMI and low power consumption figures • 64 KB FLASH ROM; supports automatic programming, 10.000 erase cycles, 10 year data retention time and no second programming voltage required • 2 KB static RAM • FULL-CAN interface; conforming to Version 2.0 Part A and Part B, flexible message buffering (mailbox and FIFO buffering can be mixed) • 2 UART’s; both offering synchronous communication modes. • Powerful interrupt functions (8 programmable priority levels; 8 external interrupts) • I/O Timer • A/D Converter: 8 channel analogue inputs (Resolution 10 bits or 8 bits) • ICU (Input capture) 16bit * 4ch • PPG (Programmable Pulse Generator) 16bit * 2ch; Can be configured as 8bit * 4ch • Optimised instruction set for controller applications (bit, byte, word and long-word data types; 23 different addressing modes; barrel shift; variety of pointers) • 4-byte instruction execution queue • Signed multiply (16bit*16bit) and divide (32bit/16bit) instructions available • Program Patch Function • Fast Interrupt processing • 16-bit reload timer: 2 channels • Low Power Consumption - Several different Lo-Power modes: (Sleep, Stop, Watch,...) • Package: • QFP-64; 12mm x 12mm body, 0.65mm pin pitch QFP-64; 20mm x 18mm body, 1.0mm pin pitch MB90495 Series Data Sheet (Advance Information) 2 / 40 FMG EMDC June 19, 2000 MB90495 Series 3. PRODUCT LINEUP The following table provides an overview of the MB90495 Series Features MB90F497 MB90497 F2MC-16LX CPU CPU System clock On-chip PLL clock multiplier (x1, x2, x3, x4, 1/2 when PLL stop) Minimum instruction execution time: 62.5 ns (4 MHz osc. PLL x4) ROM Boot-block Flash memory 64 Kbytes Mask ROM 64 Kbytes RAM 2 Kbytes 2 Kbytes Technology 0.5 mm CMOS with on-chip voltage regulator for internal power supply + Flash memory Onchip charge pump for programming voltage 0.5 mm CMOS with on-chip voltage regulator for internal power supply Operating voltage range 5 V +/- 10% Temperature range - 40 to 85 °C Package MB90495 Series Data Sheet (Advance Information) QFP64 3 / 40 FME EMDC June 19, 2000 MB90495 Series 4. BLOCK DIAGRAM X0,X1 RSTX X0A, X1A Clock Controller 16LX CPU Watch Timer Time Base Timer RAM 2K IO Timer FRCK Input Capture 4ch IN[3:0] 16-bit PPG 2ch ROM/Flash 64K PPG[3:0] Prescaler Prescaler SOT 0 SCK0 SIN0 AVCC AVSS AN[7:0] AVR ADTG UART 0 (SCI) RX TX CAN UART 1 (SCI) FMC-16 Bus SOT1 SCK1 SIN1 External Interrupt INT[7:0] 16bit Reload Timer 2ch TIN[1:0] TOT[1:0] 10-bit ADC 8ch MB90495 Series Data Sheet (Advance Information) 4 / 40 FMG EMDC June 19, 2000 P44/RX P30/ALE/SOUT0 VSS P27/INT7/A23 P26/INT6/A22 P25/INT5/A21 P24/INT4/A20 P23/TOUT1/A19 P22/TIN1/A18 P21/TOUT0/A17 P20/TIN0/A16 P17/PPG3/AD15 P16/PPG2/AD14 P15/PPG1/AD13 P14/PPG0/AD12 P13/IN3/AD11 P12//IN2/AD10 P11/IN1/AD09 P10/IN0/AD08 P07/AD07 P61/INT1 P62/INT2 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/INT0 X0A X1A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P43/TX P31/RDX/SCK0 P32/WRLX/SIN0 P33/WRHX P34/HRQ P35/HAKX VCC C P36/FRCK/RDY P37/ADTG/CLK P40/SIN1 P41/SCK1 P42/SOUT1 P43/TX 52 53 54 55 56 57 58 59 60 61 62 63 64 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 51 50 49 48 P44/RX 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 QFP-64 Package code (mold) FPT-64P-M09 MB90495 Series Data Sheet (Advance Information) 5 / 40 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Package code (mold) FPT-64P-M06 QFP-64 P63/INT3 MD0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 VSS P30/ALE/SOUT0 P31/RDX/SCK0 P32/WRLX/SIN0 P33/WRHX P34/HRQ P35/HAKX VCC C P36/FRCK/RDY P37/ADTG/CLK P40/SIN1 P41/SCK1 P42/SOUT1 P61/INT1 P62/INT2 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/INT0 X0A X1A 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 48 P25/INT5/A21 P24/INT4/A20 P23/TOUT1/A19 P22/TIN1/A18 P21/TOUT0/A17 P20/TIN0/A16 P17/PPG3/AD15 P16/PPG2/AD14 P15/PPG1/AD13 P14/PPG0/AD12 P13/IN3/AD11 P12//IN2/AD10 P11/IN1/AD09 P10/IN0/AD08 P27/INT7/A23 P26/INT6/A22 MB90495 Series 5. PIN ASSIGNMENT P07/AD07 P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 VSS X1 X0 MD2 MD1 RSTX MD0 P63/INT3 Figure 5.1 FPT-64P-M09 32 31 30 29 28 27 26 25 24 23 22 21 20 P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 VSS X1 X0 MD2 MD1 RSTX Figure 5.2 FPT-64P-M06 FME EMDC June 19, 2000 MB90495 Series 6. PIN DESCRIPTION 6.1 Pin Function Pin No. Circuit Type Active Level at RST Priority D H CMOS/ TTL High-Z Port D H CMOS/ TTL High-Z Port E H CMOS High-Z Port P60 INT0 D H CMOS/ TTL High-Z Port 15 X0A A Low frequency oscillation input 17 16 X1A A Low frequency oscillation output 18 17 P63 INT3 D H CMOS/ TTL 19 18 MD0 C H CMOS Mode input 20 19 RSTX B L CMOS Reset input 21 20 MD1 C H CMOS Mode input 22 21 MD2 F H CMOS Mode input 23 22 X0 A High frequency oscillation input 24 23 X1 A High frequency oscillation output 25 24 VSS Pin Name M06 M09 2 1 3 2 4 to 11 3 to 10 12 11 AVCC 13 12 AVR 14 13 AVSS 15 14 16 P61 INT1 P62 INT2 P50 to P57 AN0 to AN7 P00 to P07 AD00 to AD07 P10 to P13 34 to 37 33 to 36 IN0 to IN3 AD08 to AD11 P14 to P17 26 to 33 25 to 32 38 to 41 37 to 40 PPG0 to PPG3 42 41 43 42 44 43 AD12 to AD15 P20 TIN0 A16 P21 TOT0 A17 P22 TIN1 A18 High-Z Port Function General pupose IO External Interrupt input 1 General pupose IO External interrupt 2 General pupose IO Inputs for A/D Converter Dedicated power supply for A/D Converter Reference Volgate inupt for A/D Converter Dedicated power ground for A/D Converter General pupose IO External interrupt input 0 General purpose IO External interrupt 3 Power ground G H CMOS/ TTL High-Z Port G H CMOS/ TTL High-Z Port G H CMOS/ TTL High-Z Port G H CMOS/ TTL High-Z Port G H CMOS/ TTL High-Z Port G H CMOS/ TTL High-Z Port MB90495 Series Data Sheet (Advance Information) 6 / 40 General purpose IO Addresss Data Bus General pupose IO Inputs for Input Captures Address Data Bus General pupose IO Outputs for Programable Pulse Generators Address Data Bus General pupose IO Input for 16-bit Reload Timer 0 Address Bus General pupose IO Output for 16-bit Reload Timer 0 Address Bus General pupose IO Input for 16-bit Reload Timer 1 Address Bus FMG EMDC June 19, 2000 MB90495 Series Pin No. Pin Name M06 M09 45 44 46 to 49 45 to 48 50 49 P23 TOT1 A19 P24 to P25 INT4 to INT 7 A20 to A23 Circuit Type Active Level at RST Priority G H CMOS/ TTL High-Z Port G H CMOS/ TTL High-Z Port VSS P30 SOT0 ALE P31 SCK0 RDX P32 SIN0 WRLX P33 WRHX P34 HRQ P35 HAKX 51 50 52 51 53 52 54 53 55 54 56 55 57 56 VCC 58 57 C 59 58 60 59 61 60 62 61 63 62 64 63 1 64 P36 FRCK RDY P37 ADTG CLK P40 SIN1 P41 SCK1 P42 SOT1 P43 Tx P44 Rx Function General pupose IO Output for 16-bit Reload Timer 1 Address Bus General pupose IO Inputs for External Interrupt Address Bus Ground G H CMOS/ TTL High-Z Port G H CMOS/ TTL High-Z Port G H CMOS/ TTL High-Z Port G H CMOS/ TTL High-Z Port G H CMOS/ TTL High-Z Port G H CMOS/ TTL High-Z Port General pupose IO Output for UART 0 Address Latch Enable output General pupose IO Input/Output for UART 0 Read Enable output General pupose IO Input for UART 0 Write Enable Low-byte output General pupose IO Write Enable High-byte output General pupose IO Halt Request input General pupose IO Halt Acknowledge output Power supply G H CMOS/ TTL High-Z Port D H CMOS High-Z Port G H CMOS/ TTL High-Z Port G H CMOS/ TTL High-Z Port G H CMOS/ TTL High-Z Port G H CMOS/ TTL High-Z Port G H CMOS/ TTL High-Z Port MB90495 Series Data Sheet (Advance Information) 7 / 40 Pin for capacitor for the internal power supply. General pupose IO Inupt for IO Timer Ready input General pupose IO Trigger inupt for A/D Converter Clock output General pupose IO Input for UART 1 General pupose IO Input/Output for UART 1 General pupose IO Output for UART 1 General pupose IO CAN Transmit pin General pupose IO CAN receive pin FME EMDC June 19, 2000 MB90495 Series 6.2 I/O Circuit Types Circuit Drawing X1 01 X1A A X0 0011 10 01 01 01 X0A Comment Standby Control Signal B 00111100 C 01 HYS 01 HYS 0110 D 010101 HYS 01 Standby Control Signal 0011 01 E 01 1111 0000 010101 HYS 10 01 Standby Control Signal Analog 00111100 01 HYS F 0110 G 01 100101 11001100 10 01 01 HYS Standby Control Signal TTL MB90495 Series Data Sheet (Advance Information) 8 / 40 FMG EMDC June 19, 2000 MB90495 Series 7. HANDLING DEVICES (1) Preventing latch-up CMOS IC chips may suffer latch-up under the following conditions: A voltage higher than Vcc or lower than Vss is applied to an input or output pin. A voltage higher than the rated voltage is applied between Vcc and Vss. The AVcc power supply is applied before the Vcc voltage. Latch-up may increase the power supply current drastically, causing thermal damage to the device. (2) Handling unused input pins Do not leave unused input pins open, as doing so may cause misoperation of the device. Use a pull-up or pull-down resistor. (3) Using external clock To use external clock, drive the X0 and X1 pins in reverse phase. Below is a diagram of how to use external clock. MB90495 Series X0 X1 Figure 7.1 Using external clock (4) Power supply pins (Vcc/Vss) Ensure that all Vcc-level power supply pins are at the same potential. In addition, ensure the same for all Vss-level power supply pins. (See the figure below.) If there are more than one Vcc or Vss system, the device may operate incorrectly even within the guaranteed operating range. Note that this product may not have as many power pins as pictured in the figure. MB90495 Series Data Sheet (Advance Information) 9 / 40 FME EMDC June 19, 2000 MB90495 Series Vcc Vss Vcc Vss Vss Vcc MB90495 Series Vcc Vss Vss Vcc Figure 7.2 Power pin connections (5) Pull-up/down resistors The MB90495 Series does not support internal pull-up/down resistors. Use external components where needed. MB90495 Series Data Sheet (Advance Information) 10 / 40 FMG EMDC June 19, 2000 MB90495 Series 8. ADDRESS SPACE MB90V495 MB90F497 MB90497 ROM FF FLASH ROM FF ROM FF ROM FE No Acess FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH ROM FD FD0000H FCFFFFH ROM FC FC0000H FBFFFFH External bus access External bus access FF ROM mirror FF ROM mirror FF ROM mirror Extended I/O Extended I/O Extended I/O External bus access External bus access RAM mirror1 Do not use RAM mirror Do not use. RAM RAM I/O I/O ROM FB FB0000H FAFFFFH ROM FA FA0000H 010000H 00FFFFH 004000H 003FFFH 003800H 0018FFH 0010FFH 000900H 0008FFH RAM 000100H 0000BFH 000000H I/O 1. The RAM contents of 0000H - 08FFH is mirrored to 0900H - 10FFH. The RAM mirror area should not be accessed for proper operation. MB90495 Series Data Sheet (Advance Information) 11 / 40 FME EMDC June 19, 2000 MB90495 Series 9. REGISTER MAP Address Register Abbreviation Peripheral 00 H Port 0 data register PDR0 Port 0 R/W XXXXXXXX 01 H Port 1 data register PDR1 Port 1 R/W XXXXXXXX 02 H Port 2 data register PDR2 Port 2 R/W XXXXXXXX 03 H Port 3 data register PDR3 Port 3 R/W XXXXXXXX 04 H Port 4 data register PDR4 Port 4 R/W XXXXXXXX 05 H Port 5 data register PDR5 Port 5 R/W XXXXXXXX 06 H Port 6 data register PDR6 Port 6 R/W XXXXXXXX 10 H Port 0 direction register DDR0 Port 0 R/W 00000000 11 H Port 1 direction register DDR1 Port 1 R/W 00000000 12 H Port 2 direction register DDR2 Port 2 R/W 00000000 13 H Port 3 direction register DDR3 Port 3 R/W 00000000 14 H Port 4 direction register DDR4 Port 4 R/W 00000000 15 H Port 5 direction register DDR5 Port 5 R/W 00000000 16 H Port 6 direction register DDR6 Port 6 R/W 00000000 Analog Input Enable ADER Port 5, A/D R/W 11111111 Serial Mode Register 1 SMR0 R/W 00000000 07-0F H Reserved 17-1A H 1B H Reserved 1C - 1F H 20 H Access Initial value Reserved 21 H Serial Control Register 1 SCR0 R/W 00000100 22 H Input/Output Data Register 1 SIDR0/SODR0 R/W XXXXXXXX R/W 00001_00 R/W 0___1111 23 H Serial Status Register 1 SSR0 24 H UART 0 Prescaler Control Register CDCR0 UART0 25 H UART 0 edge select SES0 R/W _______1 26 H Serial Mode Control Register 1 SMC1 R/W 00XXXX00 27 H Serial Control Register SRC1 28 H Input/Output Data Register 1 SIDR1/SODR1 29 H Serial Status Register 1 SMC1 2A H 2B H UART1 R/W 00000X00 R/W XXXXXXXX R/W XXXXX000 R/W 0___0000 Reserved UART 1 Prescaler Control Register CDCR0 2C - 2F H Prescaler UART 1 Reserved 30 H External Interrupt Enable ENIR R/W 00000000 31 H External Interrupt Request EIRR R/W XXXXXXXX 32 H External Interrupt Level ELVR R/W 00000000 33 H External Interrupt Level ELVR R/W 00000000 External Interrupt 34 H A/D Control Status 0 ADCS0 R/W 00000000 34 H A/D Control Status 1 ADCS1 R/W 00000100 36 H A/D Data 0 ADCR0 37 H A/D Data 1 ADCR1 PPG0 operation mode control register PPGC0 38-3FH 40 H A/D Converter R XXXXXXXX R/W 00000_XX R/W 0_00X__1 R/W 0_00X001 R/W 000000__ Reserved 41 H PPG1 operation mode control register PPGC1 42 H PPG0 and PPG1 clock select register PPG01 MB90495 Series Data Sheet (Advance Information) 12 / 40 16-bit Programable Pulse Generator 0/1 FMG EMDC June 19, 2000 MB90495 Series Address Register Abbreviation PPG2 operation mode control register PPGC2 43 H 44 H Peripheral Access Initial value Reserved 16-bit Programable Pulse Generator 2/3 R/W 0_00X__1 R/W 0_00X001 R/W 000000__ R XXXXXXXX R XXXXXXXX R XXXXXXXX 45 H PPG3 operation mode control register PPGC3 46 H PPG2 and PPG3 clock select register PPG23 50 H Input Capture 0 IPCP0 51 H Input Capture 0 IPCP0 52 H Input Capture 1 IPCP1 53 H Input Capture 1 IPCP1 R XXXXXXXX 54 H Input Capture Control Status 0/1 ICS01 R/W XX000000 55 H Input Capture Control Status 2/3 ICS23 56 H Timer Data TCDT 47-4FH Reserved 57 H Timer Data TCDT 58 H Timer Control TCCS Input Captue 0/1 Input Capture 0/1/2/3 I/O Timer R/W XX000000 R/W 00000000 R/W 00000000 R/W 00000000 59 H Timer Control TCCS R/W 0__00000 5A H Input Capture 2 IPCP2 R XXXXXXXX R XXXXXXXX R XXXXXXXX R XXXXXXXX R/W 00000X00 R/W ____0000 R/W 00000X00 R/W ____0000 R/W 000____1 R/W 11000000 5B H Input Capture 2 IPCP2 5C H Input Capture 3 IPCP3 5D H Input Capture 3 5E - 65 H IPCP3 Reserved 66 H Timer Control Status 0 TMCSR0 67 H Timer Control Status 0 TMCSR0 68 H Timer Control Status 1 TMCSR1 69 H Timer Control Status 1 TMCSR1 ROM Mirror ROMM 6A - 6E H 6F H Input Captue 2/3 16-bit Reload Timer 0 16-bit Reload Timer 1 Reserved ROM Mirror 70-7F H Reserved 80-8F H Reserved for CAN 1 Interface . Refer to “CAN Controller” 90-9D H Reserved 9E H ROM Correction Control Status PACSR ROM Correction 9F H Delayed Interrupt/release DIRR Delayed Interrupt R/W _______0 A0 H Low-power Mode LPMCR Low Power Controller R/W 00011000 A1 H Clock Selector CKSCR Low Power Controller R/W 11111100 External Memory Access 0011__00 A2-A4 H Reserved A5 H Automatic ready function select reg. ARSR W A6 H External address output control reg. HACR W A7 H Bus control signal select register ECSR W A8 H Watchdog Control WDTC Watchdog Timer R/W XXXXX111 A9 H Time Base Timer Control TBTC Time Base Timer R/W 1__0X100 Flash Memory R/W 000X0000 AA-AD H AE H 00000000 0000000_ Reserved Flash Control Status (Flash only, otherwise reserved) FMCS AF H MB90495 Series Data Sheet (Advance Information) Reserved 13 / 40 FME EMDC June 19, 2000 MB90495 Series Address Register Abbreviation Peripheral Access Initial value B0 H Interrupt control register 00 ICR00 R/W 11000111 B1 H Interrupt control register 01 ICR01 R/W 11000111 B2 H Interrupt control register 02 ICR02 R/W 11000111 B3 H Interrupt control register 03 ICR03 R/W 11000111 B4 H Interrupt control register 04 ICR04 R/W 11000111 B5 H Interrupt control register 05 ICR05 R/W 11000111 B6 H Interrupt control register 06 ICR06 R/W 11000111 B7 H Interrupt control register 07 ICR07 R/W 11000111 B8 H Interrupt control register 08 ICR08 R/W 11000111 B9 H Interrupt control register 09 ICR09 R/W 11000111 BA H Interrupt control register 10 ICR10 R/W 11000111 BB H Interrupt control register 11 ICR11 R/W 11000111 BC H Interrupt control register 12 ICR12 R/W 11000111 BD H Interrupt control register 13 ICR13 R/W 11000111 Interrupt controller BE H Interrupt control register 14 ICR14 R/W 11000111 BF H Interrupt control register 15 ICR15 R/W 11000111 R/W XXXXXXXX CO-FF H Reserved 1FF0H1FF5H ROM correction 3900 H Timer 0/Reload 0 TMR0/TMRL0 3901 H Timer 0/Reload 0 TMR0/TMRL0 3902 H Timer 1/Reload 1 TMR1/TMRL1 3903 H Timer 1/Reload 1 TMR1/TMRL1 3904-390FH 16-bit Reload Timer 0 16-bit Reload Timer 1 R/W XXXXXXXX R/W XXXXXXXX R/W XXXXXXXX Reserved 3910 H PPG0 Reload L PRLL0 R/W XXXXXXXX 3911 H PPG0 Reload H PRLH0 R/W XXXXXXXX 16-bit Programable Pulse Generator 0/1 3912 H PPG1 Reload L PRLL1 R/W XXXXXXXX 3913 H PPG1 Reload H PRLH1 R/W XXXXXXXX 3914 H PPG2 Reload L PRLL2 R/W XXXXXXXX 3915 H PPG2 Reload H PRLH2 R/W XXXXXXXX R/W XXXXXXXX R/W XXXXXXXX 3916 H PPG3 Reload L PRLL3 3917 H PPG3 Reload H PRLH3 16-bit Programable Pulse Generator 2/3 3918-392FH Reserved 3930-3BFFH Reserved 3C003CFFH Reserved for CAN 1 Interface. Refer to “CAN Controller” 3D003DFFH Reserved for CAN 1 Interface. Refer to “CAN Controller” 3E00-3EFFH Reserved 3FF0-3FFFH Reserved MB90495 Series Data Sheet (Advance Information) 14 / 40 FMG EMDC June 19, 2000 MB90495 Series 10. CAN CONTROLLER The CAN controller has the following features: • Conforms to CAN Specification Version 2.0 Part A and B - Supports transmission/reception in standard frame and extended frame formats • Supports transmitting of data frames by receiving remote frames • 8 transmitting/receiving message buffers - 29-bit ID and 8-byte data - Multi-level message buffer configuration • Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as 1D acceptance mask - Two acceptance mask registers in either standard frame format or extended frame formats • Bit rate programmable from 10 Kbits/s to 2 Mbits/s (when input clock is at 16 MHz) MB90495 Series Data Sheet (Advance Information) 15 / 40 FME EMDC June 19, 2000 MB90495 Series 10.1 List of Control Registers Address Register Abbreviation Access Initial Value BVALR R/W 00000000 TREQR R/W 00000000 TCANR W 00000000 TCR R/W 00000000 RCR R/W 00000000 RRTRR R/W 00000000 ROVRR R/W 00000000 RIER R/W 00000000 Control status register CSR R/W, R 00---000 0----0-1 Last event indicator register LEIR R/W -------- 000-0000 Receive/transmit error counter RTEC R 00000000 00000000 Bit timing register BTR R/W -1111111 11111111 IDER R/W XXXXXXXX TRTRR R/W 00000000 RFWTR R/W XXXXXXXX TIER R/W 00000000 AMSR R/W XXXXXXXX XXXXXXXX 000080H Message buffer valid register 000081H Unused 000082H Transmit request register 000083H Unused 000084H Transmit cancel register 000085H Unused 000086H Transmit complete register 000087H Unused 000088H Receive complete register 000089H Unused 00008AH Remote request receiving register 00008BH Unused 00008CH Receive overrun register 00008DH Unused 00008EH Receive interrupt enable register 00008FH Unused 003D00H 003D01H 003D02H 003D03H 003D04H 003D05H 003D06H 003D07H 003D08H IDE register 003D09H Unused 003D0AH Transmit RTR register 003D0BH Unused 003D0CH Remote frame receive waiting register 003D0DH Unused 003D0EH Transmit interrupt enable register 003D0FH Unused 003D10H 003D11H 003D12H 003D13H Acceptance mask select register Unused 003D14H 003D15H 003D16H XXXXXXXX XXXXXXXX Acceptance mask register 0 AMR0 R/W XXXXX--- XXXXXXXX 003D17H 003D18H 003D19H 003D1AH XXXXXXXX XXXXXXXX Acceptance mask register 1 AMR1 XXXXX--- XXXXXXXX 003D1BH MB90495 Series Data Sheet (Advance Information) R/W 16 / 40 FMG EMDC June 19, 2000 MB90495 Series 10.2 List of Message Buffers (ID Registers) Address Register Abbreviation Access Initial Value 003C00H to 003C0FH General-purpose RAM -- R/W XXXXXXXX to XXXXXXXX 003C10H 003C11H 003C12H XXXXXXXX XXXXXXXX ID register 0 IDR0 R/W XXXXX--- XXXXXXXX 003C13H 003C14H 003C15H 003C16H XXXXXXXX XXXXXXXX ID register 1 IDR1 R/W XXXXX--- XXXXXXXX 003C17H 003C18H 003C19H 003C1AH XXXXXXXX XXXXXXXX ID register 2 IDR2 R/W XXXXX--- XXXXXXXX 003C1BH 003C1CH 003C1DH 003C1EH XXXXXXXX XXXXXXXX ID register 3 IDR3 R/W XXXXX--- XXXXXXXX 003C1FH 003C20H 003C21H 003C22H XXXXXXXX XXXXXXXX ID register 4 IDR4 R/W XXXXX--- XXXXXXXX 003C23H 003C24H 003C25H 003C26H XXXXXXXX XXXXXXXX ID register 5 IDR5 R/W XXXXX--- XXXXXXXX 003C27H 003C28H 003C29H 003C2AH XXXXXXXX XXXXXXXX ID register 6 IDR6 R/W XXXXX--- XXXXXXXX 003C2BH 003C2CH 003C2DH 003C2EH XXXXXXXX XXXXXXXX ID register 7 IDR7 R/W XXXXX--- XXXXXXXX 003C2FH MB90495 Series Data Sheet (Advance Information) 17 / 40 FME EMDC June 19, 2000 MB90495 Series 10.3 List of Message Buffers (DLC Registers and Data Registers) Address Register Abbreviation Access Initial Value DLC register 0 DLCR0 R/W ----XXXX DLC register 1 DLCR1 R/W ----XXXX DLC register 2 DLCR2 R/W ----XXXX DLC register 3 DLCR3 R/W ----XXXX DLC register 4 DLCR4 R/W ----XXXX DLC register 5 DLCR5 R/W ----XXXX DLC register 6 DLCR6 R/W ----XXXX DLC register 7 DLCR7 R/W ----XXXX 003C40H to 003C47H Data register 0 (8 bytes) DTR0 R/W XXXXXXXX to XXXXXXXX 003C48H to 003C4FH Data register 1 (8 bytes) DTR1 R/W XXXXXXXX to XXXXXXXX 003C50H to 003C57H Data register 2 (8 bytes) DTR2 R/W XXXXXXXX to XXXXXXXX 003C58H to 003C5FH Data register 3 (8 bytes) DTR3 R/W XXXXXXXX to XXXXXXXX 003C60H to 003C67H Data register 4 (8 bytes) DTR4 R/W XXXXXXXX to XXXXXXXX 003C68H to 003C6FH Data register 5 (8 bytes) DTR5 R/W XXXXXXXX to XXXXXXXX 003C70H to 003C77H Data register 6 (8 bytes) DTR6 R/W XXXXXXXX to XXXXXXXX 003C78H to 003C7FH Data register 7 (8 bytes) DTR7 R/W XXXXXXXX to XXXXXXXX 003C30H 003C31H 003C32H 003C33H 003C34H 003C35H 003C36H 003C37H 003C38H 003C39H 003C3AH 003C3BH 003C3CH 003C3DH 003C3EH 003C3FH MB90495 Series Data Sheet (Advance Information) 18 / 40 FMG EMDC June 19, 2000 MB90495 Series 11. INTERRUPTS Interrupt vector Interrupt cause Reset INT9 instruction Exception CAN RX CAN TX/NS Reserved Reserved External Interrupt INT0/INT1 Time Base Timer 16-bit Reload Timer 0 A/D Converter I/O Timer External Interrupt INT2/INT3 Reserved PPG 0/1 Input Capture 0 External Interrupt INT4/INT5 Input Capture 1 PPG 2/3 External Interrupt INT6/INT7 Watch Timer Reserved Input Capture 2/3 Reserved Reserved Reserved Reserved Reserved 16-bit Reload Timer 1 UART 0 RX UART 0 TX UART 1 RX UART 1 TX Flash Memory Delayed interrupt Interrupt control register DMA Ch. —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— Number Address Number Address # 08 # 09 # 10 # 11 # 12 # 13 # 14 # 15 # 16 # 17 # 18 # 19 # 20 # 21 # 22 # 23 # 24 # 25 # 26 # 27 # 28 # 29 # 30 # 31 # 32 # 33 # 34 # 35 # 36 # 37 # 38 # 39 # 40 # 41 # 42 FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H FFFF60H FFFF5CH FFFF58H FFFF54H —— —— —— —— —— —— ICR00 0000B0H ICR01 0000B1H ICR02 0000B2H ICR03 0000B3H ICR04 0000B4H ICR05 0000B5H ICR06 0000B6H ICR07 0000B7H ICR08 0000B8H ICR09 0000B9H ICR10 0000BAH ICR11 0000BBH ICR12 0000BCH ICR13 0000BDH ICR14 0000BEH ICR15 0000BFH MB90495 Series Data Sheet (Advance Information) 19 / 40 FME EMDC June 19, 2000 MB90495 Series 12. ELECTRICAL CHARACTERISTICS 12.1 Absolute Maximum Ratings (VSS = AVSS = 0 V) Parameter Symbol Rated Value Units Remarks Min. Max. VCC VSS – 0.3 VSS + 6.0 V AVCC VSS – 0.3 VSS + 6.0 V VCC = AVCC AVR VSS – 0.3 VSS + 6.0 V AVCC AVR AVss Input voltage VI VSS – 0.3 VSS + 6.0 V *2 Output voltage VO VSS – 0.3 VSS + 6.0 V *2 "L" level max. output current IOL — 15 mA "L" level avg. output current IOLAV — 4 mA "L" level max. overall output current IOL — 100 mA "L" level avg. overall output current IOLAV — 50 mA "H" level max. output current IOH — –15 mA "H" level avg. output current IOHAV — –4 mA "H" level max. overall output current IOH — -100 mA "H" level avg. overall output current IOHAV — -50 mA Power consumption PD — 300 mW Operating temperature TA –40 +85 °C TSTG –55 +150 °C Power supply voltage Storage temperature *1 Average value over a period of 100ms Average value over a period of 100ms Average value over a period of 100ms Average value over a period of 100ms *1: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the analog inputs does not exceed AVCC when the power is switched on. *2: VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximun current to/from a input is limited by some means with external components, the II rating supercedes the VI rating. MB90495 Series Data Sheet (Advance Information) 20 / 40 FMG EMDC June 19, 2000 MB90495 Series 12.2 Recommended Conditions (VSS = AVSS = 0 V) Parameter Power supply voltage Symbol Rated Value Min. Typ. Max. Unit s VCC AVCC 4.5 5.0 5.5 V Normal operating conditions 3.0 5.5 V Maintains RAM data in stop mode. VIHS 0.8 VCC VCC + 0.3 V CMOS hysteresis input pin VIHM VCC – 0.3 VCC + 0.3 V MD input pin VILS VSS – 0.3 0.2 VCC V CMOS hysteresis input pin VILM VSS – 0.3 VSS + 0.3 V MD input pin 1.0 µF Use a ceramic capacitor or capacitor of better AC characteristics. Capacitor at the VCC should be greater than this capacitor. +85 °C Remarks Input H voltage Input L voltage Smooth capacitor CS 0.022 Operating temperature TA –40 0.1 C CS Figure 12.1 C-Pin Connection Diagram MB90495 Series Data Sheet (Advance Information) 21 / 40 FME EMDC June 19, 2000 MB90495 Series 13. DC CHARACTERISTICS (TA = –40 to +85°C, VCC = 5.0 V 10%, VSS = AVSS = 0 V) Parameter Symbol Output H voltage VOH All output pins VCC = 4.5 V, IOH = –4.0 mA Output L voltage VOL All output pins Input leak current IIL Pin Rated Value Test Condition Max. VCC – 0.5 — — V VCC = 4.5 V, IOL = 4.0 mA — — 0.4 V VCC = 5.5 V, VSS < VI < VCC –5 — 5 µA — 35 40 mA MB90497 — 35 40 mA MB90F497 VCC = 5.0 V±10%, Int. frequency: 16 MHz, At flash programming 45 50 mA MB90F497 VCC = 5.0 V±10%, Int. frequency: 16 MHz, At flash erasing 45 50 mA MB90F497 — 11 18 mA MB90497 — 11 18 mA MB90F497 0.6 1.2 mA MB90497 0.6 1.2 mA MB90F497 — 16 20 µA MB90497 — 116 220 µA MB90F497 — 7.5 10 µA MB90497 — 8 20 µA MB90F497 — 3 5 µA MB90497 — 3 10 µA MB90F497 — 2 20 µA MB90497 — 2 20 µA MB90F497 — 10 80 pF VCC = 5.0 V±10%, Int. frequency: 16 MHz, At sleep ICCS ICTS Power supply current VCC * ICCL ICCLS ICCT ICCH Input capacity *: CIN Remarks Typ. VCC = 5.0 V±10%, Int. frequency: 16 MHz, At normal operating ICC Units Min. VCC = 5.0 V 10%, Int. frequency: 16 MHz, At timer mode VCC = 5.0 V, Int. frequency: 8 kHz, At sub operation VCC = 5.0 V, Int. frequency: 8 kHz, At sub sleep VCC = 5.0 V, Int. frequency: 8 kHz, At watch mode VCC = 5.0 V±10%, At stop, TA = 25°C Other than AVCC, AVSS, AVR, C, VCC, VSS — Current values are tentative. They are subject to change without notice according to improvements in the characteristics. The power supply current testing conditions are when using the external clock with square pulses. MB90495 Series Data Sheet (Advance Information) 22 / 40 FMG EMDC June 19, 2000 MB90495 Series 14. AC CHARACTERISTICS 14.1 Clock Timing (TA = –40 to +85°C, VCC = 5.0 V 10%, VSS = AVSS = 0 V) Parameter Symbol Pin fC Rated Value Units Min. Typ. Max. X0, X1 3 — 16 MHz fCL X0A, X1A — 32.768 — kHz tHCYL X0, X1 62.5 — 333 ns tLCYL X0A, X1A — 30.5 — µs ∆f — — — 5 % Remarks Oscillation frequency Oscillation cycle time Frequency deviation with PLL * Input clock pulse width Input clock rise and fall time PWH, PWL X0 10 — — ns PWLH,PWLL X0A — 15.2 — µs Duty ratio is about 30 to 70%. tCR, tCF X0 — — 5 ns When using external clock fCP — 1.5 — 16 MHz When using main clock fLCP — — 8.192 — kHz When using sub-clock tCP — 62.5 — 666 ns When using main clock tLCP — — 122.1 — µs When using sub-clock Machine clock frequency Machine clock cycle time *: Frequency deviation indicates the maximum frequency difference from the target frequency when using a multiplied clock. +a |a| ∆f = × 100% fO Central frequency fO –a tHCYL 0.8 VCC X0 0.2 VCC PWH PWL tCF tCR tLCYL 0.8 VCC X0A 0.2 VCC PWLH PWLL tCF MB90495 Series Data Sheet (Advance Information) tCR 23 / 40 FME EMDC June 19, 2000 MB90495 Series Guaranteed operation range for MB90F497, MB90497 5.5 4.5 Power supply voltage VCC (V) Guaranteed PLL operation 3.3 3.0 1.5 3 8 12 16 Machine clock fCP (MHz) Guaranteed operation range x4 16 x3 x1 x2 12 Machine clock fCP (MHz) 9 8 x 1/2 (PLL off) 4 3 4 8 16 Oscillation clock fC (MHz) Ocsillation clock frequency and Machine clock frequency Figure 14.1 Clock Timing AC characteristics are set to the measured reference voltage values below. • Output signal waveform • Input signal waveform Output Pin Hysteresis Input Pin 2.4 V 0.8 V 0.8 VCC 0.2 VCC Figure 14.2 Measured Reference Voltages MB90495 Series Data Sheet (Advance Information) 24 / 40 FMG EMDC June 19, 2000 MB90495 Series 14.2 Clock Output Timing (TA = –40 to +85°C, VCC = 5.0 V 10%, VSS = AVSS = 0.0 V) Parameter Cycle time Symbol Test Condition CLK VCC = 5 V ±10% tCYC CLK ↑ ⇒ CLK ↓ Rated Value Pin Units Min. Max. 62.5 — ns 20 — ns tCHCL Remarks tCYC tCHCL 2.4 V 2.4 V CLK 0.8 V Figure 14.3 Measured CLK timing MB90495 Series Data Sheet (Advance Information) 25 / 40 FME EMDC June 19, 2000 MB90495 Series 14.3 Reset Input (TA = –40 to +85°C, VCC = 5.0 V 10%, VSS = AVSS = 0.0 V) Parameter Reset input time Symbol Pin tRSTL RST Rated Value Min. Max. 16 tCP — Units Remarks ns “tcp” represents one cycle time of the machine clock. Any reset can not fully initialize the Flash Memory if it is performing the automatic algorithm. tRSTL, tHSTL RST 0.2 VCC 0.2 VCC Figure 14.4 Measured RST timing MB90495 Series Data Sheet (Advance Information) 26 / 40 FMG EMDC June 19, 2000 MB90495 Series 14.4 Power On Reset (TA = –40 to +85°C, VCC = 5.0 V 10%, VSS = AVSS = 0.0 V) Parameter Symbol Pin Power on rise time tR VCC Test Condition Rated Value Units Min. Max. 0.05 30 ms 50 — ms Remarks — Power off time tOFF VCC Due to repetitive operation tR 3.5 V VCC 0.2 V 0.2 V 0.2 V tOFF If you change the power supply voltage too rapidly, a power on reset may occur. We recommend that you startup smoothly by restraining voltages when changing the power supply voltage during operation, as shown in the figure below. Perform while not using the PLL clock. However, if voltage drops are within 1 mV/sec, you can operate while using the PLL clock. VCC We recommend a rise of 50 mV/ms maximum. 3V Holds RAM data VSS Figure 14.5 Power On Reset Timing MB90495 Series Data Sheet (Advance Information) 27 / 40 FME EMDC June 19, 2000 MB90495 Series 14.5 External Bus Timing (Read) (TA = –40 to +85°C, VCC = 4.5 to 5.5 V, VSS = 0 V) Parameter Test Condition Rated Value Symbol Pin ALE pulse width tLHLL ALE tCP/2 – 20 Valid address ⇒ ALE ↓ time tAVLL ALE, A23 - A16, AD15 - AD00 tCP/2 – 20 — ns ALE ↓ ⇒ Address valid time tLLAX ALE, AD15 - AD00 tCP/2 – 15 — ns Valid address ⇒ RD ↓ time tAVRL A23 - A16, AD15 - AD00, RD tCP – 15 — ns Valid address ⇒ Valid data input tAVDV A23 - A16, AD15 - AD00 — 5 tCP/2 – 60 ns RD pulse width tRLRH RD 3 tCP/2 – 20 — ns — 3 tCP/2 – 60 ns Min. Max. Units ns — RD ↓ ⇒ Valid data input tRLDV RD, AD15 - AD00 RD ↑ ⇒ Data hold time tRHDX RD, AD15 - AD00 0 — ns RD ↓ ⇒ ALE ↑ time tRHLH RD, ALE tCP/2 – 15 — ns RD ↑ ⇒ Address valid time tRHAX RD, A23 - A16 tCP/2 – 10 — ns Valid address ⇒ CLK ↑ time tAVCH A23 - A16, AD15 - AD00, CLK tCP/2 – 20 — ns RD ↓ ⇒ CLK ↑ time tRLCH RD, CLK tCP/2 – 20 — ns ALE ↓ ⇒ RD ↓ time tLLRL ALE, RD tCP/2 – 15 — ns MB90495 Series Data Sheet (Advance Information) Remarks 28 / 40 FMG EMDC June 19, 2000 MB90495 Series tRLCH tAVCH 2.4 V CLK 2.4 V tLLAX tAVLL ALE 2.4 V tRHLH 2.4 V 2.4 V 0.8 V tLHLL tAVRL tRLRH 2.4 V RD 0.8 V tLLRL tRHAX A23 to A16 2.4 V 2.4 V 0.8 V 0.8 V tRLDV tRHDX tAVDV AD15 to AD00 2.4 V 0.8 V Address 2.4 V 0.8 VCC 0.8 V 0.2 VCC 0.8 VCC Read data 0.2 VCC Figure 14.6 Bus Timing (Read) MB90495 Series Data Sheet (Advance Information) 29 / 40 FME EMDC June 19, 2000 MB90495 Series 14.6 External Bus Timing (Write) (TA = –40 to +85°C, VCC = 4.5 to 5.5 V, VSS = 0 V) Parameter Symbol Pin Valid address ⇒ WR ↓ time tAVWL WR pulse width Rated Value Test Condition Units Min. Max. A23 - A16, AD15 - AD00, WR tCP – 15 — ns tWLWH WR 3 tCP/2 – 20 — ns Valid data output ⇒ WR ↑ time tDVWH AD15 - AD00, WR 3 tCP/2 – 20 — ns WR ↑ ⇒ Data hold time tWHDX AD15 - AD00, WR 20 — ns WR ↑ ⇒ Address valid time tWHAX A23 - A16, WR tCP/2 – 10 — ns WR ↑ ⇒ ALE ↑ time tWHLH WR, ALE tCP/2 – 15 — ns WR ↓ ⇒ CLK ↑ time tWLCH WR, CLK tCP/2 – 20 — ns Remarks — tWLCH 2.4 V CLK tWHLH 2.4 V ALE tAVWL tWLWH 2.4 V WR (WRL, WRH) 0.8 V tWHAX A23 to A16 2.4 V 2.4 V 0.8 V 0.8 V tDVWH AD15 to AD00 2.4 V 0.8 V tWHDX 2.4 V 2.4 V Address 0.8 V Write data 0.8 V Figure 14.7 Bus Timing (Write) MB90495 Series Data Sheet (Advance Information) 30 / 40 FMG EMDC June 19, 2000 MB90495 Series 14.7 External Bus Ready Input Timing (TA = –40 to +85°C, VCC = 4.5 to 5.5 V, VSS = 0 V) Parameter RDY setup time Symbol Pin tRYHS RDY Rated Value Test Condition Units Min. Max. 45 — ns 0 — ns Remarks — RDY hold time tRYHH RDY Note: If the RDY setup time is insufficient, use the auto-ready function. 2.4 V CLK ALE RD/WR tRYHS 0.8 VCC RDY no WAIT is used. RDY When WAIT is used tRYHH 0.8 VCC 0.2 VCC Figure 14.8 Ready Input Timing MB90495 Series Data Sheet (Advance Information) 31 / 40 FME EMDC June 19, 2000 MB90495 Series 14.8 External Bus Hold Timing (TA = –40 to +85°C, VCC = 4.5 to 5.5 V, VSS = 0 V) Parameter Pin floating ⇒ HAK ↓ time HAK ↑ time ⇒ Pin valid time Symbol Pin tXHAL HAK Test Condition Rated Value Units Min. Max. 30 tCP ns tCP 2 tCP ns Remarks — tHAHV HAK Note: There is more than 1 cycle from when HRQ reads in until the HAK is changed. 2.4V HAK 0.8V tHAHV tXHAL Each pin 2.4V High impedance 0.8V 2.4V 0.8V Figure 14.9 Hold Timing MB90495 Series Data Sheet (Advance Information) 32 / 40 FMG EMDC June 19, 2000 MB90495 Series 14.9 UART1 Timing (TA = –40 to +85°C, VCC = 4.5 to 5.5 V, VSS = 0 V) Parameter Symbol Pin Symbol Serial clock cycle time tSCYC SCK1 SCK ↓ ⇒ SOT delay time tSLOV SCK1, SOT1 Valid SIN ⇒ SCK ↑ tIVSH SCK1, SIN1 SCK ↑ ⇒ Valid SIN hold time tSHIX SCK1, SIN1 Serial clock "H" pulse width tSHSL SCK1 Serial clock "L" pulse width tSLSH SCK1 Rated Value Test Condition Internal clock operation output pins are CL = 80 pF + 1 TTL. External clock operation output pins are CL = 80 pF + 1 TTL. Units Min. Max. 8 tCP — ns –80 80 ns 100 — ns 60 — ns 4 tCP — ns 4 tCP — ns — 150 ns SCK ↓ ⇒ SOT delay time tSLOV SCK1, SOT1 Valid SIN ⇒ SCK ↑ tIVSH SCK1, SIN1 60 — ns SCK ↑ ⇒ Valid SIN hold time tSHIX SCK1, SIN1 60 — ns Remarks Notes: 1. AC characteristic in CLK synchronized mode. 2. CL is load capacity value of pins when testing. 3. tCP is the machine cycle (Unit: ns). tSCYC SCK 2.4 V 0.8 V 0.8 V tSLOV SOT 2.4 V 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC Figure 14.10 Internal Shift Clock Mode MB90495 Series Data Sheet (Advance Information) 33 / 40 FME EMDC June 19, 2000 MB90495 Series tSLSH tSHSL 0.8 VCC SCK 0.2 VCC 0.8 VCC 0.2 VCC tSLOV SOT 2.4 V 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC Figure 14.11 External Shift Clock Mode MB90495 Series Data Sheet (Advance Information) 34 / 40 FMG EMDC June 19, 2000 MB90495 Series 14.10 Timer Related Resource Input Timing (TA = –40 to +85°C, VCC = 4.5 to 5.5 V, VSS = 0 V) Parameter Input pulse width Symbol Pin tTIWH TIN0, TIN1 tTIWL IN0 to IN3 Rated Value Test Condition Min. Max. Unit s — 4 tCP — ns Remarks 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tTIWH tTIWL Figure 14.12 Timer Input Timing MB90495 Series Data Sheet (Advance Information) 35 / 40 FME EMDC June 19, 2000 MB90495 Series 14.11 Timer Related Resource Output Timing (TA = –40 to +85°C, VCC = 4.5 to 5.5 V, VSS = 0 V) Parameter Symbol Pin Test Condition CLK ↑ ⇒ TOUT change time tTO TOT0 to TOT1, PPG0 to PPG3 — CLK Rated Value Min. Max. 30 — Units Remarks ns 2.4 V 2.4 V TOT/PPG 0.8 V tTO Figure 14.13 Timer Output Timing MB90495 Series Data Sheet (Advance Information) 36 / 40 FMG EMDC June 19, 2000 MB90495 Series 14.12 External Trigger Input Timing (TA = –40 to +85°C, VCC = 4.5 to 5.5 V, VSS = 0 V) Parameter Input pulse width Symbol Pin Test Condition tTRGH tTRGL INT0 to INT7, ADTG — Rated Value Min. Max. 5 tCP — Units Remarks ns 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tTRGH tTRGL Figure 14.14 External Trigger Input Timing MB90495 Series Data Sheet (Advance Information) 37 / 40 FME EMDC June 19, 2000 MB90495 Series 14.13 A/D Converter (TA = –40 to +85°C, 3.0 V ≤ AVR – AVSS, VCC = AVCC = 5.0 V 10%, VSS = AVSS = 0 V) Parameter Rated Value Symbol Pin Resolution — — — Conversion error — — — Nonlinearity error — — Differential nonlinearity error — Zero reading voltage Full scale reading voltage Min. Typ. Max. Units 10 bit — 5.0 LSB — — 2.5 LSB — — — 1.9 LSB VOT AN0 to AN7 AVSS – 3.5 AVSS +0.5 AVSS + 4.5 LSB VFST AN0 to AN7 AVR – 6.5 AVR –1.5 AVR + 1.5 LSB Conversion time — — — 176tCP — ns Sampling time — — — 64tCP — ns Analog port input current IAIN AN0 to AN7 — — 10 µA Analog input voltage range VAIN AN0 to AN7 AVSS — AVR V — AVR AVSS + 2.7 — AVCC V IA AVCC — 5 — mA IAH AVCC — — 5 µA IR AVR 200 400 600 µA IRH AVR — — 5 µA — AN0 to AN7 — — 4 LSB Reference voltage range Power supply current Reference voltage current Offset between input channels Remarks 1 LSB = AVR/1024 *1 *1 *1: When not operating A/D converter, this is the current (VCC = AVCC = AVR = 5.0 V) when the CPU is stopped. Terminology: Conversion error : Absolute maximum conversion deviation with respect to the theoretical conversion line. Nonlinearlity : Relative maximum conversion deviation with respect to the theoretical conversion line connecting to the device-unique zero reading voltage and full-scale reading voltage. Differential non-linearlity : Maximum conversion deviation in any two adjacent reading voltages with respect to the theoretical LSB conversion step. Zero-reading voltage : Input voltage which results in the minimum conversion value. Full-scale reading voltage : Input voltage which results in the maximum coversion value. Notes: 1. The accuracy gets worse as AVR - AVSS becomes smaller. 2. Analog input external circuit output impedance should use the following conditions: External circuit output impedance less than 15 kΩ 3. If the external circuit output impedance is too high, there may be insufficient time for sampling of the analog voltage. Converter C1 Analog input Figure 14.15 Analog Input pin MB90495 Series Data Sheet (Advance Information) 38 / 40 C0 FMG EMDC June 19, 2000 MB90495 Series 15. PACKAGE DIMENSIONS 14.00±0.20(.551±.008)SQ 48 33 12.00±0.10(.472±.004)SQ +0.20 1.50 –0.10 +.008 .059 –.004 49 (Mounting height) 32 9.75 (.384) REF 13.00 (.512) NOM 1 PIN INDEX 64 LEAD No. 17 1 0.65(.0256)TYP Details of "A" part 16 0.30±0.10 (.012±.004) "A" 0.13(.005) M +0.05 0.127 –0.02 0.10±0.10 (STAND OFF) (.004±.004) +.002 .005 –.001 0.10(.004) 0 C 10° 0.50±0.20 (.020±.008) 1994 FUJITSU LIMITED F64018S-1C-2 Figure 15.1 Package Code: FPT-64P-M09 MB90495 Series Data Sheet (Advance Information) 39 / 40 FME EMDC June 19, 2000 MB90495 Series 3.35(.132)MAX (Mounting height) 0.05(.002)MIN (STAND OFF) 24.70±0.40(.972±.016) 20.00±0.20(.787±.008) 51 33 52 32 14.00±0.20 (.551±.008) 18.70±0.40 (.736±.016) 12.00(.472) REF 16.30±0.40 (.642±.016) INDEX 64 20 "A" LEAD No. 19 1 1.00(.0394) TYP 0.40±0.10 (.016±.004) 0.15±0.05(.006±.002) 0.20(.008) M Details of "A" part Details of "B" part 0.25(.010) "B" 0.30(.012) 0.10(.004) 0.18(.007)MAX 18.00(.709)REF 0.63(.025)MAX 22.30±0.40(.878±.016) C 0 10° 1.20±0.20 (.047±.008) 1994 FUJITSU LIMITED F64013S-3C-2 Figure 15.2 Package Code FPT-64P-M06 MB90495 Series Data Sheet (Advance Information) 40 / 40 FMG EMDC June 19, 2000