FUJITSU MB90P663A

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13604-2E
16-bit Proprietary Microcontroller
CMOS
F2MC-16L MB90660A Series
MB90662A/663A/P663A
■ DESCRIPTION
MB90660A series microcontrollers are 16-bit microcontrollers optimized for high speed realtime processing of
consumer equipment and system control of air conditioner video cameras, VCRs, and copiers. Based on the
F2MC*-16 CPU core, an F2MC-16L is used as the CPU. This CPU includes high-level language-support
instructions and robust task switching instructions, and additional addressing modes.
Microcontrollers in this series have built-in peripheral resources including multi-function timers, 16-bit reload
timer four channels, 8-bit PWM one channel, UART one channel, 10-bit A/D eight converter channels, and
external interrupt eight channels.
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ FEATURES
• F2MC-16L CPU
• Minimum execution time: 62.5 ns/4 MHz oscillation (uses PLL multiplier): fastest speed at quadruple operation
• Instruction set optimized for controller applications
Upward compatibility at object level with the F2MC-16(H)
Various data types (bit, byte, word, long-word)
Higher speed due to review of instruction cycle
Expanded addressing modes: 23 types
High coding efficiency
Two access methods (bank system or linear pointer)
Improved multiply-and-divide instructions (additional signed instructions)
Improved high-precision operation with 32-bit accumulator
Extended intelligent I/O services (access area extended by 64 Kbytes)
Large memory space: 16 Mbytes
(Continued)
■ PACKAGE
64-pin Plastic SH-DIP
64-pin Plastic LQFP
(DIP-64P-M01)
(FPT-64P-M09)
MB90660A Series
(Continued)
• Improved instruction set applicable to high-level language (C) and multitasking
System stack pointer
Improved indirect instructions using various pointers
Barrel shift instruction
Stack check function
• Improved execution speed: 4-byte instruction queue
• Improved interrupt functions
• Automatic data transfer function independent of CPU
Peripheral Resources
• ROM: 16 Kbytes (MB90661A)
32 Kbytes (MB90662A)
48 Kbytes (MB90663A)
One-time PROM: 48 Kbytes (MB90P663A)
• RAM: 512 bytes (MB90661A)
1.64 Kbytes (MB90662A)
2 Kbytes (MB90663A/MB90P663A)
• General-purpose ports: Max. 51
• UART: 1 channel
Can be used for both asynchronous transfer and clocked serial (I/O extended serial) communications
• A/D converter: 10-bit, 8 channels
Includes 8-bit conversion mode
• 16-bit reload timer: 4 channels
• 8-bit PWM: 1 channel
• External interrupts: 8 channels
• 18-bit timebase timer with watchdog timer function
• PLL clock multiplier function
• CPU intermittent operation function
• Various standby modes
• Package: SH-DIP-64/LQFP-64 (0.65-mm pitch)
• CMOS technology
2
MB90660A Series
■ PRODUCT LINEUP
Part number
MB90P663A
MB90662A
MB90663A
Classification
OTPROM
MASK ROM
MASK ROM
ROM size
48 Kbytes
32 Kbytes
48 Kbytes
RAM size
2 Kbytes
1.64 Kbytes
2 Kbytes
Parameter
CPU functions
Number of basic instructions
Instruction bit length
Instruction length
Data bit length
Minimum execution time
Interrupt processing time
: 340
: 8/16 bits
: 1 to 7 bytes
: 1, 4, 8, 16, or 32 bits
: 62.5 ns/4 MHz (PLL 4 multiply)
: 1000 ns/16 MHz (minimum)
Ports
Input Ports
I/O ports (CMOS)
I/O ports (N channel open-drain)
Total
:4
: 39
:8
: 51
Packages
DIP-64P-M01
FPT-64P-M09
DIP-64P-M01
FPT-64P-M09
DIP-64P-M01
FPT-64P-M09
Multi-Function
Timer
14-bit up/down count timer × 1, buffered compare register × 4, buffered compare clear
register, zero detect terminal control, 4 output channels, non-overlapped 3-phase waveform
output, 3-phase independent dead time timer, 4-bit carrier counter
UART
Full duplex double buffer
Selectable clock synchronous/asynchronous operation
Built-in dedicated baud rate generator (During asynchronous operation: 62500, 31250,
19230, 9615, 4808, 2404, 1202 bps)
A/D Converter
10-bit precision × 8 channels
A/D conversion time
Startup trigger
Activiation
: 6.13 µs (98 machine cycles at 16 MHz machine clock,
includes sample hold time)
: Startup by software, external source, or multi-function
timer output (RT0) can be selected
: Single, scan (multiple channel continuous), continuous
(1 channel continuous), stop (synchronized with
conversion start in scan mode)
16-Bit Reload
Timer
16-bit reload timer operation (toggle output, one-shot output selectable)
(Count clock can be selected from 0.125 µs, 0.5 µs, or 2.0 µs at 16 MHz machine cycle)
Event count function selectable
4 channels built-in
8-Bit PWM
8-bit resolution PWM operation (arbitrary cycle: duty ratio pulse output)
(Count clock can be selected from 0.125 µs or 64.0 µs at 16 MHz machine cycle)
External Interrupts Number of inputs: 8
External interrupt mode (Interrupts can be generated by four types of request detect
sources)
PLL Function
1/2/3/4-time multiplier can be selected (Please set so as not to exceed guaranteed
operation frequency)
Miscellaneous
Items
VPP is shared with MD2
terminal (when writing the
EPROM)
—
—
3
MB90660A Series
■ PIN ASSIGNMENT
(TOP VIEW)
P66/RT0
DTTI
P40/SIN
P41/SOT
P42/SCK
P43/PWM
P44/INT0
P45/INT1
P46/INT2/TRG
P47/INT3/ATG
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AVCC
AVR
AVSS
P30
P31
P32
P33
MD0
RST
MD1
MD2
X0
X1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
(DIP-64P-M01)
4
VCC
P65/Z
P64/Y
P63/X
P62/RT3/W
P61/RT2/V
P60/RT1/U
VSS
P27/TIM3/INT7
P26/TIM2/INT6
P25/TIM1/INT5
P24/TIM0/INT4
P23
P22
P21
P20
P17
P16
P15
P14
P13
P12
P11
P10
P07
P06
P05
P04
P03
P02
P01
P00
MB90660A Series
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
P45/INT1
P44/INT0
P43/PWM
P42/SCK
P41/SOT
P40/SIN
DTTI
P66/RT0
VCC
P65/Z
P64/Y
P63/X
P62/RT3/W
P61/RT2/V
P60/RT1/U
VSS
(TOP VIEW)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P27/TIM3/INT7
P26/TIM2/INT6
P25/TIM1/INT5
P24/TIM0/INT4
P23
P22
P21
P20
P17
P16
P15
P14
P13
P12
P11
P10
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
P33
MD0
RST
MD1
MD2
X0
X1
VSS
P00
P01
P02
P03
P04
P05
P06
P07
P46/INT2/TRG
P47/INT3/ATG
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AVCC
AVR
AVSS
P30
P31
P32
(FPT-64P-M09)
5
MB90660A Series
■ PIN DESCRIPTION
Pin no.
SH-DIP*
1
30
31
2
LQFP*
22
23
Pin name
X0
X1
Circuit
type
A
Crystal oscillator pin (32 MHz).
(Oscillator)
33 to 40
25 to 32 P00 to P07
B
(CMOS)
General-purpose I/O ports.
41 to 48
33 to 40 P10 to P17
B
(CMOS)
General-purpose I/O ports.
49 to 52
41 to 44 P20 to P23
B
(CMOS)
General-purpose I/O ports.
53 to 56
45 to 48 P24 to P27
G
(CMOS)
General-purpose I/O ports.
This function is activated when the output specification of the
reload timer is “disabled”.
22 to 25
3
TIM0 to TIM3
I/O pins for reload timers 0 to 4.
Input is used only as necessary while serving as input for the
reload timer. It is therefore necessary to stop output
beforehand using other functions unless intentionally used
otherwise.
Their function as output terminals for the reload timer is
activated when the output specification is “enabled”.
INT4 to INT7
External interrupt request input pins.
Input is used only as necessary while external interrupts are
enabled. It is therefore necessary to stop output beforehand
using other functions unless intentionally used otherwise.
14 to 17 P30 to P33
59
P40
B
(CMOS)
E
(CMOS/H)
SIN
4
60
P41
SOT
*1: DIP-64P-M01
*2: FPT-64P-M09
General-purpose I/O ports.
General-purpose I/O port.
This function is always enabled.
UART serial data input pin.
Input is used only as necessary while serving as UART input.
It is therefore necessary to stop output beforehand using other
functions unless intentionally used otherwise.
E
(CMOS/H)
6
Function
General-purpose I/O port.
This function is activated when the serial data output
specification of the UART is “disabled”.
UART serial data output pin.
This function is activated when the serial data output
specification of the UART is “enabled”.
(Continued)
MB90660A Series
Pin no.
SH-DIP*1
LQFP*2
5
61
Pin name
P42
Circuit
type
E
(CMOS/H)
SCK
6
62
P43
E
PWM
63
64
P44 to P45
1
D
(CMOS/H)
P46
2
D
3 to 10
External interrupt request input pin.
Input is used only as necessary while external interrupts are
enabled.
TRG
Timer clear trigger input pin for multi-function timer.
Input is used only as necessary while multi-function timer
input is enabled.
P47
D
General-purpose input port.
This function is always active.
INT3
External interrupt request input pin.
Input is used only as necessary while external interrupts are
enabled.
ATG
Trigger input pin for the A/D converter.
Input is used only as necessary while the A/D converter is
performing input.
P50 to P57
AN0 to AN7
*1: DIP-64P-M01
*2: FPT-64P-M09
General-purpose input port.
This function is always active.
INT2
(CMOS/H)
11 to 18
General-purpose I/O ports.
This function is always active.
External interrupt request input pins.
Input is used only as necessary while external interrupts are
enabled.
(CMOS/H)
10
General-purpose I/O port.
This function is activated when the output specification of the
PWM is “disabled”.
PWM timer output pin.
This function is activated when the waveform output specification of the PWM timer is “enabled”.
INT0 to INT1
9
General-purpose I/O port.
This function is activated when the clock output specification
of the UART is “disabled”.
UART clock I/O pin.
This function is activated when the clock output specification
of the UART is “enabled”.
Input is used only as necessary while serving as UART input.
It is therefore necessary to stop output beforehand using other
functions unless intentionally used otherwise.
(CMOS/H)
7
8
Function
C
(AD)
Open-drain type I/O ports.
This function is enabled when the analog input enable register
specification is “port”.
Analog input pins for the A/D converter.
This function is enabled when the analog input enable register
specification is “AD”.
(Continued)
7
MB90660A Series
Pin no.
SH-DIP*1
LQFP*2
58
50
Pin name
P60
Circuit
type
E
(CMOS/H)
59
51
52
Multi-function timer waveform output pin.
This function is enabled when the multi-function timer output
specification is “enabled”.
U
3-phase waveform output pin.
This function is enabled when the 3-phase waveform output
specification is “enabled”.
P61
E
53
Multi-function timer waveform output pin.
This function is enabled when the multi-function timer output
specification is “enabled”.
V
3-phase waveform output pin.
This function is enabled when the 3-phase waveform output
specification is “enabled”.
P62
E
Multi-function timer waveform output pin.
This function is enabled when the multi-function timer output
specification is “enabled”.
W
3-phase waveform output pin.
This function is enabled when the 3-phase waveform output
specification is “enabled”.
P63
E
X
54
P64
Y
8
General-purpose I/O port.
This function is enabled when the 3-phase waveform output
specification is “disabled”.
3-phase waveform output pin.
This function is enabled when the 3-phase waveform output
specification is “enabled”.
E
(CMOS/H)
*1: DIP-64P-M01
*2: FPT-64P-M09
General-purpose I/O port.
This function is enabled when the multi-function timer
waveform output specification is “disabled” and the 3-phase
waveform output specification is “disabled”.
RT3
(CMOS/H)
62
General-purpose I/O port.
This function is enabled when the multi-function timer
waveform output specification is “disabled” and the 3-phase
waveform output specification is “disabled”.
RT2
(CMOS/H)
61
General-purpose I/O port.
This function is enabled when the multi-function timer
waveform output specification is “disabled” and the 3-phase
waveform output specification is “disabled”.
RT1
(CMOS/H)
60
Function
General-purpose I/O port.
This function is enabled when the 3-phase waveform output
specification is “disabled”.
3-phase waveform output pin.
This function is enabled when the 3-phase waveform output
specification is “enabled”.
(Continued)
MB90660A Series
(Continued)
Pin no.
SH-DIP*1
LQFP*2
63
55
Pin name
P65
Circuit
type
E
(CMOS/H)
Z
1
57
P66
E
RT0
58
DTTI
General-purpose I/O port.
This function is enabled when the 3-phase waveform output
specification is “disabled”.
3-phase waveform output pin.
This function is enabled when the 3-phase waveform output
specification is “enabled”.
(CMOS/H)
2
Function
General-purpose I/O port.
This function is enabled when the multi-function timer
waveform output specification is “disabled”.
Multi-function timer waveform output pin.
This function is enabled when the multi-function timer output
specification is “enabled”.
D
(CMOS/H)
3-phase waveform output disable input (DTTI) pin.
19
11
AVCC
Power
supply
Power supply for analog circuits.
Turn this power supply on/off by applying a voltage level
greater than AVCC to VCC.
20
12
AVR
Power
supply
Reference power supply for analog circuits.
Turn this pin on/off by applying a voltage level greater than
AVR to AVCC.
21
13
AVSS
Power
supply
Ground level for analog circuits.
26
28
29
18
20
21
MD0 to MD2
27
19
RST
F
(CMOS/H)
D
(CMOS/H)
Input pins for specifying operation mode.
Use these pins by directly connecting to VCC or VSS.
External reset request input pin.
64
56
VCC
Power
supply
Power supply for digital circuits.
32
57
24
49
VSS
Power
supply
Ground level for digital circuits.
*1: DIP-64P-M01
*2: FPT-64P-M09
9
MB90660A Series
■ I/O CIRCUIT TYPE
Type
A
Circuit
Remarks
Clock input
• 3 MHz to 32 MHz operation
• Oscillation feedback resistor: Approx. 1 M¾
Digital output
• CMOS level input and output
With standby control
• Pull-up option can be selected
With standby control
X1
X0
Standby control signal
B
Digital output
Standby control
signal
Digital input
C
• N-channel open-drain output
CMOS level hysteresis input
With A/D control
Digital output
A/D input
Digital input
A/D disable
D
• CMOS level hysteresis input
Without standby control
• Pull-up option can be selected
Without standby control
Digital input
(Continued)
10
MB90660A Series
(Continued)
Type
Circuit
Remarks
E
Digital output
• CMOS level output
• CMOS level hysteresis input
With standby control
• Pull-up option can be selected
With standby control
Digital output
Digital input
Standby control
signal
F
*2
*3
*1
Noise filter
Typ. 40 ns
Digital input
G
Digital output
• CMOS level input
(Mask ROM version uses CMOS hysteresis
input)
Without standby control
• Pull-up option can be selected for MD2 (*1)
Pull-up option can be selected for MD1/0 (*2)
Both without standby option
• The MB90P663A does not include a noise filter.
It also does not have a P channel protect Tr (*3)
for the MD2 pin or pull-down.
• CMOS level input and output
Without standby control
• Pull-up option can be selected
With standby control
Digital output
Digital input
11
MB90660A Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur with CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output
pins other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum
Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
To prevent the similar aftereffects, use also the utmost care not to allow the analog supply voltage to exceed the
digital supply voltage.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be pins should be connected to a pullup or pull-down resistor.
3. External Reset Input
When resetting by inputting “L” level to the RST pin, the “L” level must be input for at least 5 machine cycles to
ensure that internal reset has occurred. Be aware of this point when using external clock input.
4. VCC, VSS Pin
Be sure that both VCC and VSS are at the same voltage.
5. Notes on Using an External Clock
Drive X0 when using an external clock.
• Using an External Clock
MB90660A
X0
X1
6. Order of Power-on to A/D Converter and Analog Inputs
Power-off (AVCC, AVR) to the digital power supply (VCC) must be performed only after the A/D converter and the
analog inputs (AN0 to AN7) has been turned on.
Turning on or off should always be performed keeping AVR below AVCC.
Use caution for the input voltage not to exceed AVCC when the pin sharing the analog input for its function is
used as an input port.
7. Programming Mode
When the MB90P663A is shipped from Fujitsu, all bits (48 K × 8 bits) are set to “1”. Program by setting selected
bits to “0” when you wish to set the data. Note that “1” cannot be programming electrically.
12
MB90660A Series
8. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked
OTPROM microcomputer program.
Program and verify
Aging
150°C, 48 H
Data verification
Assembly
9. Programming Yields
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.
For this reason, a programming yield of 100% cannot be assured at all times.
10.Fluctuations in Supply Voltage
Although the assured VCC supply voltage operating range is as specified, sudden fluctuations even within this
range may cause a malfunction. Therefore, the voltage supply to the IC should be kept as constant as possible.
The VCC ripple (P-P value) at the supply frequency (50 to 60 Hz) should be less than 10% of the typical VCC
value, or the coefficient of excessive variation should not be more than 0.1 V/ms instantaneous change when
power is supplied.
13
MB90660A Series
■ PROGRAMMING THE MB90P663A EPROM
Since the MB90P663A is functionally equivalent to the MBM27C1000 when it is in EPROM mode, it is possible
to program them with a general-purpose EPROM programmer by using a special adaptor socket.
However, the MB90660A does not support the electronic signature (device ID code) mode.
1. Pin Assignment in EPROM Mode
• MBM27C1000-compatible pins
MBM27C1000
Pin no.
MB90P663A
Pin name
Pin no.
SH-DIP
LQFP
Pin name
Pin no.
Pin name
MB90P663A
Pin no.
SH-DIP
LQFP
Pin name
1
VPP
29
21
MD2 (VPP)
32
VCC
64
56
VCC
2
OE
24
16
P32
31
PGM
25
17
P33
3
A15
48
40
P17
30
NC
—
—
—
4
A12
45
37
P14
29
A14
47
39
P16
5
A07
56
48
P27
28
A13
46
38
P15
6
A06
55
47
P26
27
A08
41
33
P10
7
A05
54
46
P25
26
A09
42
34
P11
8
A04
53
45
P24
25
A11
44
36
P13
9
A03
52
44
P23
24
A16
22
14
P30
10
A02
51
43
P22
23
A10
43
35
P12
11
A01
50
42
P21
22
CE
23
15
P31
12
A00
49
41
P20
21
D07
40
32
P07
13
D00
33
25
P00
20
D06
39
31
P06
14
D01
34
26
P01
19
D05
38
30
P05
15
D02
35
27
P02
18
D04
37
29
P04
16
GND
—
—
—
17
D03
36
28
P03
• Power supply, GND connection pins
Type
14
MBM27C1000
Pin no.
Pin name
SH-DIP
LQFP
Power
2
64
58
56
DTTI
VCC
GND
57
21
27
32
26
3
4
5
49
13
19
24
18
59
60
61
VSS
AVSS
RST
VSS
MD0
P40
P41
P42
MB90660A Series
• Pins other than MBM27C1000-compatible pins
Pin no.
Pin name
Processing
SH-DIP
LQFP
30
28
22
20
X0
MD1
Pull-up by
4.7 KΩ
31
23
X1
OPEN
9
10
11 to 18
19
20
58 to 63
1
6 to 8
1
2
3 to 10
11
12
50 to 55
57
62 to 64
P46
P47
P50 to P57
AVCC
AVR
P60 to P65
P66
P43 to P45
1 MΩ-level
pull-up resistor
connected to
each pin
2. EPROM Programmer Socket Adapter and Recommended Programmer Manufacturer
Part no.
Package
Compatible socket
adapter
Sun Hayato Co., Ltd.
Recommended programmer manufacturer
and programmer name
Minato
Electronics Inc.
Data I/O Co.,
Ltd.
Advantest Corp.
MB90P663AP
SH-DIP-64 ROM-64SD-32DP-16L
Recommended
Recommended
Recommended
MB90P663APF
LQFP-64
Recommended
Recommended
Recommended
ROM-64SF-32DP-16L
Inquiry: Sun Hayato Co., Ltd.: TEL (81)-3-3986-0403
FAX (81)-3-5396-9106
Minato Electronics Inc.: TEL: USA (1)-916-348-6066
JAPAN (81)-45-591-5611
Data I/O Co., Ltd.: TEL: USA/ASIA (1)-206-881-6444
EUROPE (49)-8-985-8580
Advantest Corp.: TEL: Except JAPAN (81)-3-3930-4111
15
MB90660A Series
3. Programming Data
(1) Adjust the EPROM programmer to settings for the MBM27C1000.
(2) Load program data from addresses 10000H to 1FFFFH in the EPROM programmer.
OTPROM addresses FF4000H to FFFFFFH of the MB90P663A in operation mode correspond to addresses
14000H to 1FFFFH in EPROM mode.
Operation mode
FFFFFFH
EPROM mode
1FFFFH
OTPROM
OTPROM
FF4000H
14000H
FF0000H
10000H
(3) Set the MB90P663A into the adaptor socket and install the adaptor socket into the EPROM programmer.
Pay attention to the orientation of the device and the adaptor socket at this time.
(4) Programming data to the EPROM.
(5) If data cannot be programmed, try again with a 0.1 µF capacitor connected between VCC and GND and VPP
and GND.
Note: Since Mask ROM products (MB90662A/663A) do not include an EPROM mode, data cannot be read-out
using an EPROM programmer.
16
MB90660A Series
4. PROM Option Bitmap
The programming method is the same as a PROM, and can be set by programming values to addresses indicated
in the memory map.
The following bit map shows the relation between bits and options.
• PROM Option Bitmap
Address
Bit
7
6
5
4
3
2
1
0
00004H
P07
Pull-up
1: No
0: Yes
P06
Pull-up
1: No
0: Yes
P05
Pull-up
1: No
0: Yes
P04
Pull-up
1: No
0: Yes
P03
Pull-up
1: No
0: Yes
P02
Pull-up
1: No
0: Yes
P01
Pull-up
1: No
0: Yes
P00
Pull-up
1: No
0: Yes
00008H
P17
Pull-up
1: No
0: Yes
P16
Pull-up
1: No
0: Yes
P15
Pull-up
1: No
0: Yes
P14
Pull-up
1: No
0: Yes
P13
Pull-up
1: No
0: Yes
P12
Pull-up
1: No
0: Yes
P11
Pull-up
1: No
0: Yes
P10
Pull-up
1: No
0: Yes
0000CH
P27
Pull-up
1: No
0: Yes
P26
Pull-up
1: No
0: Yes
P25
Pull-up
1: No
0: Yes
P24
Pull-up
1: No
0: Yes
P23
Pull-up
1: No
0: Yes
P22
Pull-up
1: No
0: Yes
P21
Pull-up
1: No
0: Yes
P20
Pull-up
1: No
0: Yes
00010H
P43
Pull-up
1: No
0: Yes
P42
Pull-up
1: No
0: Yes
P41
Pull-up
1: No
0: Yes
P40
Pull-up
1: No
0: Yes
P33
Pull-up
1: No
0: Yes
P32
Pull-up
1: No
0: Yes
P31
Pull-up
1: No
0: Yes
P30
Pull-up
1: No
0: Yes
00014H *1 P47
Pull-up
1: No
0: Yes
P46
Pull-up
1: No
0: Yes
P45
Pull-up
1: No
0: Yes
P44
Pull-up
1: No
0: Yes
RST
Pull-up
1: No
0: Yes
DTTI
Pull-up
1: No
0: Yes
Accept asynchronous
reset
1: Yes
0: No
MD1/MD0*2
Pull-up
1: No
0: Yes
P66
Pull-up
1: No
0: Yes
P65
Pull-up
1: No
0: Yes
P64
Pull-up
1: No
0: Yes
P63
Pull-up
1: No
0: Yes
P62
Pull-up
1: No
0: Yes
P61
Pull-up
1: No
0: Yes
P60
Pull-up
1: No
0: Yes
00018H
Open
Initially (value when blank), all bits are “1”.
*1: Under this release, the pull-up resistor is cut-off during stop mode for pins for which the pull-up option was
selected. (Pins for which the circuit type shown in the “■ Pin Description” is B or E.)
However, the pull-up resistor is not cut-off even in stop mode for P44 to 47, RST, DTTI (pins for which the circuit
type shown in the “■ Pin Description” is D or G), and MD1 and MD0.
*2: Whether or not a pull-up/pull-down resistor is present for MD2, MD1 and MD0 is determined as follows. If pullup/pull-down resistor is selected, it is included with all 2 (or 3) pins. Presence or absence of the pull-up or pulldown resistors for the mode terminal cannot be selected for each pin.
Pin
MB90P663A
MB90663A/2A
MD2
No
Pull-down can be selected
MD1
With pull-up resistor
With pull-up resistor
MD0
With pull-up resistor
With pull-up resistor
Notes: • “FFH” must be set to addresses no defined in the table above.
• Since the option setting for the MB90P663A takes 8 machine cycles, the option setting is not made until
a clock is provided after power-on. (This results in no pull-up for all pins, and asynchronous reset input is
accepted.)
17
MB90660A Series
■ BLOCK DIAGRAM
X0, X1
RST
MD0 to MD2
CPU
F2MC-16L family core
Clock
controller
External interrupts
RAM
INT0 to INT7
Interrupt controller
SIN
SOT
SCK
AVcc
AVR
AVss
AN0 to AN7
ATG
F2MC-16 bus
ROM
UART
Multi-function timer
(Dead time timer)
10-bit
A/D converter
16-bit timer
TIM0 to TIM3
8-bit PWM
PWM
I/O ports
8
8
8
4
8
8
7
P00
to
P07
P10
to
P17
P20
to
P27
P30
to
P33
P40
to
P47
P50
to
P57
P60
to
P66
Note: In the diagram above, I/O ports share pins with all internal function blocks. These
cannot be used as I/O ports when used as internal module pins.
18
TRG
DTTI
RT0 to RT3
U, V, W
X, Y, Z
MB90660A Series
■ F2MC-16L CPU PROGRAMMING MODEL
• Dedicated Registers
AH
AL
Accumulator
USP
User stack pointer
SSP
System stack pointer
PS
Processor status
PC
Program counter
DPR
Direct page register
PCB
Program bank register
DTB
Data bank register
USB
User stack bank register
SSB
System stack bank register
ADB
Additional data bank register
8 bits
16 bits
32 bits
• General-purpose Registers
32 banks max.
R7
R6
RW7
R5
R4
RW6
R3
R2
RW5
R1
R0
RW4
RL3
RL2
RW3
RL1
RW2
RW1
RL0
RW0
000180H + RP ∗ 10H→
16 bits
• Processor States (PS)
ILM
RP
—
I
S
T
N
Z
V
C
CCR
19
MB90660A Series
■ MEMORY MAP
FFFFFF H
Single chip
ROM area
Address1#
FF0000 H
010000 H
ROM area
(FF bank image)
Address2#
004000 H
002000 H
Address3#
000380 H
RAM
Registers
000180 H
000100 H
: Internal
0000C0 H
Peripheral resources
: Access disabled
000000 H
Product Model
20
Address #1
Address #2
Address #3
MB90662A
FF8000H
008000H
000780H
MB90663A
FF4000H
004000H
000900H
MB90P663A
FF4000H
004000H
000900H
MB90660A Series
■ I/O MAP
Address
Register
Name
Access*2
Resource name
Initial value
000000H
Port 0 data register
PDR0
R/W*
Port 0
XXXXXXXX
000001H
Port 1 data register
PDR1
R/W*
Port 1
XXXXXXXX
000002H
Port 2 data register
PDR2
R/W*
Port 2
XXXXXXXX
000003H
Port 3 data register
PDR3
R/W*
Port 3
– – – – XXXX
000004H
Port 4 data register
PDR4
R/W!
Port 4
XXXXXXXX
000005H
Port 5 data register
PDR5
R/W*
Port 5
11111111
000006H
Port 6 data register/
Port data buffer register
PDR6/
PDBR
R/W*
Port 6
– XXXXXXX
000007H to
Vacancy
0FH
—
*1
—
—
000010H
Port 0 direction register
DDR0
R/W
Port 0
00000000
000011H
Port 1 direction register
DDR1
R/W
Port 1
00000000
000012H
Port 2 direction register
DDR2
R/W
Port 2
00000000
000013H
Port 3 direction register
DDR3
R/W
Port 3
––––0000
000014H
Port 4 direction register
DDR4
R/W
Port 4
––––0000
000015H
Analog input enable register
ADER
R/W
Port 5
11111111
000016H
Port 6 direction register
DDR6
R/W
Port 6
–0000000
000017H
to 1BH
Vacancy
—
*1
—
—
00001CH
to 1FH
System reserved area
—
*1
—
—
000020H
PWM operation mode control
register
000021H
Vacancy
000022H
000023H
PWM reload register
PWMC
—
R/W
*1
XXXXXXXX
PRLH
R/W
XXXXXXXX
00000–00
SMR
R/W!
000025H
Serial control register
SCR
R/W!
000026H
Serial input data register/
Serial output data register
SIDR/
SODR
R/W
000027H
Serial status register
SSR
R/W!
000028H
Interrupt enable register
ENIR
R/W
000029H
Interrupt source register
EIRR
R/W
Request level setting register
ELVR
R/W
A/D control status register
ADCS
R/W!
00002CH
00002DH
—
R/W
Serial mode register
00002BH
PWM
PRLL
000024H
00002AH
00000––1
00000100
UART
XXXXXXXX
00001–00
External interrupt
00000000
XXXXXXXX
External interrupt
00000000
00000000
A/D converter
00000000
00000000
(Continued)
21
MB90660A Series
(Continued)
Address
00002EH
00002FH
000030H
000031H
000032H
000033H
000034H
000035H
000036H
000037H
000038H
000039H
00003AH
00003BH
00003CH
00003DH
00003EH
Register
Name
Access*2
A/D data register
ADCR
R/W!
Control status register
TMCSR0
R/W
Resource name
A/D converter
TMR0/
TMRLR0
R/W
Control status register
TMCSR1
R/W
TMR1/
TMRLR1
R/W
Control status register
TMCSR2
R/W
TMR2/
TMRLR2
R/W
Control status register
TMCSR3
R/W
––––0000
XXXXXXXX
00000000
––––0000
XXXXXXXX
XXXXXXXX
00000000
16-bit
reload timer 2
16-bit timer register/
16-bit reload register
0 0 0 0 0 0XX
XXXXXXXX
16-bit
reload timer 1
16-bit timer register/
16-bit reload register
XXXXXXXX
00000000
16-bit
reload timer 0
16-bit timer register/
16-bit reload register
Initial value
––––0000
XXXXXXXX
XXXXXXXX
00000000
16-bit
reload timer 3
––––0000
XXXXXXXX
00003FH
16-bit timer register/
16-bit reload register
TMR3/
TMRLR3
R/W
000040H
Timer control status register
TCSR
R/W!
10000000
000041H
Compare interrupt control register
CICR
R/W
00000000
000042H
Timer mode control register
TMCR
R/W!
001–0000
000043H
Compare/data select register
COER
R/W
––––0000
000044H
Compare buffer mode control
register
CMCR
R/W
––––0000
000045H
Zero detect output control register
ZOCTR
W
000046H
Output control buffer register
OCTBR
R/W
000047H
Zero detect interrupt control register
ZICR
R/W!
Output compare buffer register 0
OCPBR0
W
Output compare buffer register 1
OCPBR1
W
Output compare buffer register 2
OCPBR2
W
000048H
000049H
00004AH
00004BH
00004CH
00004DH
XXXXXXXX
–––X0000
Multi-function
timer
11111111
0 – – – XXXX
XXXXXXXX
– – XXXXXX
XXXXXXXX
– – XXXXXX
XXXXXXXX
– – XXXXXX
(Continued)
22
MB90660A Series
(Continued)
Address
Name
Access*2
Output compare buffer register 3
OCPBR3
W
Compare clear buffer register
CLRBR
W
000052H
Dead time control register
DTCR
R/W!
00000000
000053H
Dead time setting register
DTSR
W
XXX 0 XXXX
000054H
Dead time compare register
DTCMR
W
XXXXXXXX
000055H
Vacancy
00004EH
00004FH
000050H
000051H
000056H
000057H
Register
Timer pin control register
000058H
to 5EH
Vacancy
00005FH
Machine clock division control
register
—
TPCR
Resource name
XXXXXXXX
– – XXXXXX
00000000
Multi-function
timer
*1
R/W
Initial value
—
16-bit reload
timer
––000000
—
–001–000
–011–010
—
*1
CDCR
W
000060H to
Vacancy
8FH
—
*1
—
—
000090H to
System reserved area
9EH
—
*1
—
—
Delayed interrupt
generator module
–––––––0
00009FH
Delayed interrupt source generate/
cancel register
DIRR
R/W
0000A0H
Low power mode control register
LPMCR
R/W!
0000A1H
Clock select register
CKSCR
R/W!
0000A2H to
System reserved area
A7H
—
*1
—
UART
—
––––1111
Low power
—
00011000
11111100
—
0000A8H
Watchdog timer control register
WDTC
R/W!
Watchdog timer
X –XXX1 1 1
0000A9H
Timebase timer control register
TBTC
R/W!
Timebased timer
1––00100
0000AAH
to AFH
System reserved area
*1
—
—
0000B0H
Interrupt control register 00
ICR00
R/W!
00000111
0000B1H
Interrupt control register 01
ICR01
R/W!
00000111
0000B2H
Interrupt control register 02
ICR02
R/W!
00000111
0000B3H
Interrupt control register 03
ICR03
R/W!
0000B4H
Interrupt control register 04
ICR04
R/W!
0000B5H
Interrupt control register 05
ICR05
R/W!
00000111
0000B6H
Interrupt control register 06
ICR06
R/W!
00000111
0000B7H
Interrupt control register 07
ICR07
R/W!
00000111
—
Interrupt
controller
00000111
00000111
(Continued)
23
MB90660A Series
(Continued)
Address
Register
Name
Access*2
Resource name
Initial value
0000B8H
Interrupt control register 08
ICR08
R/W!
00000111
0000B9H
Interrupt control register 09
ICR09
R/W!
00000111
0000BAH
Interrupt control register 10
ICR10
R/W!
00000111
0000BBH
Interrupt control register 11
ICR11
R/W!
0000BCH
Interrupt control register 12
ICR12
R/W!
0000BDH
Interrupt control register 13
ICR13
R/W!
00000111
0000BEH
Interrupt control register 14
ICR14
R/W!
00000111
0000BFH
Interrupt control register 15
ICR15
R/W!
00000111
0000C0H
to FFH
System reserved area
—
*1
Interrupt
controller
—
00000111
00000111
—
*1: Access prohibited
*2: Registers marked “R/W!” in the access column include some bits that can only be read or only be written. For
details, see the register list for each resource.
* : When a register marked “R/W!”, “R/W*” or “W” in the access column is accessed by a read-modify-write
instruction (such as a bit set instruction), the bit operated on by the instruction will be set to the specified value,
but a malfunction will occur if there are any other bits which can only be written. Therefore, do not access these
locations using these instructions.
Description of Initial Values
0: The initial value of this bit is “0”.
1: The initial value of this bit is “1”.
*: The initial value of this bit is “1” or “0”. (This is determined depending on the level of the MD0 to MD2 pins.)
X: The initial value of this bit is undefined.
–: This bit is not used. The initial value is undefined.
Note: The initial value results for bits which can only be written when initialized by a reset. Note that this is not the
value when read.
Also, sometimes LPMCR, CKSCR and WDTC are initialized and sometimes they are not depending on the
type of reset. If they are initialized, the initial value is used.
24
MB90660A Series
■ INTERRUPT SOURCES, INTERRUPT VECTORS
AND INTERRUPT CONTROL REGISTERS
Interrupt source
Interrupt vector
I2OS
support
Number
Interrupt control register
Address
ICR
Address
Reset
×
#08
08H
FFFFDCH
—
—
INT9 instruction
×
#09
09H
FFFFD8H
—
—
Exception
×
#10
0AH
FFFFD4H
—
—
Multi-function timer DTTI input
×
#12
0CH
FFFFCCH
External interrupt #0
#13
0DH
FFFFC8H
External interrupt #4
#14
0EH
FFFFC4H
Multi-function timer trigger input or
zero detect
#15
0FH
Multi-function timer zero detect
#17
Multi-function timer overflow, compare
clear or zero detect
External interrupt #1
ICR00
0000B0H
ICR01
0000B1H
FFFFC0H
ICR02
0000B2H
11H
FFFFB8H
ICR03
0000B3H
#19
13H
FFFFB0H
ICR04
0000B4H
#21
15H
FFFFA8H
ICR05
0000B5H
#22
16H
FFFFA4H
#23
17H
FFFFA0H
ICR06
0000B6H
#24
18H
FFFF9CH
External interrupt #2
#25
19H
FFFF98H
ICR07
0000B7H
External interrupt #6
#26
1AH
FFFF94H
16-bit reload timer #0
#27
1BH
FFFF90H
ICR08
0000B8H
16-bit reload timer #1
#28
1CH
FFFF8CH
16-bit reload timer #2
#29
1DH
FFFF88H
ICR09
0000B9H
16-bit reload timer #3
#30
1EH
FFFF84H
End of A/D converter conversion
#31
1FH
FFFF80H
ICR10
0000BAH
#34
22H
FFFF74H
ICR11
0000BBH
UART send complete
#35
23H
FFFF70H
ICR12
0000BCH
UART receive complete
#37
25H
FFFF68H
ICR13
0000BDH
External interrupt #3
#39
27H
FFFF60H
ICR14
0000BEH
External interrupt #7
#40
28H
FFFF5CH
#42
2AH
FFFF54H
ICR15
0000BFH
Multi-function timer compare match
×
External interrupt #5
PWM underflow
Timebase timer interval interrupt
Delayed interrupt generator module
×
×
×
: indicates that the interrupt request flag is cleared by the I2OS interrupt clear signal (no stop request).
: indicates that the interrupt request flag is cleared by the I2OS interrupt clear signal (with stop request).
: indicates that the interrupt request flag is not cleared by the I2OS interrupt clear signal.
Note: Do not specify I2OS activation in interrupt control registers that do not support I2OS.
25
MB90660A Series
■ PERIPHERAL RESOURCES
1. Parallel Port
The MB90660A includes 39 I/O pins, 4 input pins, and 8 open-drain output pins.
Port 0, 1, 2, 3 and 6 are I/O ports. They are used for input when the corresponding direction register value is
“0”, and for output when the value is “1”.
Port 5 is an open-drain port. It is used as a port when the analog input enable register is “0”.
Ports 40 to 43 are I/O ports. They are used for input when the corresponding direction register value is “0”, and
for output when the value is “1”. Ports 44 to 47 are input ports which can only be used for reading data.
(1) Register Configuration
bit
Port Data Register
Address : PDR1 000001H
: PDR3 000003H
bit
Port Data Register
Address : PDR0 000000H
: PDR2 000002H
: PDR6 000006H
(PDBR)
Read/Write
Initial value
bit
13
12
bit
Read/Write
Initial value
10
9
8
PD×7 PD×6 PD×5 PD×4 PD×3 PD×2 PD×1 PD×0
7
6
5
4
3
2
1
PDR1, 3
0
PD×7 PD×6 PD×5 PD×4 PD×3 PD×2 PD×1 PD×0
PDR0, 2, 6
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
15
14
13
12
11
10
9
8
PDR5
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
7
6
5
4
3
2
1
0
PD47 PD46 PD45 PD44 PD43 PD42 PD41 PD40
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
Notes: There are no register bits for bits 15 to 12 of Port 3.
There is no register bit for bit 7 of Port 6.
Bits 7 to 4 of Port 4 can only be used to read data.
26
11
PD57 PD56 PD55 PD54 PD53 PD52 PD51 PD50
Read/Write
Initial value
Port Data Register
Address : 000004H
14
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
Read/Write
Initial value
Port Data Register
Address : 000005H
15
(R/W) (R/W) (R/W) (R/W)
(X)
(X)
(X)
(X)
PDR4
MB90660A Series
Port Direction Register bit
Address : DDR1 000011H
: DDR3 000013H
15
14
13
12
11
10
9
8
DD×7 DD×6 DD×5 DD×4 DD×3 DD×2 DD×1 DD×0
DDR1, 3
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Read/Write
Initial value
bit
Port Direction Register
Address : DDR0 000010H
: DDR2 000012H
: DDR4 000014H
: DDR6 000016H
Read/Write
Initial value
7
6
5
4
3
2
1
0
DD×7 DD×6 DD×5 DD×4 DD×3 DD×2 DD×1 DD×0
DDR0, 2, 4, 6
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Notes: There are no register bits for bits 15 to 12 of Port 3.
There are not register bits for bits 7 to 4 of Port 4
There is no DDR for Port 5.
There is no register bit for bit 7 of Port 6.
Analog Input Enable Register
Address : 000015H
Read/Write
Initial value
bit
15
14
13
12
11
10
9
8
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
ADER
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
27
MB90660A Series
(2) Block Diagrams
• I/O Ports
Internal data bus
Data register read
Pin
Data register
Data register write
Direction register
Direction register write
Direction register read
• Open-drain Ports (Also Used for Analog Input)
Internal data bus
RMW
(Read-modifywrite instruction)
Pin
Data register read
Data register
Data register write
ADER
ADER register write
ADER register read
Internal data bus
• Input Ports
28
Pin
Data register read
MB90660A Series
2. Multi-function Timer
The multi-function timer controls up to 7 realtime output pins, and includes the following functions.
• Interval timer function
It can output pulses or generate an interrupt at a fixed interval.
• PWM output function
Can perform output for a fixed cycle pulse while changing the duty ratio (ratio between “L” output width and
“H” output width) in realtime.
• 3-phase AC sine wave output (inverter control output) function
Can perform 3-phase AC sine wave output using AC motor inverter control, etc. (using any setting for the nonoverlap interval)
This timer also has the following characteristics.
• Pulse cycle control using 14-bit timer
A machine cycle of 1, 2, 8 or 16 can be selected based on pre-scalars as the clock source (Minimum resolution
of 62.5 ns at 16 MHz operation).
Can use a carrier frequency up to 30 KHz at 8-bit stop when used for AC motor control.
Up count only or up/down count can be selected using the count mode selection.
Possessing a buffer, cycle can be changed in realtime by transferring data from buffer upon zero detect.
• Duty control using compare registers
Possessing four compare registers, output pulse duty can be set for four separate channels.
Each possessing a separate buffer, duty can be changed in realtime by transferring data from buffer upon zero
detect or comparison.
• Non-overlap control using dead time timer
Dead time timer can be used to generate PWM output for three channels or even reversed signals with nonoverlap, thus allowing an AC motor control wave (U, V, W, X, Y, Z) to be generated.
A machine cycle of 1, 4, 8 or 32 can be selected based on pre-scalars as the clock source for the dead timer
(Minimum resolution of 62.5 ns at 16 MHz operation)
• Forced stop control using DTTI pin input
The forced pin output level can be fixed by DTTI pin input or software.
Inactive control can be performed during AC motor control using DTTI pin input.
External pin control even during vibration stop can be performed through clockless DTTI pin input.
• Event detection and interrupt generation using various flags
Flags can be set and/or interrupts generated upon zero detect, overflow, detect of match with compare registers,
or clear by TRG pin input, or any match of the compare registers for the four channels for the 14-bit timer (also
possible to disable interrupt output).
29
MB90660A Series
(1) Register Configuration
000040H
000041H
000042H
000043H
000044H
8 bits
TCSR
CICR
TMCR
COER
CMCR
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Timer control status register
Compare interrupt control register
Timer mode control register
Compare/data select register
Compare buffer mode control register
Address : 000045H
ZOCTR
(W)
Zero detect output control register
Address :
Address :
Address :
Address :
Address :
OCTR
Output control register
Address : 000046H
OCTBR
(R/W) Output control buffer register
Address : 000047H
ZICR
(R/W) Zero detect interrupt control register
14 bits
Output compare registers 0 to 3
OCPR0 to 3
Address : 000048H
to
: 00004FH
30
OCPBR0 to 3
(W)
Output compare buffer registers 0 to 3
CLRR
(W)
Compare clear register
Address : 000050H
: 000051H
CLRBR
(W)
Compare clear buffer register
Address : 000052H
Address : 000053H
Address : 000054H
DTCR
DTSR
DTCMR
(R/W) Dead time timer control register
Dead time setting register
(W)
Dead time compare register
(W)
Address : 000006H
PDBR
14 bits
(W)
Port data buffer register
MB90660A Series
(2) Block Diagrams
• Timer/wave generator block diagram
CLRR, CLRBR
Reverse
or Clear
TRG
(External Input)
Interrupt Control
Comparator
14-bit Timer
STCR, TMST, MODE
CES1, 0
TCS1, 0
Count Clock
Pre-scalar
(1, 2, 8 or 16 machine cycles)
IIOS
TCIE, TCIR
TZIE, TZIR
TMIE, TMIR
CIE3 to 0, CIR3 to 0
Timer Clear
Zero detect interrupt
Zero detect
Zero detect interrupt mask
Timer interrupt
Compare interrupt
ZOSC, IME, CYC3 to 0
14
Zero detect
Zero detect pin control
ZSB0
Comparator, pin control
Set, Reset
Set, Reset,
Transfer
RO01, 0
PDR6
PD66
RT0
(External Output)
OCPR0, OCPBR0
Zero detect pin control
Set, Reset
ZSB1
Comparator, pin control
RO11, 0
Set, Reset,
Transfer
PDR6
PD60
RT1
(to Output Selector)
OCPR1, OCPBR1
Zero detect pin control
ZSB2
Comparator, pin control
RO21, 0
Set, Reset
Set, Reset,
Transfer
PDR6
PD61
RT2
(to Output Selector)
OCPR2, OCPBR2
Zero detect pin control
Set, Reset
ZSB3
Transfer request
Buffer transfer control
TREN, TMSK, BFS1, 0
Set, Reset,
Comparator, pin control Transfer
RO31, 0
PDR6
PD62
RT3
(to Output Selector)
OCPR3, OCPBR3
31
MB90660A Series
• Output selector/dead time generator block diagram
DTTI interrupt
DTIE, DTIF
DTTI Interrupt
Flag set
DTTI control
DTTI
(External input)
Inactive
TOCE, TOC1, 0
NRSL
RT1
(from wave
generator)
P60/RT1/U
Comparator
Compare
Dead time
wave
generator
U
Selector
X
P63/X
(External output)
8-bit timer
Count clock
Mode select
Active level
Pre-scalar
Inactive
Division select
RT2
(from wave
generator)
P61/RT2/V
Comparator
Compare
Dead time
wave
generator
V
Selector
P64/Y
(External output)
Y
8-bit timer
Active level
Count clock
Mode select
Pre-scalar
Inactive
Division select
RT3
(from wave
generator)
P62/RT3/W
Comparator
Compare
Dead time
wave
generator
W
Selector
(External output)
Z
8-bit timer
Active level
Count clock
Pre-scalar
Division select
Wave control
8
DTCMR
32
DMOD, DT1, 0
DCS1, 0
P65/Z
Mode select
MB90660A Series
3. UART
The UART is a serial I/O port for asynchronous (start/stop) or CLK synchronous communications with external
resources. It has the following characteristics:
•
•
•
•
Full duplex double buffering
Asynchronous (start/stop) or CLK synchronous communications
Multiprocessor mode support
Internal dedicated baud-rate generator
Asynchronous
: 19230/9615/31250/4808/2404/1202 bps
CLK synchronous
•
•
•
•
: 2 M/1 M/500 K/250 K bps
Free baud-rate setting based on external clock
Error detection functions (parity, framing and overrun)
Use of NRZ coded transfer signal
Supports intelligent I/O services
(1) Register Configuration
15
8 7
SCR
SSR
0
SMR
SIDR (R)/SODR (W)
CDCR
8 bits
bit
(R/W)
(R/W)
(W)
8 bits
7
6
5
4
3
2
MD1
MD0
CS2
CS1
CS0
–
15
14
13
12
11
10
9
8
PEN
P
SBL
CL
A/D
REC
RXE
TXE
bit
7
6
5
4
3
2
1
0
Address : 000026H
D7
D6
D5
D4
D3
D2
D1
D0
bit
15
14
13
12
11
10
9
8
Address : 000027H
PE
ORE
–
RIE
TIE
bit
15
14
13
12
10
9
8
–
–
–
–
Address : 000024H
bit
Address : 000025H
Address : 00005FH
FRE RDRF TDRE
11
1
0
SCKE SOE
DIV3 DIV2 DIV1 DIV0
Serial mode register
(SMR)
Serial control register
(SCR)
Serial input register
Serial output register
(SIDR/SODR)
Serial status register
(SSR)
Machine clock
division control register
(CDCR)
33
MB90660A Series
(2) Block Diagram
Control signal
Receive interrupt
(to CPU)
Dedicated baud
rate generator
SCK
16-bit timer0
(connected internally)
Send interrupt
(to CPU)
Transfer clock
Clock selector
Receive clock
External clock
Receive controller
SIN
Send controller
Start bit
detect circuit
Send start circuit
Receive bit
counter
Send bit counter
Receive parity
counter
Send parity
counter
SOT
Receive shifter
Receive status
determination circuit
Send shifter
Send start
Receive end
SODR
SIDR
Receive error
generator signal for EI2OS
(to CPU)
F2MC-16 bus
SMR
register
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
SCR
register
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR
register
PE
ORE
FRE
RDRF
TDRE
RIE
TIE
Control signal
34
MB90660A Series
4. 10-bit, 8-channel A/D Converter (with 8-bit Resolution Mode)
This 10-bit, 8-channel A/D converter is used to convert analog input voltage to corresponding digital values. It
has the following features.
• Conversion time: 6.13 µs per channel (includes sample and hold time at 98 machine cycles/machine clock
of 16 MHz)
• Sample hold time: 3.75 µs per channel (60 machine cycles per machine clock of 16 MHz)
• RC-type sequential approximation conversion with sample and hold circuits
• 10-bit or 8-bit resolution
• Analog input can be selected from 8 channels
Single conversion mode
: One channel selected for conversion
Scan conversion mode
: Consecutive multiple channels converted (programmable with max. eight
channels)
Repetitive conversion mode : Data on the specified channel is converted repeatedly
Stop conversion mode
: Once one channel is converted, operations stop and the device waits until
started again (conversion start can be synchronized)
• At the end of each A/D conversion, an interrupt request to the CPU can be generated. This interrupt can be
used to activate I2OS or transfer A/D conversion results to memory, making it useful when continuous
processing is desired.
• Conversion can be triggered by software, an external trigger (falling edge), and/or a timer (rising edge).
(1) Register Configuration
bit
15
14
A/DControl status register (upper)
BUSY INT
Address : 00002DH
bit
A/D Control status register (lower)
Address : 00002CH
bit
Read/Write
Initial value
Read/Write
Initial value
11
10
7
MD1
6
9
INTE PAUS STS1 STS0 STRT
5
4
3
2
8
Reserved
(W)
(0)
(–)
(0)
1
0
MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
ADCS
ADCS
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Read/Write
Initial value
A/D Data register (lower)
Address : 00002EH
12
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
Read/Write
Initial value
A/D Data register (upper)
Address : 00002FH
13
bit
15
14
13
12
11
10
9
8
S10
–
–
–
–
–
D9
D8
(R/W)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(X)
(R)
(X)
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
ADCR
ADCR
35
MB90660A Series
(2) Block Diagram
AVCC
AVR
AVSS
D/A converter
MPX
Sequential
comparison register
Input circuit
Comparator
Data bus
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Decoder
Sample and
hold circuits
Data register
ADCR0, 1
A/D control register 1
A/D control register 2
ADCS0, 1
ATG
Trigger start
Operation clock
Multi-function timer
(RT0 output)
Peripheral clock
36
Timer start
Pre-scalar
MB90660A Series
5. PWM Timer
This block, which is an 8-bit reload timer module, outputs the pulse width modulation (PWM) using pulse output
control corresponding to the timer operation.
In terms of hardware, this block possesses an 8-bit down counter, two 8-bit reload registers for setting “L” width
and “H” width, a control register, external pulse output pin, and interrupt output circuit to achieve the following
functions.
• PWM output operation
: Pulse waves of any period and duty factor are output.
This block can also be used as a D/A converter with an external circuit.
Interrupt requests can be output based on counter underflow.
(1) Register Configuration
PWM operation mode
control register
Address: 000020H
PWM reload register
000022H
(Functions)
8 bits
000023H
PWMC (R/W)
Operation mode control
PRLL
(R/W)
Hold “L” pulse width reload value
PRLH
(R/W)
Hold “H” pulse width reload value
(2) Block Diagram
PWM
Output enabled
(Port)
TBT output main clock divided by 4
TBT output main clock divided by 512
TBT: Timebase timer
PWMO
Output latch
Reverse
Clear
PEN
PCNT
(down counter)
IRQ
Count clock
selection
Reload
L/H select
L/H selector
PRLL
PRLBH
PWMC
PRLH
Operation mode
control
F2MC-16 bus
37
MB90660A Series
6. 16-bit Reload Timer (with Event Count Function)
The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload register, control register, and 4 timer
pins (I/O set by timer pin select register). Three internal clocks and an external clock can be selected as input
clocks. A toggle output waveform is output at the output pin (TOT) in reload mode, while a square wave indicating
that the timer is counting is output at the output pin in single-shot mode. The input pin (TIN) can be used for
event input in even count mode, and for trigger input or gate input in internal clock mode.
This product has this timer built into four channels.
(1) Register Configuration
Control status register (upper)
bit
Address : channel 0 000031H
: channel 1 000035H
: channels 2 000039H
: channels 3 00003DH
Read/Write
Initial value
15
14
13
12
11
10
9
8
–
–
–
–
CSL1 CSL0 MOD2 MOD1
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
Control status register (lower)
bit
7
6
5
4
3
2
1
0
Address : channel 0 000030H
: channel 1 000034H
MOD0 Reserved OUTL RELD INTE UF CNTE TRG
: channels 2 000038H
: channels 3 00003CH
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Read/Write
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Initial value
16-bit timer register (upper)
16-bit reload register (upper)
Address : channel 0 000033H
: channel 1 000037H
: channels 2 00003BH
: channels 3 00003FH
Read/Write
Initial value
bit
16-bit timer register (lower)
16-bit reload register (lower)
Address : channel 0 000032H
: channel 1 000036H
: channels 2 00003AH
: channels 3 00003EH
Read/Write
Initial value
bit
Timer pin control register (upper)
Address : 000057H
Read/Write
Initial value
38
14
13
12
11
10
9
8
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
7
6
5
4
3
2
1
0
TMR/
TMRLR
0 to 3
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
bit
Read/Write
Initial value
Timer pin control register (lower)
Address : 000056H
15
TMCSR
0 to 3
bit
15
14
13
12
11
10
9
8
–
OTE3 CSB3 CSA3
–
OTE2 CSB2 CSA2
(–)
(–)
(R/W) (R/W) (R/W)
(0)
(1)
(1)
(–)
(–)
(R/W) (R/W) (R/W)
(0)
(1)
(0)
7
6
5
4
3
2
1
0
–
OTE1 CSB1 CSA1
–
OTE0 CSB0 CSA0
(–)
(–)
(R/W) (R/W) (R/W)
(0)
(0)
(1)
(–)
(–)
(R/W) (R/W) (R/W)
(0)
(0)
(0)
TPCR
MB90660A Series
(2) Block Diagram
16
16-bit reload register
8
Reload
RELD
UF
16-bit down counter
16
OUTL
F2MC-16 bus
2
OUT
CTL
GATE
INTE
UF
IRQ
CSL1
Clock selector
CNTE
CSL0
TRG
Trigger
Clear
I2OSCLR
2
IN CTL
TIN
EXCK
φ φ φ
– – –
21 23 25
3
Prescaler
clear
TOT
MOD2
Serial baud rate
(channel 0 only)
MOD1
Peripheral clock
MOD0
3
I/O pins for timer*
TIN0
TOT0
TIM0
16-bit reload timer
Channel 1
TIN1
TOT1
TIM1
16-bit reload timer
Channel 2
TIN2
TOT2
16-bit reload timer
Channel 3
TIN3
TOT3
Selector
16-bit reload timer
Channel 0
TIM2
TIM3
* : Timer channel and direction (I/O) can be selected for each pin.
39
MB90660A Series
7. External Interrupts
In addition to “H” and “L”, rising and falling edge can be selected as the external interrupt level for a total of four
interrupt level types.
(1) Register Configuration
bit
Interrupt enable register
Address : 000028H
bit
5
4
3
2
1
0
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
ENIR
15
14
13
12
11
10
9
8
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
EIRR
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Read/Write
Initial value
bit
Request level setting register (upper)
Address : 00002BH
15
14
13
12
11
10
9
8
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Read/Write
Initial value
bit
Request level setting register (lower)
Address : 00002AH
Read/Write
Initial value
6
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Read/Write
Initial value
Interrupt source register
Address : 000029H
7
7
6
5
4
3
2
1
0
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
ELVR
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(2) Block Diagram
F2MC-16 bus
8
Source F/F
8
16
40
Interrupt enable register
Interrupt source register
Request level setting register
Gate
Edge detector
8
8
IRQ
Request input
MB90660A Series
8. Delayed Interrupt Generation Module
The delayed interrupt generation module is used to generate an interrupt for task switching. If this module is
used, an interrupt request to the F2MC-16L CPU can be generated or cancelled by software.
(1) Register Configuration
Delayed interrupt request
generation/cancel register
Address : 000009H
Read/Write
Initial value
bit
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
R0
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(R/W)
(0)
DIRR
The DIRR register controls the generation and cancellation of delayed interrupt requests. A delayed interrupt
request is generated when “1” is written to this register, while a delayed interrupt request is cancelled when “0”
is written here. Request cancel status results upon reset. Although either “0” or “1” may be written into reserved
bits, we recommend using the set bit and clear bit instructions when accessing this register in consideration of
possible future extensions.
F2MC-16 bus
(2) Block Diagram
Delayed interrupt source generation/
cancel decoder
Source latch
41
MB90660A Series
9. Watchdog Timer and Timebase Timer Functions
The watchdog timer consists of a 2-bit watchdog counter using carry signals from the 18-bit timebase timer as
the clock source, a control register, and a watchdog reset controller.
In addition to an 18-bit timer, the timebase timer consists of a circuit for controlling interval interrupts. Note that
the timebase timer uses the main clock regardless of the status of the MCS bit within the CKSCR register.
(1) Register Configuration
bit
Watchdog timer
control register
Address : 0000A8H
Read/Write
Initial value
bit
Timebase timer
control register
Address : 0000A9H
Read/Write
Initial value
7
6
5
4
3
2
1
PONR
–
(R)
(X)
(–)
(–)
(R)
(X)
(R)
(X)
(R)
(X)
(W)
(1)
(W)
(1)
(W)
(1)
15
14
13
12
11
10
9
8
Reserved
–
–
(–)
(1)
(–)
(–)
(–)
(–)
WRST ERST SRST WTE WT1
0
WT0
TBIE TBOF TBR TBC1 TBC0
(R/W) (R/W)
(0)
(0)
(W)
(1)
WDTC
TBTC
(R/W) (R/W)
(0)
(0)
(2) Block Diagram
Main clock
(OSC oscillation)
TBTC
212
214
216
219
TBTRES
TBC1
Selector
TBC0
TBR
TBIE
AND
Clock input
22
Timebase timer
to PWM timer
29
212 214 216 219
S
Q R
F2MC-16 bus
TBOF
Timebase
interrupt
WDTC
WT1
Selector
WT0
2-bit counter
OF
CLR
Watchdog reset
generator
CLR
to WDGRST
internal reset
generator
WTE
PONR
from power-on generator
WRST
42
ERST
RST pin
SRST
from RST bit of
STBYC register
MB90660A Series
10. Low Power Consumption Controller (CPU intermittent operation function, stable oscillation
wait time, and clock multiplier function)
The following operation modes are available: PLL clock mode, PLL sleep mode, clock mode, main clock mode,
main sleep mode and stop mode. Operation modes other than PLL clock mode are classified as low power
consumption modes.
Main clock mode and main sleep mode are modes where the microcontroller operates using the main clock
(OSC oscillation clock) only. In these modes, the main clock divided by two is used as the operation clock and
the PLL clock (VCO oscillation clock) is stopped.
In PLL sleep mode and main sleep mode, only the operation clock of the CPU is stopped, while operations
besides the CPU clock continue.
In clock mode, only the timebase timer is allowed to operate.
In stop mode, oscillation is stopped, allowing data to be held at the lowest power consumption possible.
The CPU intermittent operation function causes the clock provided to the CPU to function intermittently when
accessing registers, internal memory, internal resources and the external bus. This allows processing to be
performed at lower power consumption by reducing the CPU execution speed while continuing to provide a high
speed clock to internal resources.
The PLL clock multiplier can be selected as 1, 2, 3 or 4 using the CS1 and CS0 bits.
The stable oscillation wait time for the main clock when stop mode is cancelled can be set using the WS1 and
WS0 bits.
(1) Register Configuration
Low power consumption mode bit
control register
Address : 0000A0H
Read/Write
Initial value
Clock selection register
Address : 0000A1H
Read/Write
Initial value
bit
7
6
5
4
3
2
1
0
STP
SLP
SPL
RST
Reserved
CG1
CG0
Reserved
(W)
(0)
(W)
(0)
(R/W)
(0)
(W)
(1)
(–)
(1)
15
14
13
12
11
10
9
8
Reserved
MCS
CS1
CS0
Reserved
(–)
(1)
MCM WS1 WS0
(R)
(1)
(R/W) (R/W)
(1)
(1)
(–)
(1)
(R/W) (R/W)
(0)
(0)
LPMCR
(–)
(0)
CKSCR
(R/W) (R/W) (R/W)
(1)
(0)
(0)
43
MB90660A Series
(2) Block Diagram
CKSCR
MCM
PLL multiplier
circuit
MCS
1
2
3
4
Main clock
(OSC oscillation)
1
2
CPU clock
Clock generator
for CPU
CKSCR
CS1
CPU
CS0
Clock selector
0, 9, 17 or 33
intermittent cycle select
F2MC-16 bus
LPMCR
CG1
CPU intermittent
operation function
CG0
Cycle count selector
SLP
Standby controller
STP
RST cancel
Peripheral resource
clock
Clock generator
for peripheral
resources
LPMCR
Interrupt request
or RST
CKSCR
WS1
WS0
Stable
oscillation
wait time
selector
24
213
215
218
Clock input
to PWM timer
Timebase timer
LPMCR
SPL
Pin high-impedance controller
LPMCR
22
29
212 214 216 219
Pin HI-Z
RST pin
Internal reset generator
RST
Internal RST
to watchdog timer
WDGRST
44
MB90660A Series
11. Interrupt Controller
The interrupt control register is located within the interrupt controller. Its status conforms to all I/O possessed
by the interrupt function. This register includes the following three functions.
• Sets the interrupt level of the corresponding peripheral resource
• Selects whether to use conventional interrupts or extended intelligent I/O services for the interrupt of the
corresponding peripheral resource
• Selects the channel for the extended intelligent I/O services
(1) Register Configuration
Interrupt control register
bit
15
14
13
12
11
10
9
8
Address : ICR01 0000B1H
: ICR03 0000B3H
: ICR05 0000B5H
ICS1 ICS0
: ICR07 0000B7H
ICS3 ICS2
or
ISE
IL2
IL1
IL0
or
: ICR09 0000B9H
S1
S0
: ICR11 0000BBH
: ICR13 0000BDH
: ICR15 0000BFH
Read/Write
Initial value
(W)
(0)
(W)
(0)
ICR01, 03, 05, 07,
09, 11, 13, 15
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(1)
(1)
(1)
Interrupt control register
bit
7
6
5
4
3
2
1
0
Address : ICR00 0000B0H
: ICR02 0000B2H
: ICR04 0000B4H
ICS1 ICS0
: ICR06 0000B6H
ICS3 ICS2
or
ISE
IL2
IL1
IL0
or
: ICR08 0000B8H
S1
S0
: ICR10 0000BAH
: ICR12 0000BCH
: ICR14 0000BEH
(W)
(W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Read/Write
(0)
(0)
(0)
(0)
(0)
(1)
(1)
(1)
Initial value
ICR00, 02, 04, 06,
08, 10, 12, 14
Note: Since read-modify-write type instructions can cause a malfunction, do not access using these instructions.
45
MB90660A Series
(2) Block Diagram
4
ISE
IL2
IL1
4
IL0
I2OS select
ICS3
ICS2
S1
S0
ICS1
ICS0
4
4
32
3
Selects I2OS vector
4
Interrupt request/
I2OS request
(peripheral resource)
(CPU)
Interrupt level
I2OS vector
(CPU)
F2MC-16 bus
4
Determines interrupt/I2OS
priority level
2
46
2
Detects I2OS end condition
2
I2OS end condition
MB90660A Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Rating
Parameter
(VSS = AVSS = 0.0 V)
Symbol
Unit
Min.
Max.
VSS – 0.3
VSS + 7.0
V
AV *
VSS – 0.3
VSS + 7.0
V
AVR 1
VSS – 0.3
VSS + 7.0
V
VCC
Power supply voltage
Value
CC 1
V
*
Remarks
Programming voltage
VPP
VSS – 0.3
13.0
V
Input voltage*2
VI
VSS – 0.3
VCC + 0.3
V
Output voltage*2
VO
VSS – 0.3
VCC + 0.3
V
IOL1
—
10
mA
*7
IOL2
—
30
mA
*8
IOLAV1
—
4
mA
*7
IOLAV2
—
20
mA
*8
²IOLAV1
—
30
mA
*7
²IOLAV2
—
60
mA
*8
“H” level maximum output current*3
IOH
—
–10
mA
“H” level average output current*4
IOHAV
—
–4
mA
“H” level total average output current*5
²IOHAV
—
–40
mA
Power consumption
Pd
—
400
mW
Operating temperature
TA
–40
+85
°C
Storage temperature
Tstg
–55
+150
°C
“L” level maximum current*3
“L” level average output current*4
“L” level total average output current*5
*1:
*2:
*3:
*4:
*5:
*6:
*7:
*8:
*6
AVCC and VAVR must not exceed VCC.
VI and VO must not exceed VCC + 0.3 V.
Maximum output current specifies the peak value of one corresponding pin.
Average output current specifies the average current within a 100 ms interval flowing through one corresponding
pin.
Average total output current specifies the average current within a 100 ms interval flowing through all
corresponding pins.
MD2 pin of MB90P663A
Pins excluding P60/RT1/U, P61/RT2/V, P62/RT3/W, P63/X, P64/Y and P65/Z pins
P60/RT1/U, P61/RT2/V, P62/RT3/W, P63/X, P64/Y and P65/Z pins
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
47
MB90660A Series
2. Recommended Operating Conditions
(VSS = AVSS = 0.0 V)
Parameter
Power supply voltage
Operating temperature
Symbol
Ratings
Min.
Max.
VCC
2.7
5.5
VCC
2.0
5.5
TA
–40
+85
Unit
V
Remarks
During normal operation
Stop operation status is held
°C
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All
the device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
48
MB90660A Series
3. DC Characteristics
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
“H” level
output voltage
Symbol
VOH
VOL1
Pin name
Except P50 to P57
Except P60 to P65
“L” level
output voltage
VOL2
P60 to P65
Conditions
Value
Unit
Min.
Typ.
Max.
VCC = 4.5 V
IOH = –4.0 mA
VCC – 0.5
—
—
V
VCC = 2.7 V
IOH = –1.6 mA
VCC – 0.3
—
—
V
VCC = 4.5 V
IOL = 4.0 mA
—
—
0.4
V
VCC = 2.7 V
IOL = 2.0 mA
—
—
0.4
V
VCC = 4.5 V
IOL = 15.0 mA
—
—
1.0
V
VCC = 2.7 V
IOL = 2.0 mA
—
—
0.4
V
Remarks
VIH
Pins except VIHS,
VIHM
—
0.7 VCC
—
VCC + 0.3
V
VIHS
Hysteresis input pins
—
0.8 VCC
—
VCC + 0.3
V
VIHM
MD pin
—
VCC – 0.3
—
VCC + 0.3
V
VIL
Pins except VILS,
VILM
—
VSS – 0.3
—
0.3 VCC
V
VILS
Hysteresis input pins
—
VSS – 0.3
—
0.2 VCC
V
VILM
MD pin
—
VSS – 0.3
—
VSS + 0.3
V
Input leakage
current
IIL
Except P50 to P57
VCC = 5.5 V
VSS < VI < VCC
–10
—
10
µA
Pull-up
resistor
Pins for which
pull-up option is
selected
When VCC = 5.0 V
25
—
100
kΩ
RPUP
When VCC = 3.0 V
40
—
200
kΩ
Pull-down
resister
Pins for which
pull-down options
selected
When VCC = 5.0 V
25
80
200
kΩ
RPDN
When VCC = 3.0 V
40
160
400
kΩ
Internal 16 MHz
operation
—
50
70
mA
ICCS
Internal 16 MHz
operation
—
25
30
mA During sleep
ICC
Internal 8 MHz
operation
—
10
20
mA
Internal 8 MHz
operation
—
5
10
mA During sleep
TA = 25°C
—
0.1
10
µA
“H” level
input voltage
“L” level
input voltage
ICC
When VCC = 5.0 V
Supply current
When VCC = 3.0 V
ICCS
ICCH
—
Input
capacitance
CIN
Except AVCC,
AVSS, VCC and VSS
—
—
10
—
pF
Open-drain
output leakage
current
Ileak
P50 to P57
—
—
0.1
10
µA
*
*
During normal
operation
During normal
operation
During stop
N channel Tr off
* : Applies to pins P40 to P47, P50 to P57, P60 to P66, DTTI and RST.
49
MB90660A Series
4. AC Characteristics
(1) Clock Timing Values
• Used at VCC = 5.0 V ±10%
(VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin name
Oscillation frequency
FC
X0, X1
Oscillation cycle time
tC
Frequency fluctuation ratio*
(when locked)
ýf
Input clock pulse width
PWH
PWL
Input clock rising and falling
times
tcr
tcf
Internal operating clock
frequency
fCP
Internal operating clock
cycle time
tCP
Conditions
Value
Unit
Min.
Max.
—
3
32
MHz
X0, X1
—
31.25
333
ns
—
—
—
3
%
X0
—
10
—
ns
X0
—
—
5
ns
—
—
1.5
16
MHz
—
—
62.5
666
ns
Remarks
Use duty ratio of 30% to
70% as guideline
* : The frequency fluctuation ratio represents the maximum fluctuation from the central frequency as a percentage
when a multiplier is locked.
+
∆f=
α
f0
+α
× 100 (%)
Central frequency
f0
–α
–
• Used at VCC = 2.7 V (minimum)
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
50
Symbol
Pin name
Conditions
Value
Min.
Max.
Unit
Oscillation frequency
FC
X0, X1
—
3
16
MHz
Oscillation cycle time
tC
X0, X1
—
62.5
333
ns
Input clock pulse width
PWH
PWL
X0
—
20
—
ns
Input clock rising and falling
times
tcr
tcf
X0
—
—
5
ns
Internal operating clock
frequency
fCP
—
—
1.5
8
MHz
Internal operating clock
cycle time
tCP
—
—
125
666
ns
Remarks
Use duty ratio of 30% to
70% as guideline
MB90660A Series
(2) Recommended Resonator Manufacturers
• Sample Application of Piezoelectric Resonator (FAR Family)
X0
X1
R
*1
FAR
*1
*2
C1
C2
*1: Fujitsu Acoustic Resonator
FAR part number
(built-in capacitor type)
FAR-C4CC-02000-L20
FAR-C4SA-04000-M01
FAR-C4CB-04000-M00
Temperature
characteristics of
Loading*2
FAR frequency
capacitors
(TA = –20°C to +60°C)
Frequency
(MHz)
Dumping
resistor
Initial deviation of
FAR frequency
(TA = +25°C)
2.00
510 Ω
±0.5%
±0.5%
—
±0.5%
±0.5%
—
±0.5%
±0.5%
4.00
FAR-C4CB-08000-M02
8.00
—
±0.5%
±0.5%
FAR-C4CB-12000-M02
12.00
—
±0.5%
±0.5%
FAR-C4CB-16000-M02
16.00
—
±0.5%
±0.5%
FAR-C4CB-20000-L14B
19.80
—
±0.5%
±0.5%
FAR-C4CB-24000-L14A
23.76
—
±0.5%
±0.5%
Built-in
Inquiry: FUJITSU LIMITED
51
MB90660A Series
• Sample Application of Ceramic Resonator
X0
X1
R
*
C1
C2
• Mask Products
Resonator
manufacturer*
Kyocera Corporation
52
Resonator
KBR-2.0MS
PBRC2.00A
KBR-4.0MSA
KBR-4.0MKS
PBRC4.00A
PBRC4.00B
KBR-6.0MSA
KBR-6.0MKS
PBRC6.00A
PBRC6.00B
KBR-8.0M
PBRC8.00A
PBRC8.00B
KBR-10.0M
PBRC10.00B
KBR-12.0M
PBRC12.00B
Frequency (MHz)
2.00
4.00
6.00
8.00
8.00
10.00
12.00
C1 (pF)
C2 (pF)
R
150
150
33
Built-in
33
Built-in
33
Built-in
33
Built-in
33
33
Built-in
33
Built-in
33
Built-in
150
150
33
Built-in
33
Built-in
33
Built-in
33
Built-in
33
33
Built-in
33
Built-in
33
Built-in
—
—
680 Ω
680 Ω
680 Ω
680 Ω
—
—
—
—
560 Ω
—
—
330 Ω
680 Ω
330 Ω
680 Ω
(Continued)
MB90660A Series
(Continued)
Resonator
manufacturer*
Murata Mfg. Co., Ltd.
Resonator
CSA2.00MG040
CST2.00MG040
CSA4.00MG040
CST4.00MGW040
CSA6.00MG
CST6.00MGW
CSA8.00MTZ
CST8.00MTW
CSA10.00MTZ
CST10.00MTW
CSA12.00MTZ
CST12.00MTW
CSA16.00MXZ040
CST16.00MXW0C3
CSA20.00MXZ040
CSA24.00MXZ040
CSA32.00MXZ040
Frequency (MHz)
2.00
4.00
6.00
8.00
10.00
12.00
16.00
20.00
24.00
32.00
C1 (pF)
C2 (pF)
R
100
Built-in
100
Built-in
30
Built-in
30
Built-in
30
Built-in
30
Built-in
15
Built-in
10
5
5
100
Built-in
100
Built-in
30
Built-in
30
Built-in
30
Built-in
30
Built-in
15
Built-in
10
5
5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Inquiry: Kyocera Corporation
• AVX Corporation
North American Sales Headquarters: TEL 1-803-448-9411
• AVX Limited
European Sales Headquarters: TEL 44-1252-770000
• AVX/Kyocera H.K. Ltd.
Asian Sales Headquarters: TEL 852-363-3303
Murata Mfg. Co., Ltd.
• Murata Electronics North America, Inc.: TEL 1-404-436-1300
• Murata Europe Management GmbH: TEL 49-911-66870
• Murata Electronics Singapore (Pte.) Ltd.: TEL 65-758-4233
53
MB90660A Series
• Clock Timing
tC
0.8 VCC
0.2 VCC
PWH
PWL
tcf
tcr
• PLL Operation Warranty Range
Power supply VCC (V)
Relationship between clock frequency and supply voltage
5.5
PLL operation
warranty range
Normal operating
range
4.5
3.3
2.7
0 1.5
3
8
16
Internal clock
fCP
(MHz)
Relationship between oscillator frequency and internal operating clock frequency
Multiplied Multiplied
by 4
by 3
Internal clock fCP (MHz)
16
No multiplication
Multiplied
by 2
Multiplied by 1
12
9
8
4
0
34
8
16
Oscillation clock
24
32
FC
(MHz)
Note: Even in the case of evaluation tool, operation is assured down to 2.7 V.
AC specification values are specified for the measured reference voltages given below.
• Input Signal Waveforms
Hysteresis input pin
Output pin
0.8 VCC
2.4 V
0.2 VCC
0.8 V
Pins except hysteresis input and MD input
0.7 VCC
0.3 VCC
54
• Output Signal Waveforms
MB90660A Series
(3) Reset Input Specifications
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Reset input time
Symbol
Pin name
tRSTL
RST
Conditions
—
Value
Min.
Max.
16
—
Unit
Remarks
Machine cycle
tRSTL
RST
0.2 VCC
0.2 VCC
(4) Power-On Reset
(VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Power supply rise time
Power supply cutoff time
Symbol
tR
tOFF
Pin name
Conditions
VCC
—
VCC
Value
Unit
Remarks
Min.
Max.
—
30
ms
*
1
—
ms
Due to repeated
operations
* : VCC should be lower than 0.2 V before power supply rise.
Notes: • The above specifications are the numeric values needed for causing a power-on reset.
• There are built in resisters initialized only by power on reset in the device.
Turn on power supply according to the specification at the point of this initialization.
tR
2.7 V
VCC
0.2 V
An abrupt change in the supply voltage may activate power-on reset.
If the supply voltage must be changed during operation, the voltage change should be smooth without
sudden fluctuations.
5.0 V
VCC
2.0 V
RAM data maintained
A rise time of 50 mV/ms or less
is recommended.
VSS
55
MB90660A Series
(5) UART timing
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin
name
Conditions
Value
Max.
—
8 tCP
—
ns
VCC = 5.0 V ±10%
–80
80
ns
VCC = 3.0 V ±10%
–120
120
ns
VCC = 5.0 V ±10%
100
—
ns
VCC = 3.0 V ±10%
200
—
ns
VCC = 5.0 V ±10%
60
—
ns
VCC = 3.0 V ±10%
120
—
ns
Serial clock cycle time
tSCYC
SCK
SCK ↓ → SOT delay time
tSLOV
SCK
SOT
Valid SIN → SCK ↑
tIVSH
SCK
SIN
SCK ↑ → valid SIN hold
time
tSHIX
SCK
SIN
Serial clock
H pulse width
tSHSL
SCK
—
4 tCP
—
ns
Serial clock
L pulse width
tSLSH
SCK
—
4 tCP
—
ns
SCK ↓ → SOT delay time
tSLOV
SCK
SOT
VCC = 5.0 V ±10%
—
150
ns
VCC = 3.0 V ±10%
—
200
ns
Valid SIN → SCK ↑
tIVSH
SCK
SIN
VCC = 5.0 V ±10%
60
—
ns
VCC = 3.0 V ±10%
120
—
ns
SCK ↑ → valid SIN hold
time
tSHIX
SCK
SIN
VCC = 5.0 V ±10%
60
—
ns
VCC = 3.0 V ±10%
120
—
ns
Notes: • These are AC specification during CLK synchronous mode.
• CL is the load capacity value assigned to the pin during testing.
• tCP is the machine cycle time (unit: ns).
56
Unit
Min.
Remarks
CL = 80 pF + 1 TTL
for internal clock
operation output
pin
CL = 80 pF + 1 TTL
for external clock
operation output
pin
MB90660A Series
• Internal Shift Clock Mode
tSCYC
SCK
2.4 V
0.8 V
0.8 V
tSLOV
2.4 V
SOT
0.8 V
tIVSH
SIN
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
• External Shift Clock Mode
tSLSH
SCK
tSHSL
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tSLOV
SOT
2.4 V
0.8 V
tIVSH
SIN
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
57
MB90660A Series
(6) Timer input timing
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
tTIWH
tTIWL
Input pulse width
Pin name
Conditions
TIM0 to TIM3
—
0.7 VCC
Value
Min.
Max.
4 tCP
—
Unit
Remarks
ns
0.7 VCC
0.3 VCC
0.3 VCC
tTIWH
tTIWL
(7) Trigger input timing
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Input pulse width
Pin name
Symbol
ATG, DTTI, TRG,
INT4 to INT7
tTRGH
tTRGL
Value
Conditions
Unit
Min.
Max.
5 tCP
—
ns
5 tCP
—
ns
—
ATG, DTTI, TRG,
INT0 to INT3
• INT4 to INT7
0.7 VCC
0.7 VCC
0.3 VCC
0.3 VCC
tTRGH
tTRGL
• INT0 to INT3
0.7 VCC
0.8 VCC
0.2 VCC
tTRGH
58
0.2 VCC
tTRGL
Remarks
MB90660A Series
5. Electrical Characteristics of A/D Converter
(AVCC = VCC = +2.7 V to +5.5 V, AVSS = VSS = 0.0 V, 2.7 V ≤ AVR, TA = –40°C to +85°C)
Parameter
Symbol
Pin name
Resolution
—
Total error
Value
Unit
Min.
Typ.
Max.
—
—
10
10
bit
—
—
—
—
±3.0
LSB
Linearity error
—
—
—
—
±2.0
LSB
Differential linearity error
—
—
—
—
±1.5
LSB
Zero transition voltage
VOT
AN0 to AN7
–1.5
+0.5
+2.5
LSB
Full-scale transition voltage
VFST
AN0 to AN7
AVR – 4.5
Conversion time
—
—
AVR – 1.5
AVR + 0.5
LSB
*1
—
—
µs
*2
12.25
—
—
µs
6.125
Analog port input voltage
IAIN
AN0 to AN7
—
0.1
10
µA
Analog input voltage
VAIN
AN0 to AN7
0
—
AVR
V
AVR
3.5
—
AVCC
V
AVCC
—
3
—
mA
*3
Reference voltage
—
IA
Supply current
Reference voltage supply current
IAH
AVCC
—
—
5
µA
IR
AVR
—
200
—
µA
*3
IRH
Variation between channels
—
AVR
—
—
5
µA
AN0 to AN7
—
—
4
LSB
*1: VCC = 5.0 V ±10% at 16 MHz machine clock
*2: VCC = 3.0 V ±10% at 8 MHz machine clock
*3: Current when CPU is stopped and A/D converter is not operating (when VCC = AVCC = AVR = 5.0 V)
Notes: • The relative error becomes larger as the reference voltage (AVR) becomes smaller.
• Be sure to use the A/D converter only when output impedance of the external analog input circuit meets
the following conditions.
External circuit output impedance < approx. 7 kΩ
• If the output impedance of the external circuit is too high, there may not be enough time to sample the
analog voltage. (Sampling time = 3.75 µs @4 MHz (equivalent to internal 16 MHz when multiplying by 4))
• For an external capacitor to be provided outside the chip, its capacity should desirably be thousands times
larger than of the capacity in the chip taking in consideration the influence of the capacity destribution of
the external and internal capacitors.
• Figure Model of Analog Input Circuit
Sample and hold circuit
C0
Analog input
Comparator
RON1
RON2
RON3
RON1 = Approx. 1.5 kΩ (VCC = 5.0 V)
RON2 = Approx. 0.5 kΩ (VCC = 5.0 V)
RON3 = Approx. 0.5 kΩ (VCC = 5.0 V)
RON4 = Approx. 0.5 kΩ (VCC = 5.0 V)
C0 = Approx. 60 pF
C1 = Approx. 4 pF
RON4
C1
Note: Use the values shown here as guidelines.
59
MB90660A Series
6. Definitions of A/D Converter Terms
Resolution
: Analog transition observed with an A/D converter.
Analog voltage can be divided in 1024 = 210 parts at 10-bit resolution.
Total error
: This refers to the difference between actual and logical values. This error is
caused by offset errors, gain errors, non-linearity errors and noise.
Linearity error
: Deviation of the line drawn between the zero transition point (00 0000 0000 ↔
00 0000 0001) and the full-scale transition point (11 1111 1110 ↔ 11 1111
1111) for the device from actual conversion characteristics.
Differential linearity error
: Deviation from ideal input voltage required to shift output code by one LSB.
Digital output
11 1111 1111
11 1111 1110
•
•
•
•
•
•
•
•
•
•
•
00 0000 0010
00 0000 0001
00 0000 0000
(1LSB × N + VOT)
Linearity error
Analog input
VOT
1LSB =
VNT V(N + 1)T
VFST – VOT
1022
Linearity error =
VNT – (1LSB × N + VOT )
1LSB
Differential linearity error =
60
V(N + 1) T – VNT
1LSB
(LSB)
– 1 (LSB)
VFST
MB90660A Series
■ EXAMPLES CHARACTERISTICS
(1) “H” Level Output Voltage
(2) “L” Level Output Voltage
VOH – IOH
VOH (V)
1.0
0.9 TA = +25°C
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
–2
–4
–6
VCC = 3.0 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
–8
IOH (mA)
(3) “L” Level Output Voltage (P60 to P65)
VOL – IOL
VOL (V)
1.0
0.9 TA = +25°C
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
5
10
15
VOL – IOL
VOL (V)
1.0
0.9 TA = +25°C
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
2
VCC = 2.7 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
4
6
8
IOL (mA)
(4) “H” Level Input Voltage/“L” Level Input Voltage
VIN (V)
5.0
VCC = 2.7 V
4.5
VCC = 3.0 V
4.0
VIN – VCC (CMOS input)
TA = +25°C
3.5
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
3.0
2.5
2.0
1.5
1.0
0.5
20
25
IOL (mA)
0
2
3
4
5
6
VCC (V)
(5) “H” Level Input Voltage/“L” Level Input Voltage
V IN (V)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
2
VIN – VCC (Hysteresis input)
TA = +25°C
VIHS
VILS
VIHS: Threshold when input voltage in hysteresis
characteristics is set to “H” level
3
4
5
6
VCC (V)
VILS: Threshold when input voltage in hysteresis
characteristics is set to “L” level
(Continued)
61
MB90660A Series
(6) Power Supply Current (fcp = Internal frequency)
ICC – VCC
ICC (mA)
70
ICCS – VCC
ICCS (mA)
25
TA = +25°C
TA = +25°C
fCP = 16 MHz
60
fCP = 12.5 MHz
50
20
fCP = 16 MHz
15
40
fCP = 12.5 MHz
fCP = 8 MHz
30
10
fCP = 8 MHz
5
fCP = 4 MHz
fCP = 4 MHz
20
10
0
0
3.0
4.0
5.0
6.0
VCC (V)
3.0
IA – AVCC
I A (mA)
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5.0
TA = +25°C
fCP = 16 MHz
0.20
0.10
0
3.0
4.0
5.0
6.0
AV CC (V)
3.0
4.0
(7) Pull-up Resistor
R – VCC
R (kΩ)
1000
TA = +25°C
100
10
2.5
62
6.0
VCC (V)
IR – AVR
I R (mA)
0.30
TA = +25°C
fCP = 16 MHz
4.0
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VCC (V)
5.0
6.0
AVR (V)
MB90660A Series
■ INSTRUCTIONS (340 INSTRUCTIONS)
Table 1
Explanation of Items in Tables of Instructions
Item
Mnemonic
Meaning
Upper-case letters and symbols: Represented as they appear in assembler.
Lower-case letters:
Replaced when described in assembler.
Numbers after lower-case letters: Indicate the bit width within the instruction.
#
Indicates the number of bytes.
~
Indicates the number of cycles.
m : When branching
n : When not branching
See Table 4 for details about meanings of other letters in items.
RG
B
Operation
Indicates the number of accesses to the register during execution of the instruction.
It is used calculate a correction value for intermittent operation of CPU.
Indicates the correction value for calculating the number of actual cycles during execution of the
instruction. (Table 5)
The number of actual cycles during execution of the instruction is the correction value summed
with the value in the “~” column.
Indicates the operation of instruction.
LH
Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator.
Z : Transfers “0”.
X : Extends with a sign before transferring.
– : Transfers nothing.
AH
Indicates special operations involving the upper 16 bits in the accumulator.
* : Transfers from AL to AH.
– : No transfer.
Z : Transfers 00H to AH.
X : Transfers 00H or FFH to AH by signing and extending AL.
I
S
T
N
Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit),
N (negative), Z (zero), V (overflow), and C (carry).
* : Changes due to execution of instruction.
– : No change.
S : Set by execution of instruction.
R : Reset by execution of instruction.
Z
V
C
RMW
Indicates whether the instruction is a read-modify-write instruction. (a single instruction that
reads data from memory, etc., processes the data, and then writes the result to memory.)
* : Instruction is a read-modify-write instruction.
– : Instruction is not a read-modify-write instruction.
Note: A read-modify-write instruction cannot be used on addresses that have different
meanings depending on whether they are read or written.
63
MB90660A Series
Table 2
Explanation of Symbols in Tables of Instructions
Symbol
A
Meaning
32-bit accumulator
The bit length varies according to the instruction.
Byte : Lower 8 bits of AL
Word : 16 bits of AL
Long : 32 bits of AL:AH
AH
AL
Upper 16 bits of A
Lower 16 bits of A
SP
Stack pointer (USP or SSP)
PC
Program counter
PCB
Program bank register
DTB
Data bank register
ADB
Additional data bank register
SSB
System stack bank register
USB
User stack bank register
SPB
Current stack bank register (SSB or USB)
DPR
Direct page register
brg1
DTB, ADB, SSB, USB, DPR, PCB, SPB
brg2
DTB, ADB, SSB, USB, DPR, SPB
Ri
R0, R1, R2, R3, R4, R5, R6, R7
RWi
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj
RW0, RW1, RW2, RW3
RLi
RL0, RL1, RL2, RL3
dir
Compact direct addressing
addr16
addr24
ad24 0 to 15
ad24 16 to 23
Direct addressing
Physical direct addressing
Bit 0 to bit 15 of addr24
Bit 16 to bit 23 of addr24
io
imm4
imm8
imm16
imm32
ext (imm8)
disp8
disp16
bp
I/O area (000000H to 0000FFH)
4-bit immediate data
8-bit immediate data
16-bit immediate data
32-bit immediate data
16-bit data signed and extended from 8-bit immediate data
8-bit displacement
16-bit displacement
Bit offset
vct4
vct8
Vector number (0 to 15)
Vector number (0 to 255)
( )b
Bit address
(Continued)
64
MB90660A Series
(Continued)
Symbol
Meaning
rel
Branch specification relative to PC
ear
eam
Effective addressing (codes 00 to 07)
Effective addressing (codes 08 to 1F)
rlst
Register list
Table 3
Code
00
01
02
03
04
05
06
07
Notation
R0
R1
R2
R3
R4
R5
R6
R7
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
Effective Address Fields
Address format
RL0
(RL0)
RL1
(RL1)
RL2
(RL2)
RL3
(RL3)
Number of bytes in address
extension *
Register direct
“ea” corresponds to byte, word, and
long-word types, starting from the
left
08
09
0A
0B
@RW0
@RW1
@RW2
@RW3
Register indirect
0C
0D
0E
0F
@RW0 +
@RW1 +
@RW2 +
@RW3 +
Register indirect with post-increment
10
11
12
13
14
15
16
17
@RW0 + disp8
@RW1 + disp8
@RW2 + disp8
@RW3 + disp8
@RW4 + disp8
@RW5 + disp8
@RW6 + disp8
@RW7 + disp8
Register indirect with 8-bit
displacement
18
19
1A
1B
@RW0 + disp16
@RW1 + disp16
@RW2 + disp16
@RW3 + disp16
Register indirect with 16-bit
displacement
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct address
—
0
0
1
2
0
0
2
2
Note: The number of bytes in the address extension is indicated by the “+” symbol in the “#” (number of bytes)
column in the tables of instructions.
65
MB90660A Series
Table 4
Number of Execution Cycles for Each Type of Addressing
(a)
Code
Operand
Number of execution cycles
for each type of addressing
Number of register
accesses for each type of
addressing
Listed in tables of instructions
Listed in tables of instructions
00 to 07
Ri
RWi
RLi
08 to 0B
@RWj
2
1
0C to 0F
@RWj +
4
2
10 to 17
@RWi + disp8
2
1
18 to 1B
@RWj + disp16
2
1
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
4
4
2
1
2
2
0
0
Note: “(a)” is used in the “~” (number of states) column and column B (correction value) in the tables of instructions.
Table 5
Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles
(b) byte
Operand
(c) word
(d) long
Number Number Number Number Number Number
of cycles of access of cycles of access of cycles of access
Internal register
+0
1
+0
1
+0
2
Internal memory even address
Internal memory odd address
+0
+0
1
1
+0
+2
1
2
+0
+4
2
4
Even address on external data bus (16 bits)
Odd address on external data bus (16 bits)
+1
+1
1
1
+1
+4
1
2
+2
+8
2
4
External data bus (8 bits)
+1
1
+4
2
+8
4
Notes: • “(b)”, “(c)”, and “(d)” are used in the “~” (number of states) column and column B (correction value)
in the tables of instructions.
• When the external data bus is used, it is necessary to add in the number of wait cycles used for ready
input and automatic ready.
Table 6
Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles
Instruction
Byte boundary
Word boundary
Internal memory
—
+2
External data bus (16 bits)
—
+3
External data bus (8 bits)
+3
—
Notes: • When the external data bus is used, it is necessary to add in the number of wait cycles used for ready
input and automatic ready.
• Because instruction execution is not slowed down by all program fetches in actuality, these correction
values should be used for “worst case” calculations.
66
MB90660A Series
Table 7
Mnemonic
Transfer Instructions (Byte) [41 Instructions]
#
~
RG
B
Operation
LH AH
I
S T N Z V C
RMW
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVN
A, dir
A, addr16
A, Ri
A, ear
A, eam
A, io
A, #imm8
A, @A
A, @RLi+disp8
A, #imm4
2
3
1
2
2+
2
2
2
3
1
3
4
2
2
3+ (a)
3
2
3
10
1
0
0
1
1
0
0
0
0
2
0
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
0
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RLi)+disp8)
byte (A) ← imm4
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
*
*
*
*
*
*
*
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
R
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
A, dir
A, addr16
A, Ri
A, ear
A, eam
A, io
A, #imm8
A, @A
A,@RWi+disp8
A, @RLi+disp8
2
3
2
2
2+
2
2
2
2
3
3
4
2
2
3+ (a)
3
2
3
5
10
0
0
1
1
0
0
0
0
1
2
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
(b)
byte (A) ←
byte (A) ←
byte (A) ←
byte (A) ←
byte (A) ←
byte (A) ←
byte (A) ←
byte (A) ←
byte (A) ←
byte (A) ←
(dir)
(addr16)
(Ri)
(ear)
(eam)
(io)
imm8
((A))
((RWi)+disp8)
((RLi)+disp8)
X
X
X
X
X
X
X
X
X
X
*
*
*
*
*
*
*
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
/MOV
dir, A
addr16, A
Ri, A
ear, A
eam, A
io, A
@RLi+disp8, A
Ri, ear
Ri, eam
ear, Ri
eam, Ri
Ri, #imm8
io, #imm8
dir, #imm8
ear, #imm8
eam, #imm8
@AL, AH
@A, T
2
3
1
2
2+
2
3
2
2+
2
2+
2
3
3
3
3+
2
3
4
2
2
3+ (a)
3
10
3
4+ (a)
4
5+ (a)
2
5
5
2
4+ (a)
3
0
0
1
1
0
0
2
2
1
2
1
1
0
0
1
0
0
(b)
(b)
0
0
(b)
(b)
(b)
0
(b)
0
(b)
0
(b)
(b)
0
(b)
(b)
byte (dir) ← (A)
byte (addr16) ← (A)
byte (Ri) ← (A)
byte (ear) ← (A)
byte (eam) ← (A)
byte (io) ← (A)
byte ((RLi) +disp8) ← (A)
byte (Ri) ← (ear)
byte (Ri) ← (eam)
byte (ear) ← (Ri)
byte (eam) ← (Ri)
byte (Ri) ← imm8
byte (io) ← imm8
byte (dir) ← imm8
byte (ear) ← imm8
byte (eam) ← imm8
byte ((A)) ← (AH)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
*
–
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
XCH
XCH
XCH
XCH
A, ear
A, eam
Ri, ear
Ri, eam
2
2+
2
2+
4
5+ (a)
7
9+ (a)
2
0
4
2
0
2× (b)
0
2× (b)
byte (A) ↔ (ear)
byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
byte (Ri) ↔ (eam)
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
67
MB90660A Series
Table 8
Mnemonic
Transfer Instructions (Word/Long Word) [38 Instructions]
#
~
RG
B
Operation
LH AH
I
S T N Z V C
RMW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
A, dir
A, addr16
A, SP
A, RWi
A, ear
A, eam
A, io
A, @A
A, #imm16
A, @RWi+disp8
A, @RLi+disp8
2
3
1
1
2
2+
2
2
3
2
3
3
4
1
2
2
3+ (a)
3
3
2
5
10
0
0
0
1
1
0
0
0
0
1
2
(c)
(c)
0
0
0
(c)
(c)
(c)
0
(c)
(c)
word (A) ← (dir)
word (A) ← (addr16)
word (A) ← (SP)
word (A) ← (RWi)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← (io)
word (A) ← ((A))
word (A) ← imm16
word (A) ← ((RWi) +disp8)
word (A) ← ((RLi) +disp8)
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
–
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
dir, A
addr16, A
SP, A
RWi, A
ear, A
eam, A
io, A
@RWi+disp8, A
@RLi+disp8, A
RWi, ear
RWi, eam
ear, RWi
eam, RWi
RWi, #imm16
io, #imm16
ear, #imm16
eam, #imm16
2
3
1
1
2
2+
2
2
3
2
2+
2
2+
3
4
4
4+
3
4
1
2
2
3+ (a)
3
5
10
3
4+ (a)
4
5+ (a)
2
5
2
4+ (a)
0
0
0
1
1
0
0
1
2
2
1
2
1
1
0
1
0
(c)
(c)
0
0
0
(c)
(c)
(c)
(c)
(0)
(c)
0
(c)
0
(c)
0
(c)
word (dir) ← (A)
word (addr16) ← (A)
word (SP) ← (A)
word (RWi) ← (A)
word (ear) ← (A)
word (eam) ← (A)
word (io) ← (A)
word ((RWi) +disp8) ← (A)
word ((RLi) +disp8) ← (A)
word (RWi) ← (ear)
word (RWi) ← (eam)
word (ear) ← (RWi)
word (eam) ← (RWi)
word (RWi) ← imm16
word (io) ← imm16
word (ear) ← imm16
word (eam) ← imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2
3
0
(c)
word ((A)) ← (AH)
–
–
–
–
–
*
*
–
–
–
word (A) ↔ (ear)
word (A) ↔ (eam)
word (RWi) ↔ (ear)
word (RWi) ↔ (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVW AL, AH
/MOVW @A, T
XCHW
XCHW
XCHW
XCHW
A, ear
A, eam
RWi, ear
RWi, eam
2
2+
2
2+
4
5+ (a)
7
9+ (a)
2
0
4
2
0
2× (c)
0
2× (c)
MOVL
MOVL
MOVL
A, ear
A, eam
A, #imm32
2
2+
5
4
5+ (a)
3
2
0
0
0
(d)
0
long (A) ← (ear)
long (A) ← (eam)
long (A) ← imm32
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
MOVL
MOVL
ear, A
eam, A
2
2+
4
5+ (a)
2
0
0
(d)
long (ear) ← (A)
long (eam) ← (A)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
68
MB90660A Series
Table 9
Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions]
#
~
RG
B
Operation
ADD
A,#imm8
ADD
A, dir
ADD
A, ear
ADD
A, eam
ADD
ear, A
ADD
eam, A
ADDC
A
ADDC
A, ear
ADDC
A, eam
ADDDC A
SUB
A, #imm8
SUB
A, dir
SUB
A, ear
SUB
A, eam
SUB
ear, A
SUB
eam, A
SUBC
A
SUBC
A, ear
SUBC
A, eam
SUBDC A
2
2
2
2+
2
2+
1
2
2+
1
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4+ (a)
3
5+ (a)
2
3
4+ (a)
3
2
5
3
4+ (a)
3
5+ (a)
2
3
4+ (a)
3
0
0
1
0
2
0
0
1
0
0
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2× (b)
0
0
(b)
0
0
(b)
0
(b)
0
2× (b)
0
0
(b)
0
byte (A) ← (A) +imm8
byte (A) ← (A) +(dir)
byte (A) ← (A) +(ear)
byte (A) ← (A) +(eam)
byte (ear) ← (ear) + (A)
byte (eam) ← (eam) + (A)
byte (A) ← (AH) + (AL) + (C)
byte (A) ← (A) + (ear) + (C)
byte (A) ← (A) + (eam) + (C)
byte (A) ← (AH) + (AL) + (C) (decimal)
byte (A) ← (A) –imm8
byte (A) ← (A) – (dir)
byte (A) ← (A) – (ear)
byte (A) ← (A) – (eam)
byte (ear) ← (ear) – (A)
byte (eam) ← (eam) – (A)
byte (A) ← (AH) – (AL) – (C)
byte (A) ← (A) – (ear) – (C)
byte (A) ← (A) – (eam) – (C)
byte (A) ← (AH) – (AL) – (C) (decimal)
Z
Z
Z
Z
–
Z
Z
Z
Z
Z
Z
Z
Z
Z
–
–
Z
Z
Z
Z
ADDW
ADDW
ADDW
ADDW
ADDW
ADDW
ADDCW
ADDCW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBCW
SUBCW
A
A, ear
A, eam
A, #imm16
ear, A
eam, A
A, ear
A, eam
A
A, ear
A, eam
A, #imm16
ear, A
eam, A
A, ear
A, eam
1
2
2+
3
2
2+
2
2+
1
2
2+
3
2
2+
2
2+
2
3
4+ (a)
2
3
5+ (a)
3
4+ (a)
2
3
4+ (a)
2
3
5+ (a)
3
4+ (a)
0
1
0
0
2
0
1
0
0
1
0
0
2
0
1
0
0
0
(c)
0
0
2× (c)
0
(c)
0
0
(c)
0
0
2× (c)
0
(c)
word (A) ← (AH) + (AL)
word (A) ← (A) +(ear)
word (A) ← (A) +(eam)
word (A) ← (A) +imm16
word (ear) ← (ear) + (A)
word (eam) ← (eam) + (A)
word (A) ← (A) + (ear) + (C)
word (A) ← (A) + (eam) + (C)
word (A) ← (AH) – (AL)
word (A) ← (A) – (ear)
word (A) ← (A) – (eam)
word (A) ← (A) –imm16
word (ear) ← (ear) – (A)
word (eam) ← (eam) – (A)
word (A) ← (A) – (ear) – (C)
word (A) ← (A) – (eam) – (C)
A, ear
A, eam
A, #imm32
A, ear
A, eam
A, #imm32
2
2+
5
2
2+
5
6
7+ (a)
4
6
7+ (a)
4
2
0
0
2
0
0
0
(d)
0
0
(d)
0
long (A) ← (A) + (ear)
long (A) ← (A) + (eam)
long (A) ← (A) +imm32
long (A) ← (A) – (ear)
long (A) ← (A) – (eam)
long (A) ← (A) –imm32
Mnemonic
ADDL
ADDL
ADDL
SUBL
SUBL
SUBL
I
S T N Z V C
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
–
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
LH AH
RMW
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
69
MB90660A Series
Table 10
Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions]
Mnemonic
#
~
RG
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
INC
INC
ear
eam
byte (ear) ← (ear) +1
0
2
2
2
2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
DEC
DEC
ear
eam
byte (ear) ← (ear) –1
0
2
3
2
2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
INCW
INCW
ear
eam
2
3
2
0
word (ear) ← (ear) +1
2+ 5+ (a) 0 2× (c) word (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
DECW ear
DECW eam
2
3
2
0
word (ear) ← (ear) –1
2+ 5+ (a) 0 2× (c) word (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
INCL
INCL
ear
eam
long (ear) ← (ear) +1
0
4
7
2
2+ 9+ (a) 0 2× (d) long (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
DECL
DECL
ear
eam
long (ear) ← (ear) –1
0
4
7
2
2+ 9+ (a) 0 2× (d) long (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 11
Mnemonic
#
Compare Instructions (Byte/Word/Long Word) [11 Instructions]
~
RG
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
CMP
CMP
CMP
CMP
A
A, ear
A, eam
A, #imm8
1
1
2
2
2+ 3+ (a)
2
2
0
1
0
0
0
0
(b)
0
byte (AH) – (AL)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPW
CMPW
CMPW
CMPW
A
A, ear
A, eam
A, #imm16
1
1
2
2
2+ 3+ (a)
2
3
0
1
0
0
0
0
(c)
0
word (AH) – (AL)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPL
CMPL
CMPL
A, ear
A, eam
A, #imm32
2
6
2
2+ 7+ (a) 0
5
3
0
0
(d)
0
word (A) ← (ear)
word (A) ← (eam)
word (A) ← imm32
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
70
MB90660A Series
Table 12
Mnemonic
Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions]
#
~
RG
B
Operation
*
1
0
0
*
2
1
0
*
3
0
6
*
*
4
1
0
5
0
7
*
word (AH) /byte (AL)
Quotient → byte (AL) Remainder → byte (AH)
word (A)/byte (ear)
Quotient → byte (A) Remainder → byte (ear)
word (A)/byte (eam)
Quotient → byte (A) Remainder → byte (eam)
long (A)/word (ear)
Quotient → word (A) Remainder → word (ear)
long (A)/word (eam)
Quotient → word (A) Remainder → word
(eam)
0
0 byte (AH) *byte (AL) → word (A)
(b) byte (A) *byte (ear) → word (A)
byte (A) *byte (eam) → word (A)
0
0 word (AH) *word (AL) → long (A)
(c) word (A) *word (ear) → long (A)
word (A) *word (eam) → long (A)
DIVU
A
1
DIVU
A, ear
2
DIVU
A, eam
2+
DIVUW
A, ear
2
DIVUW
A, eam
2+
*
MULU
MULU
MULU
A
A, ear
A, eam
1
2
2+
*8
*9
*10
0
1
0
MULUW
MULUW
MULUW
A
A, ear
A, eam
1
2
2+
*11
*12
*13
0
1
0
*1:
*2:
*3:
*4:
*5:
*6:
*7:
*8:
*9:
*10:
*11:
*12:
*13:
LH AH
I
S
T
N
Z
V
C
RMW
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3 when the result is zero, 7 when an overflow occurs, and 15 normally.
4 when the result is zero, 8 when an overflow occurs, and 16 normally.
6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally.
4 when the result is zero, 7 when an overflow occurs, and 22 normally.
6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally.
(b) when the result is zero or when an overflow occurs, and 2 × (b) normally.
(c) when the result is zero or when an overflow occurs, and 2 × (c) normally.
3 when byte (AH) is zero, and 7 when byte (AH) is not zero.
4 when byte (ear) is zero, and 8 when byte (ear) is not zero.
5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0.
3 when word (AH) is zero, and 11 when word (AH) is not zero.
4 when word (ear) is zero, and 12 when word (ear) is not zero.
5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
71
MB90660A Series
Table 13
Mnemonic
#
~
Logical 1 Instructions (Byte/Word) [39 Instructions]
RG
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
AND
AND
AND
AND
AND
A, #imm8
A, ear
A, eam
ear, A
eam, A
2
2
3
2
2+ 4+ (a)
3
2
2+ 5+ (a)
0
0
0
1
(b)
0
0
2
0 2× (b)
byte (A) ← (A) and imm8
byte (A) ← (A) and (ear)
byte (A) ← (A) and (eam)
byte (ear) ← (ear) and (A)
byte (eam) ← (eam) and (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
OR
OR
OR
OR
OR
A, #imm8
A, ear
A, eam
ear, A
eam, A
2
2
3
2
2+ 4+ (a)
3
2
2+ 5+ (a)
0
0
0
1
(b)
0
0
2
0 2× (b)
byte (A) ← (A) or imm8
byte (A) ← (A) or (ear)
byte (A) ← (A) or (eam)
byte (ear) ← (ear) or (A)
byte (eam) ← (eam) or (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
XOR
XOR
XOR
XOR
XOR
A, #imm8
A, ear
A, eam
ear, A
eam, A
2
2
3
2
2+ 4+ (a)
3
2
2+ 5+ (a)
0
0
0
1
(b)
0
0
2
0 2× (b)
byte (A) ← (A) xor imm8
byte (A) ← (A) xor (ear)
byte (A) ← (A) xor (eam)
byte (ear) ← (ear) xor (A)
byte (eam) ← (eam) xor (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
NOT
NOT
NOT
A
ear
eam
byte (A) ← not (A)
0
0
2
1
byte (ear) ← not (ear)
0
2
3
2
2+ 5+ (a) 0 2× (b) byte (eam) ← not (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
R
R
R
–
–
–
–
–
*
ANDW
ANDW
ANDW
ANDW
ANDW
ANDW
2
1
A
2
A, #imm16 3
3
2
A, ear
2+ 4+ (a)
A, eam
3
2
ear, A
2+ 5+ (a)
eam, A
0
0
0
0
0
1
(c)
0
0
2
0 2× (c)
word (A) ← (AH) and (A)
word (A) ← (A) and imm16
word (A) ← (A) and (ear)
word (A) ← (A) and (eam)
word (ear) ← (ear) and (A)
word (eam) ← (eam) and (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
ORW
ORW
ORW
ORW
ORW
ORW
2
1
A
2
A, #imm16 3
3
2
A, ear
2+ 4+ (a)
A, eam
3
2
ear, A
2+ 5+ (a)
eam, A
0
0
0
0
0
1
(c)
0
0
2
0 2× (c)
word (A) ← (AH) or (A)
word (A) ← (A) or imm16
word (A) ← (A) or (ear)
word (A) ← (A) or (eam)
word (ear) ← (ear) or (A)
word (eam) ← (eam) or (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
XORW
XORW
XORW
XORW
XORW
XORW
2
1
A
2
A, #imm16 3
3
2
A, ear
2+ 4+ (a)
A, eam
3
2
ear, A
2+ 5+ (a)
eam, A
0
0
0
0
0
1
(c)
0
0
2
0 2× (c)
word (A) ← (AH) xor (A)
word (A) ← (A) xor imm16
word (A) ← (A) xor (ear)
word (A) ← (A) xor (eam)
word (ear) ← (ear) xor (A)
word (eam) ← (eam) xor (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
R
R
R
–
–
–
–
–
*
NOTW A
NOTW ear
NOTW eam
word (A) ← not (A)
0
0
2
1
word (ear) ← not (ear)
0
2
3
2
2+ 5+ (a) 0 2× (c) word (eam) ← not (eam)
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
72
MB90660A Series
Table 14
Mnemonic
#
~
Logical 2 Instructions (Long Word) [6 Instructions]
RG
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
ANDL A, ear
ANDL A, eam
2
6
2
2+ 7+ (a) 0
0
(d)
long (A) ← (A) and (ear)
long (A) ← (A) and (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
ORL
ORL
A, ear
A, eam
2
6
2
2+ 7+ (a) 0
0
(d)
long (A) ← (A) or (ear)
long (A) ← (A) or (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
XORL A, ea
XORL A, eam
2
6
2
2+ 7+ (a) 0
0
(d)
long (A) ← (A) xor (ear)
long (A) ← (A) xor (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
Table 15
Mnemonic
Sign Inversion Instructions (Byte/Word) [6 Instructions]
#
~
RG
B
Operation
2
0
0
byte (A) ← 0 – (A)
LH AH
NEG
A
1
NEG
NEG
ear
eam
byte (ear) ← 0 – (ear)
0
2
3
2
2+ 5+ (a) 0 2× (b) byte (eam) ← 0 – (eam)
2
0
0
word (A) ← 0 – (A)
NEGW A
1
NEGW ear
NEGW eam
word (ear) ← 0 – (ear)
0
2
3
2
2+ 5+ (a) 0 2× (c) word (eam) ← 0 – (eam)
Table 16
I
S
T
N
Z
V
C
RMW
X
–
–
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
*
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
*
Normalize Instruction (Long Word) [1 Instruction]
Mnemonic
#
~
RG
B
NRML A, R0
2
*1
1
0
Operation
long (A) ← Shift until first digit is
byte (R0) ← Current shift count
LH AH
“1” –
–
I
S
T
N
Z
V
C
RMW
–
–
–
–
*
–
–
–
*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count).
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
73
MB90660A Series
Table 17
Mnemonic
RORC A
ROLC A
RORC
RORC
ROLC
ROLC
ear
eam
ear
eam
ASR
LSR
LSL
A, R0
A, R0
A, R0
ASRW A
LSRW A/SHRW
A
LSLW A/SHLW A
ASRW A, R0
LSRW A, R0
LSLW A, R0
ASRL A, R0
LSRL A, R0
LSLL A, R0
Shift Instructions (Byte/Word/Long Word) [18 Instructions]
#
~
RG
B
2
2
2
2
0
0
0
0
2
0
2
0
0
2× (b)
0
2× (b)
2
3
2+ 5+ (a)
2
3
2+ 5+ (a)
Operation
LH AH
I
S T N Z V C
RMW
byte (A) ← Right rotation with carry
byte (A) ← Left rotation with carry
–
–
–
–
–
–
–
–
–
–
*
*
*
*
–
–
*
*
–
–
byte (ear) ← Right rotation with carry
byte (eam) ← Right rotation with carry
byte (ear) ← Left rotation with carry
byte (eam) ← Left rotation with carry
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
*
*
*
*
–
*
–
*
2
2
2
*1
*1
*1
1
1
1
0
0
0
byte (A) ← Arithmetic right barrel shift (A, R0)
byte (A) ← Logical right barrel shift (A, R0)
byte (A) ← Logical left barrel shift (A, R0)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
1
1
1
2
2
2
0
0
0
0
0
0
word (A) ← Arithmetic right shift (A, 1 bit)
word (A) ← Logical right shift (A, 1 bit)
word (A) ← Logical left shift (A, 1 bit)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
R
*
*
*
*
–
–
–
*
*
*
–
–
–
2
2
2
*1
*1
*1
1
1
1
0
0
0
word (A) ← Arithmetic right barrel shift (A, R0)
word (A) ← Logical right barrel shift (A, R0)
word (A) ← Logical left barrel shift (A, R0)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
2
2
2
*2
*2
*2
1
1
1
0
0
0
long (A) ← Arithmetic right shift (A, R0)
long (A) ← Logical right barrel shift (A, R0)
long (A) ← Logical left barrel shift (A, R0)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
*1: 6 when R0 is 0, 5 + (R0) in all other cases.
*2: 6 when R0 is 0, 6 + (R0) in all other cases.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
74
MB90660A Series
Table 18
Mnemonic
BZ/BEQ
BNZ/BNE
BC/BLO
BNC/BHS
BN
rel
BP
rel
BV
rel
BNV
rel
BT
rel
BNT
rel
BLT
rel
BGE
rel
BLE
rel
BGT
rel
BLS
rel
BHI
rel
BRA
rel
rel
rel
rel
rel
#
~
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
JMP
JMP
JMP
JMP
JMPP
JMPP
JMPP
@A
addr16
@ear
@eam
@ear *3
@eam *3
addr24
1
3
2
2+
2
2+
4
CALL
CALL
CALL
CALLV
CALLP
@ear *4
@eam *4
addr16 *5
#vct4 *5
@ear *6
2
2+
3
1
2
CALLP
@eam *6
2+
CALLP
addr24 *7
4
*1:
*2:
*3:
*4:
*5:
*6:
*7:
*
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
2
3
3
4+ (a)
5
6+ (a)
4
6
7+ (a)
6
7
10
11+ (a)
10
RG
B
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
2
0
0
0
0
0
(c)
0
(d)
0
1
0
0
0
2
(c)
2× (c)
(c)
2× (c)
2× (c)
0
*2
0
2× (c)
Branch 1 Instructions [31 Instructions]
Operation
LH AH
I
S T N Z V C
RMW
Branch when (Z) = 1
Branch when (Z) = 0
Branch when (C) = 1
Branch when (C) = 0
Branch when (N) = 1
Branch when (N) = 0
Branch when (V) = 1
Branch when (V) = 0
Branch when (T) = 1
Branch when (T) = 0
Branch when (V) xor (N) = 1
Branch when (V) xor (N) = 0
Branch when ((V) xor (N)) or (Z) = 1
Branch when ((V) xor (N)) or (Z) = 0
Branch when (C) or (Z) = 1
Branch when (C) or (Z) = 0
Branch unconditionally
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
word (PC) ← (A)
word (PC) ← addr16
word (PC) ← (ear)
word (PC) ← (eam)
word (PC) ← (ear), (PCB) ← (ear +2)
word (PC) ← (eam), (PCB) ← (eam +2)
word (PC) ← ad24 0 to 15,
(PCB) ← ad24 16 to 23
word (PC) ← (ear)
word (PC) ← (eam)
word (PC) ← addr16
Vector call instruction
word (PC) ← (ear) 0 to 15
(PCB) ← (ear) 16 to 23
word (PC) ← (eam) 0 to 15
(PCB) ← (eam) 16 to 23
word (PC) ← addr0 to 15,
(PCB) ← addr16 to 23
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
4 when branching, 3 when not branching.
(b) + 3 × (c)
Read (word) branch address.
W: Save (word) to stack; R: read (word) branch address.
Save (word) to stack.
W: Save (long word) to W stack; R: read (long word) R branch address.
Save (long word) to stack.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
75
MB90660A Series
Table 19
Mnemonic
CBNE
A, #imm8, rel
CWBNE A, #imm16, rel
CBNE
CBNE
CWBNE
CWBNE
ear, #imm8, rel
eam, #imm8, rel*9
ear, #imm16, rel
eam, #imm16, rel*9
DBNZ
ear, rel
Branch 2 Instructions [19 Instructions]
#
~
RG
B
3
4
1
*
*1
0
0
0
0
4
4+
5
5+
*2
*3
*4
*3
1
0
1
0
0
(b)
0
(c)
3
*5
2
0
6
2
Operation
I
S
T
N
Z
V
C
RMW
Branch when byte (A) ≠ imm8
Branch when word (A) ≠ imm16
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
Branch when byte (ear) ≠ imm8
Branch when byte (eam) ≠ imm8
Branch when word (ear) ≠ imm16
Branch when word (eam) ≠ imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
*
*
*
–
*
Software interrupt
Software interrupt
Software interrupt
Software interrupt
Return from interrupt
–
–
–
–
–
–
–
–
–
–
R
R
R
R
*
S
S
S
S
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
–
At constant entry, save old frame
pointer to stack, set new frame
pointer, and allocate local pointer
area
At constant entry, retrieve old frame
pointer from stack.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Return from subroutine
Return from subroutine
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Branch when byte (ear) =
(ear) – 1, and (ear) ≠ 0
2× (b) Branch when byte (eam) =
(eam) – 1, and (eam) ≠ 0
DBNZ
eam, rel
3+
*
DWBNZ
ear, rel
3
*5
2
DWBNZ
eam, rel
3+
*6
2
Branch when word (ear) =
(ear) – 1, and (ear) ≠ 0
2× (c) Branch when word (eam) =
(eam) – 1, and (eam) ≠ 0
INT
INT
INTP
INT9
RETI
#vct8
addr16
addr24
2
3
4
1
1
20
16
17
20
15
0
0
0
0
0
8× (c)
6× (c)
6× (c)
8× (c)
6× (c)
LINK
#local8
2
6
0
(c)
UNLINK
1
5
0
(c)
RET *7
RETP *8
1
1
4
6
0
0
(c)
(d)
*1:
*2:
*3:
*4:
*5:
*6:
*7:
*8:
*9:
LH AH
0
5 when branching, 4 when not branching
13 when branching, 12 when not branching
7 + (a) when branching, 6 + (a) when not branching
8 when branching, 7 when not branching
7 when branching, 6 when not branching
8 + (a) when branching, 7 + (a) when not branching
Retrieve (word) from stack
Retrieve (long word) from stack
In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
76
MB90660A Series
Table 20
Mnemonic
Other Control Instructions (Byte/Word/Long Word) [36 Instructions]
#
~
RG
B
Operation
LH AH
I
S T N Z V C
RMW
PUSHW
PUSHW
PUSHW
PUSHW
A
AH
PS
rlst
1
1
1
2
4
4
4
*3
0
0
0
*5
(c)
(c)
(c)
*4
word (SP) ← (SP) –2, ((SP)) ← (A)
word (SP) ← (SP) –2, ((SP)) ← (AH)
word (SP) ← (SP) –2, ((SP)) ← (PS)
(SP) ← (SP) –2n, ((SP)) ← (rlst)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
POPW
POPW
POPW
POPW
A
AH
PS
rlst
1
1
1
2
3
3
4
*2
0
0
0
*5
(c)
(c)
(c)
*4
word (A) ← ((SP)), (SP) ← (SP) +2
word (AH) ← ((SP)), (SP) ← (SP) +2
word (PS) ← ((SP)), (SP) ← (SP) +2
(rlst) ← ((SP)), (SP) ← (SP) +2n
–
–
–
–
*
–
–
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
–
–
JCTX
@A
1
14
0
–
–
*
*
*
*
*
*
*
–
AND
OR
CCR, #imm8
CCR, #imm8
2
2
3
3
0
0
0
0
byte (CCR) ← (CCR) and imm8
byte (CCR) ← (CCR) or imm8
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
MOV RP, #imm8
MOV ILM, #imm8
2
2
2
2
0
0
0
0
byte (RP) ←imm8
byte (ILM) ←imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVEA RWi, ear
MOVEA RWi, eam
MOVEA A, ear
MOVEA A, eam
2
2+
2
2+
3
2+ (a)
1
1+ (a)
1
1
0
0
0
0
0
0
word (RWi) ←ear
word (RWi) ←eam
word(A) ←ear
word (A) ←eam
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ADDSP #imm8
ADDSP #imm16
2
3
3
3
0
0
0
0
word (SP) ← (SP) +ext (imm8)
word (SP) ← (SP) +imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOV
MOV
2
2
*1
1
0
0
0
0
byte (A) ← (brgl)
byte (brg2) ← (A)
Z
–
*
–
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
No operation
Prefix code for accessing AD space
Prefix code for accessing DT space
Prefix code for accessing PC space
Prefix code for accessing SP space
Prefix code for no flag change
Prefix code for common register bank
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
NOP
ADB
DTB
PCB
SPB
NCC
CMR
A, brgl
brg2, A
6× (c) Context switch instruction
*1: PCB, ADB, SSB, USB, and SPB : 1 state
DTB, DPR
: 2 states
*2: 7 + 3 × (pop count) + 2 × (last register number to be popped), 7 when rlst = 0 (no transfer register)
*3: 29 + (push count) – 3 × (last register number to be pushed), 8 when rlst = 0 (no transfer register)
*4: Pop count × (c), or push count × (c)
*5: Pop count or push count.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
77
MB90660A Series
Table 21
Mnemonic
Bit Manipulation Instructions [21 Instructions]
#
~
RG
B
(b)
(b)
(b)
MOVB
MOVB
MOVB
A, dir:bp
A, addr16:bp
A, io:bp
3
4
3
5
5
4
0
0
0
MOVB
MOVB
MOVB
dir:bp, A
addr16:bp, A
io:bp, A
3
4
3
7
7
6
0
0
0
SETB
SETB
SETB
dir:bp
addr16:bp
io:bp
3
4
3
7
7
7
CLRB
CLRB
CLRB
dir:bp
addr16:bp
io:bp
3
4
3
BBC
BBC
BBC
dir:bp, rel
addr16:bp, rel
io:bp, rel
BBS
BBS
BBS
Operation
byte (A) ← (dir:bp) b
byte (A) ← (addr16:bp) b
byte (A) ← (io:bp) b
LH AH
I
S T N Z V C
RMW
Z
Z
Z
*
*
*
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
2× (b) bit (dir:bp) b ← (A)
2× (b) bit (addr16:bp) b ← (A)
2× (b) bit (io:bp) b ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
*
*
*
0
0
0
2× (b) bit (dir:bp) b ← 1
2× (b) bit (addr16:bp) b ← 1
2× (b) bit (io:bp) b ← 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
7
7
7
0
0
0
2× (b) bit (dir:bp) b ← 0
2× (b) bit (addr16:bp) b ← 0
2× (b) bit (io:bp) b ← 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
4
5
4
*1
*1
*2
0
0
0
(b)
(b)
(b)
Branch when (dir:bp) b = 0
Branch when (addr16:bp) b = 0
Branch when (io:bp) b = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
dir:bp, rel
addr16:bp, rel
io:bp, rel
4
5
4
*1
*1
*2
0
0
0
(b)
(b)
(b)
Branch when (dir:bp) b = 1
Branch when (addr16:bp) b = 1
Branch when (io:bp) b = 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
SBBS
addr16:bp, rel
5
*3
0
2× (b) Branch when (addr16:bp) b = 1, bit = 1 –
–
–
–
–
–
*
–
–
*
WBTS
io:bp
3
*4
0
WBTC
io:bp
3
*4
0
*1:
*2:
*3:
*4:
*5:
*
5
Wait until (io:bp) b = 1
–
–
–
–
–
–
–
–
–
–
*
5
Wait until (io:bp) b = 0
–
–
–
–
–
–
–
–
–
–
8 when branching, 7 when not branching
7 when branching, 6 when not branching
10 when condition is satisfied, 9 when not satisfied
Undefined count
Until condition is satisfied
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
78
MB90660A Series
Table 22
Accumulator Manipulation Instructions (Byte/Word) [6 Instructions]
Mnemonic
#
~
RG
B
SWAP
SWAPW/XCHW AL, AH
EXT
EXTW
ZEXT
ZEXTW
1
1
1
1
1
1
3
2
1
2
1
1
0
0
0
0
0
0
0
0
0
0
0
0
Table 23
Mnemonic
Operation
byte (A) 0 to 7 ↔ (A) 8 to 15
word (AH) ↔ (AL)
byte sign extension
word sign extension
byte zero extension
word zero extension
LH AH
I
S
T
N
Z
V
C
RMW
–
*
–
X
–
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
R
R
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
I
S
T
N
Z
V
C
RMW
–
–
X
–
Z
–
String Instructions [10 Instructions]
#
~
MOVS/MOVSI
MOVSD
2
2
2
*
*2
*
*5
* Byte transfer @AH+ ← @AL+, counter = RW0
*3 Byte transfer @AH– ← @AL–, counter = RW0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
SCEQ/SCEQI
SCEQD
2
2
*1
*1
*5
*5
*4 Byte retrieval (@AH+) – AL, counter = RW0
*4 Byte retrieval (@AH–) – AL, counter = RW0
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
FISL/FILSI
2
6m +6
*5
*3 Byte filling @AH+ ← AL, counter = RW0
–
–
–
–
–
*
*
–
–
–
MOVSW/MOVSWI
MOVSWD
RG
5
B
Operation
3
LH AH
2
2
2
*
*2
*
*8
* Word transfer @AH+ ← @AL+, counter = RW0
*6 Word transfer @AH– ← @AL–, counter = RW0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
SCWEQ/SCWEQI
SCWEQD
2
2
*1
*1
*8
*8
*7 Word retrieval (@AH+) – AL, counter = RW0
*7 Word retrieval (@AH–) – AL, counter = RW0
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
FILSW/FILSWI
2
6m +6
*8
*6 Word filling @AH+ ← AL, counter = RW0
–
–
–
–
–
*
*
–
–
–
8
6
m: RW0 value (counter value)
n: Loop count
*1: 5 when RW0 is 0, 4 + 7 × (RW0) for count out, and 7 × n + 5 when match occurs
*2: 5 when RW0 is 0, 4 + 8 × (RW0) in any other case
*3: (b) × (RW0) + (b) × (RW0) when accessing different areas for the source and destination, calculate (b) separately
for each.
*4: (b) × n
*5: 2 × (RW0)
*6: (c) × (RW0) + (c) × (RW0) when accessing different areas for the source and destination, calculate (c) separately
for each.
*7: (c) × n
*8: 2 × (RW0)
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
79
MB90660A Series
■ MASK OPTION LIST
No.
1
2
Part number
MB60662A
MB90663A
MB90P663A
Specifying
procedure
Specify when
ordering masking
Set with EPROM
programmer
P00 to P07
P10 to P17
P20 to P27
P30 to P33
P40 to P47
P60 to P66
RST
DTTI
Pull-up resistor can be selected for
each pin
Pull-up resistor can be selected for
each pin
MD2
Pull-down resistor
Cannot be selected; pull-down
resistor not provided
MD1
Pull-up resistor
MD0
Pull-up resistor
Can be selected
all at once
Pull-up resistor
Pull-up resistor
Can be selected
all at once
Accept asynchronous reset
input
3
Can be selected
Can be selected
Accepted
Not accepted
Notes: • A specification of “yes” for accept asynchronous reset input refers to a function whereby reset input is
accepted when oscillation for output ports (including peripheral resource output) is stopped and port output
(including peripheral resource output) is forced Hi-z. Note, however, that since internal reset (reset of the
CPU and peripheral resources) is synchronized with the clock, the CPU and peripheral resources are not
initialized when the clock is stopped.
• For details on writing to the MB90P663A, see Chapter 6, “■ PROGRAMMING THE MB90P663A EPROM”.
• Use of a pull-up/pull-down resistors for the mode pins (MD2 to MD0) can be selected separately for each
pin. If “yes” is selected, a pull-up is attached to MD0 and MD1 and a pull-down to MD2 for mask ROM
versions. A pull-up is attached to MD0 and MD1, but a pull-down is not attached to MD2 for OTP versions.
• Since it takes eight machine cycles to make option settings for the MB90P663A, options cannot be set
between when power is first turned on and the clock is supplied. (This results in a setting of no pull-up for
all pins and accept asynchronous reset input.)
80
MB90660A Series
■ ORDERING INFORMATION
Part number
Package
MB90662AP-SH
MB90663AP-SH
MB90P663AP-SH
64-pin plastic SH-DIP (DIP-64P-M01)
MB90662APFM
MB90663APFM
MB90P663APFM
64-pin plastic LQFP (FTP-64P-M09)
Remarks
81
MB90660A Series
■ PACKAGE DIMENSIONS
64-pin Plastic SH-DIP
(DIP-64P-M01)
+0.22
58.00 –0.55
+.008
2.283 –.022
INDEX-1
17.00±0.25
(.669±.010)
INDEX-2
5.65(.222)MAX
0.25±0.05
(.010±.002)
3.00(.118)MIN
+0.50
1.00 –0
+.020
.039 –0
0.51(.020)MIN
0.45±0.10
(.018±.004)
15°MAX
19.05(.750)
TYP
1.778±0.18
(.070±.007)
1.778(.070)
MAX
C
55.118(2.170)REF
1994 FUJITSU LIMITED D64001S-3C-4
Dimensions in mm (inches)
64-pin Plastic LQFP
(FPT-64P-M09)
14.00±0.20(.551±.008)SQ
48
33
12.00±0.10(.472±.004)SQ
49
+0.20
1.50 –0.10
+.008
.059 –.004
32
9.75
(.384)
REF
13.00
(.512)
NOM
1 PIN INDEX
64
LEAD No.
17
1
0.65(.0256)TYP
Details of "A" part
16
0.30±0.10
(.012±.004)
"A"
0.13(.005)
M
+0.05
0.127 –0.02
+.002
.005 –.001
0.10±0.10 (STAND OFF)
(.004±.004)
0.10(.004)
0
C
82
1994 FUJITSU LIMITED F64018S-1C-2
10°
0.50±0.20
(.020±.008)
Dimensions in mm (inches)
MB90660A Series
MEMO
83
MB90660A Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-88, Japan
Tel: (044) 754-3763
Fax: (044) 754-3329
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
Fax: (408) 432-9044/9045
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document presented
as examples of semiconductor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the
use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.
F9703
 FUJITSU LIMITED Printed in Japan
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