Intersil AD7521LN 10-bit, 12-bit, multiplying d/a converter Datasheet

AD7520, AD7530,
AD7521, AD7531
10-Bit, 12-Bit, Multiplying D/A Converters
August 1997
Features
Description
• AD7520/AD7530, 10-Bit Resolution; 8-Bit, 9-Bit and
10-Bit Linearity
The AD7520/AD7530 and AD7521/AD7531 are monolithic,
high accuracy, low cost 10-bit and 12-bit resolution,
multiplying digital-to-analog converters (DAC). Intersil’
thin-film on CMOS processing gives up to 10-bit accuracy
with TTL/CMOS compatible operation. Digital inputs are fully
protected against static discharge by diodes to ground and
positive supply.
• AD7521/AD7531, 12-Bit Resolution; 8-Bit, 9-Bit and
10-Bit Linearity
• Low Power Dissipation (Max) . . . . . . . . . . . . . . . .20mW
• Low Nonlinearity Tempco at 2ppm of FSR/oC
• Current Settling Time to 0.05% of FSR . . . . . . . . 1.0µs
• Supply Voltage Range . . . . . . . . . . . . . . . . ±5V to +15V
• TTL/CMOS Compatible
• Full Input Static Protection
• /883B Processed Versions Available
Typical applications include digital/analog interfacing,
multiplication and division, programmable power supplies,
CRT character generation, digitally controlled gain circuits,
integrators and attenuators, etc.
The AD7530 and AD7531 are identical to the AD7520 and
AD7521, respectively, with the exception of output leakage
current and feedthrough specifications.
Ordering Information
LINEARITY (INL, DNL)
TEMP. RANGE (oC)
AD7520JN, AD7530JN
0.2% (8-Bit)
0 to 70
16 Ld PDIP
E16.3
AD7520KN, AD7530KN
0.1% (9-Bit)
0 to 70
16 Ld PDIP
E16.3
AD7521JN, AD7531JN
0.2% (8-Bit)
0 to 70
18 Ld PDIP
E18.3
PART NUMBER
PACKAGE
PKG. NO.
AD7521KN, AD7531KN
0.1% (9-Bit)
0 to 70
18 Ld PDIP
E18.3
AD7520LN, AD7530LN
0.05% (10-Bit)
-40 to 85
16 Ld PDIP
E16.3
AD7521LN, AD7531LN
0.05% (10-Bit)
-40 to 85
18 Ld PDIP
E18.3
AD7520JD
0.2% (8-Bit)
-25 to 85
16 Ld CERDIP
F16.3
AD7520KD
0.1% (9-Bit)
-25 to 85
16 Ld CERDIP
F16.3
AD7520LD
0.05% (10-Bit)
-25 to 85
16 Ld CERDIP
F16.3
AD7520SD, AD7520SD/883B
0.2% (8-Bit)
-55 to 125
16 Ld CERDIP
F16.3
AD7520UD, AD7520UD/883B
0.05% (10-Bit)
-55 to 125
16 Ld CERDIP
F16.3
Pinouts
AD7520, AD7530
(CERDIP, PDIP)
TOP VIEW
AD7521, AD7531
(PDIP)
TOP VIEW
IOUT1 1
16 RFEEDBACK
IOUT1 1
18 RFEEDBACK
IOUT2 2
15 VREF
IOUT2 2
17 VREF
GND 3
BIT 1 (MSB) 4
14 V+
13 BIT 10 (LSB)
GND
3
16 V+
BIT 1 (MSB)
4
15 BIT 12 (LSB)
BIT 2 5
12 BIT 9
BIT 2
5
14 BIT 11
BIT 3 6
11 BIT 8
BIT 3
6
13 BIT 10
BIT 4 7
10 BIT 7
BIT 4
7
12 BIT 9
BIT 5 8
9 BIT 6
BIT 5
8
11 BIT 8
BIT 6
9
10 BIT 7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
10-7
File Number
3104.1
AD7520, AD7530, AD7521, AD7531
Absolute Maximum Ratings
Thermal Information
Supply Voltage (V+ to GND). . . . . . . . . . . . . . . . . . . . . . . . . . . +17V
VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V
Digital Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . V+ to GND
Output Voltage Compliance . . . . . . . . . . . . . . . . . . . . -100mV to V+
Thermal Resistance (Typical, Note 1)
θJA (oC/W) θJC (oC/W)
16 Ld PDIP Package . . . . . . . . . . . . . . . .
100
N/A
18 Ld PDIP Package . . . . . . . . . . . . . . . .
90
N/A
CERDIP Package . . . . . . . . . . . . . . . . . .
75
20
Maximum Junction Temperature (Hermetic Package) . . . . . . . . 175oC
Maximum Junction Temperature (Plastic Packages) . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Ranges
JN, KN, LN Versions . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC
JD, KD, LD Versions . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC
SD, UD Versions . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy electrostatic fields. Keep
unused units in conductive foam at all times.
Do not apply voltages higher than VDD or less than GND potential on any terminal except VREF and RFEEDBACK.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
V+ = +15V, VREF = +10V, TA = 25oC Unless Otherwise Specified
AD7520/AD7530
PARAMETER
TEST CONDITIONS
MIN
TYP
AD7521/AD7531
MAX
MIN
TYP
MAX
UNITS
SYSTEM PERFORMANCE (Note 2)
Resolution
10
10
10
12
12
12
Bits
J, S
S Over -55oC to 125oC
(Notes 2, 5) (Figure 3)
-
-
±0.2
(8-Bit)
-
-
±0.2
(8-Bit)
% of
FSR
K
T Over -55oC to 125oC
(Figure 2)
-
-
±0.1
(9-Bit)
-
-
±0.1
(9-Bit)
% of
FSR
L, U
-10V ≤ VREF ≤ +10V
U Over -55oC to 125oC
(Figure 2)
-
-
±0.05
(10-Bit)
-
-
±0.05
(10-Bit)
% of
FSR
-10V ≤ VREF ≤ +10V
(Notes 3, 4)
-
-
±2
-
-
±2
ppm of
FSR/oC
Gain Error
-
±0.3
-
-
±0.3
-
% of
FSR
Gain Error Tempco
-
-
±10
-
-
±10
ppm of
FSR/oC
Over the Specified
Temperature Range
-
-
±200
(±300)
-
-
±200
(±300)
nA
Output Current Settling Time
To 0.05% of FSR (All Digital
Inputs Low To High And High
To Low) (Note 4) (Figure 7)
-
1.0
-
-
1.0
-
µs
Feedthrough Error
VREF = 20VP-P , 10kHz
(50kHz) All Digital Inputs Low
(Note 4) (Figure 6)
-
-
10
-
-
10
mVP-P
All Digital Inputs High
IOUT1 at Ground
5
10
20
5
10
20
kΩ
IOUT1 All Digital Inputs High
(Note 4) (Figure 5)
IOUT2
-
200
-
-
200
-
pF
-
75
-
-
75
-
pF
-
75
-
-
75
-
pF
-
200
-
-
200
-
pF
Nonlinearity
Nonlinearity Tempco
Output Leakage Current
(Either Output)
DYNAMIC CHARACTERISTICS
REFERENCE INPUT
Input Resistance
ANALOG OUTPUT
Output Capacitance
IOUT1 All Digital Inputs Low
(Note 4) (Figure 5)
IOUT2
10-8
AD7520, AD7530, AD7521, AD7531
V+ = +15V, VREF = +10V, TA = 25oC Unless Otherwise Specified (Continued)
Electrical Specifications
AD7520/AD7530
PARAMETER
TEST CONDITIONS
Output Noise
AD7521/AD7531
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Both Outputs
(Note 4) (Figure 4)
-
Equivalent
to 10kΩ
-
-
Equivalent
to 10kΩ
-
Johnson
Noise
Over the Specified
Temperature Range
VIN = 0V or +15V
-
-
0.8
-
-
0.8
V
2.4
-
-
2.4
-
-
V
-
-
±1
-
-
±1
µA
±0.005
-
% FSR/
% ∆V+
DIGITAL INPUTS
Low State Threshold, VIL
High State Threshold, VIH
Input Current, IIL, IIH
Input Coding
See Tables 1 and 2
Binary/Offset Binary
POWER SUPPLY CHARACTERISTICS
Power Supply Rejection
V+ = 14.5V to 15.5V
(Note 3) (Figure 3)
-
Power Supply Voltage Range
±0.005
-
-
+5 to +15
I+
Total Power Dissipation
+5 to +15
V
All Digital Inputs at 0V or V+
Excluding Ladder Network
-
±1
-
-
±1
-
µA
All Digital Inputs High or Low
Excluding Ladder Network
-
-
2
-
-
2
mA
Including the Ladder Network
-
20
-
-
20
-
mW
NOTES:
2. Full scale range (FSR) is 10V for Unipolar and ±10V for Bipolar modes.
3. Using internal feedback resistor RFEEDBACK .
4. Guaranteed by design, or characterization and not production tested.
5. Accuracy not guaranteed unless outputs at GND potential.
6. Accuracy is tested and guaranteed at V+ = 15V only.
Functional Diagram
10kΩ
VREF
20kΩ
10kΩ
20kΩ
10kΩ
20kΩ
10kΩ
20kΩ
20kΩ
20kΩ
GND
SPDT NMOS
SWITCHES
IOUT2
IOUT1
10kΩ
MSB
BIT 2
BIT 3
NOTES:
Switches shown for Digital Inputs “High”.
Resistor values are typical.
10-9
RFEEDBACK
AD7520, AD7530, AD7521, AD7531
Pin Descriptions
AD7520/30
AD7521/31
PIN NAME
DESCRIPTION
1
1
IOUT1
2
2
IOUT2
Current Out summing junction of the R2R ladder network.
Current Out virtual ground, return path for the R2R ladder network.
3
3
GND
Digital Ground. Ground potential for digital side of D/A.
4
4
5
5
Bit 2
Digital Bit 2.
6
6
Bit 3
Digital Bit 3.
7
7
Bit 4
Digital Bit 4.
8
8
Bit 5
Digital Bit 5.
Bits 1(MSB) Most Significant Digital Data Bit.
9
9
Bit 6
Digital Bit 6.
10
10
Bit 7
Digital Bit 7.
11
11
Bit 8
Digital Bit 8.
12
12
Bit 9
Digital Bit 9.
13
13
Bit 10
Digital Bit 10 (AD7521/31). Least Significant Digital Data Bit (AD7520/30).
-
14
Bit 11
Digital Bit 11 (AD7521/31).
-
15
Bit 12
14
16
V+
15
17
16
18
VREF
Least Significant Digital Data Bit (AD7521/31).
Power Supply +5V to +15V.
Voltage Reference Input to set the output range. Supplies the R2R resistor ladder.
RFEEDBACK Feedback resistor used for the current to voltage conversion when using an external Op Amp.
Definition of Terms
Nonlinearity: Error contributed by deviation of the DAC
transfer function from a “best straight line” through the actual
plot of transfer function. Normally expressed as a percentage of full scale range or in (sub)multiples of 1 LSB.
Resolution: It is addressing the smallest distinct analog
output change that a D/A converter can produce. It is
commonly expressed as the number of converter bits. A
converter with resolution of n bits can resolve output changes
of 2-N of the full-scale range, e.g., 2-N VREF for a unipolar
conversion. Resolution by no means implies linearity.
Settling Time: Time required for the output of a DAC to settle to within specified error band around its final value (e.g.,
1/ LSB) for a given digital input change, i.e., all digital inputs
2
LOW to HIGH and HIGH to LOW.
Gain Error: The difference between actual and ideal analog
output values at full scale range, i.e., all digital inputs at
HIGH state. It is expressed as a percentage of full scale
range or in (sub)multiples of 1 LSB.
Feedthrough Error: Error caused by capacitive coupling
from VREF to IOUT1 with all digital inputs LOW.
Output Capacitance: Capacitance from IOUT1 and IOUT2
terminals to ground.
or current reference and an operational amplifier are all that
is required for most voltage output applications.
A simplified equivalent circuit of the DAC is shown in the
Functional Diagram. The NMOS SPDT switches steer the ladder leg currents between IOUT1 and IOUT2 buses which must
be held either at ground potential. This configuration maintains a constant current in each ladder leg independent of the
input code.
Converter errors are further reduced by using separate
metal interconnections between the major bits and the
outputs. Use of high threshold switches reduce offset (leakage) errors to a negligible level.
The level shifter circuits are comprised of three inverters with
positive feedback from the output of the second to the first, see
Figure 1. This configuration results in TTL/CMOS compatible
operation over the full military temperature range. With the ladder SPDT switches driven by the level shifter, each switch is
binarily weighted for an ON resistance proportional to the
respective ladder leg current. This assures a constant voltage
drop across each switch, creating equipotential terminations for
the 2R ladder resistors and highly accurate leg currents.
V+
1 3
Output Leakage Current: Current which appears on IOUT1
terminal when all digital inputs are LOW or on IOUT2
terminal when all digital inputs are HIGH.
4
6
TO LADDER
8
9
Detailed Description
The AD7520, AD7530, AD7521 and AD7531 are monolithic,
multiplying D/A converters. A highly stable thin film R-2R
resistor ladder network and NMOS SPDT switches form the
basis of the converter circuit, CMOS level shifters permit low
power TTL/CMOS compatible operation. An external voltage
DTL/TTL/
CMOS INPUT
10-10
2
5
7
IOUT2 IOUT1
FIGURE 1. CMOS SWITCH
AD7520, AD7530, AD7521, AD7531
Test Circuits
The following test circuits apply for the AD7520. Similar circuits are used for the AD7530, AD7521 and AD7531.
VREF
+15V
BIT 1
(MSB)
10-BIT
BINARY
COUNTER
RFEEDBACK
4 15 16
IOUT1
1
5
AD7520
HA2600
I
BIT 10
13 3 2 OUT2 +
(LSB)
+15V
10kΩ
0.01%
1MΩ
GND
CLOCK
BIT 1
(LSB)
BIT 11
+10V
10kΩ 0.01%
12-BIT
REFERENCE
DAC
HA2600
+
LINEARITY
ERROR
X 100
BIT 10
(LSB)
BIT 12
500kΩ
BIT 1
(MSB)
-
VREF
BIT 10
VREF
UNGROUNDED
SINE WAVE
GENERATOR
400Hz 1VP-P
5K 0.01%
5kΩ 0.01%
15 14 RFEEDBACK
4
16 I
OUT1
1
5
AD7520 I
OUT2 HA2600
13 3 2
+
HA2600
+
GND
FIGURE 2. NONLINEARITY
FIGURE 3. POWER SUPPLY REJECTION
+11V (ADJUST FOR VOUT = 0V)
+15V
1K
f = 1kHz
BW = 1Hz
15µF
100Ω
15 14 IOUT2
4
2
5
AD7520 IOUT1
13 3 1
NC +15V
+15V
10kΩ
QUAN
TECH
MODEL 134D
101ALN
WAVE
VOUT ANALYZER
+
BIT 1 (MSB)
-
1kΩ
50kΩ
50V
BIT 10 (LSB)
0.1µF
FIGURE 4. NOISE
VREF = 20VP-P
100kHz SINE WAVE
+15V
BIT 1 (MSB)
15
14
4
16
5
AD7520
1
BIT 10 (LSB)
2
NC
1kΩ
100mVP-P
1MHz
SCOPE
FIGURE 5. OUTPUT CAPACITANCE
-10V
13 3
15
14
4
16
5
AD7520
1
13 3 2
VREF
BIT 1 (MSB)
IOUT1
3
IOUT2
6
HA2600
2 +
+5V
0V
VOUT
DIGITAL
INPUT
BIT 10 (LSB)
GND
5t: 1% SETTLING (1mV)
EXTRAPOLATE 8t: 0.03% SETTLING
t = RISE TIME
+15V
15
14
4
5
AD7520
1
13 3
2
SCOPE
+100mV
IOUT2
100Ω
GND
FIGURE 6. FEEDTHROUGH ERROR
FIGURE 7. OUTPUT CURRENT SETTLING TIME
10-11
AD7520, AD7530, AD7521, AD7531
Applications
“Digital Input Code/Analog Output Value” table for bipolar
mode is given in Table 2.
Unipolar Binary Operation
+15V
BIT 1 (MSB)
DIGITAL
INPUT
BIT 10 (LSB)
BIT 10
(LSB)
15
14
4
16
5
AD7520
1
13 3
2
10MΩ
15
14
RFEEDBACK
4
16
5
IOUT1
AD7520 1
13 3
2
IOUT2
-
-
R1 10K R2 10K
0.01% 0.01%
6
+
VOUT
BIT 1
(MSB)
+15V
VREF
R3
VREF
DIGITAL
INPUT
The circuit configuration for operating the AD7520 in unipolar mode is shown in Figure 8. Similar circuits can be used
for AD7521, AD7530 and AD7531. With positive and negative VREF values the circuit is capable of 2-Quadrant multiplication. The “Digital Input Code/Analog Output Value” table
for unipolar mode is given in Table 1.
6
+
RFEEDBACK
IOUT1
6
+
IOUT2
VOUT
FIGURE 9. BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION)
TABLE 2. BlPOLAR (OFFSET BINARY) CODE TABLE
GND
DIGITAL INPUT
FIGURE 8. UNIPOLAR BINARY OPERATION (2-QUADRANT
MULTIPLICATION)
TABLE 1. CODE TABLE - UNlPOLAR BINARY OPERATION
DIGITAL INPUT
ANALOG OUTPUT
1111111111
-VREF (1-2-N)
1000000001
-VREF (1/2 + 2-N)
1000000000
-VREF/2
0111111111
-VREF (1/2-2-N)
0000000001
-VREF (2-N)
0000000000
0
ANALOG OUTPUT
1111111111
-VREF (1-2-(N-1))
1000000001
-VREF (2-(N-1))
1000000000
0
0111111111
VREF (2-(N-1))
0000000001
VREF (1-2-(N-1))
0000000000
VREF
NOTES:
1. LSB = 2-(N-1) VREF .
2. N = 10 for 7520, 7521;
N = 12 for 7530, 7531.
A “Logic 1” input at any digital input forces the corresponding
ladder switch to steer the bit current to IOUT1 bus. A “Logic 0”
input forces the bit current to IOUT2 bus. For any code the
IOUT1 and IOUT2 bus currents are complements of one
another. The current amplifier at IOUT2 changes the polarity of
IOUT2 current and the transconductance amplifier at IOUT1 output sums the two currents. This configuration doubles the output range. The difference current resulting at zero offset binary
code, (MSB = “Logic 1”, All other bits = “Logic 0”), is corrected
by using an external resistor, (10MΩ), from VREF to IOUT2 .
NOTES:
1. LSB = 2-N VREF .
2. N = 10 for 7520, 7530;
N = 12 for 7521, 7531.
Zero Offset Adjustment
1. Connect all digital inputs to GND.
Offset Adjustment
2. Adjust the offset zero adjust trimpot of the output
operational amplifier for 0V at VOUT .
1. Adjust VREF to approximately +10V.
2. Connect all digital inputs to “Logic 1”.
Gain Adjustment
3. Adjust IOUT2 amplifier offset adjust trimpot for 0V ±1mV at
IOUT2 amplifier output.
1. Connect all digital inputs to V+.
2. Monitor VOUT for a -VREF (1-2-N) reading. (N = 10 for
AD7520/30 and N = 12 for AD7521/31).
4. Connect MSB (Bit 1) to “Logic 1” and all other bits to “Logic 0”.
3. To decrease VOUT , connect a series resistor (0 to 250Ω)
between the reference voltage and the VREF terminal.
4. To increase VOUT , connect a series resistor (0 to 250Ω) in
the IOUT1 amplifier feedback loop.
Bipolar (Offset Binary) Operation
The circuit configuration for operating the AD7520 in the
bipolar mode is given in Figure 9. Similar circuits can be
used for AD7521, AD7530 and AD7531. Using offset binary
digital input codes and positive and negative reference voltage values, 4-Quadrant multiplication can be realized. The
5. Adjust IOUT1 amplifier offset adjust trimpot for 0V ±1mV at
VOUT.
Gain Adjustment
1. Connect all digital inputs to V+.
2. Monitor VOUT for a -VREF (1-2-(N-1) volts reading. (N = 10 for
AD7520 and AD7530, and N = 12 for AD7521 and AD7531).
3. To increase VOUT , connect a series resistor of up to 250Ω
between VOUT and RFEEDBACK .
4. To decrease VOUT , connect a series resister of up to 250Ω
between the reference voltage and the VREF terminal.
10-12
AD7520, AD7530, AD7521, AD7531
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
101 mils x 103 mils (2565micrms x 2616micrms)
Type: PSG/Nitride
PSG: 7 ±1.4kÅ
Nitride: 8 ±1.2kÅ
METALLIZATION:
Type: Pure Aluminum
Thickness: 10 ±1kÅ
PROCESS:
CMOS Metal Gate
Metallization Mask Layout
AD7520, AD7530
PIN 7
BIT 4
PIN 6
BIT 3
PIN 5
BIT 2
PIN 4
BIT 1
(MSB)
PIN 3
GND
PIN 2
IOUT2
PIN 8
BIT 5
PIN 1
IOUT1
PIN 9
BIT 6
PIN 10
BIT 7
PIN 16
RFEEDBACK
PIN 11
BIT 8
PIN 15
VREF
PIN 14
V+
PIN 12
BIT 9
NC
PIN 13
BIT 10
(LSB)
10-13
NC
AD7520, AD7530, AD7521, AD7531
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
101 mils x 103 mils (2565micrms x 2616micrms)
Type: PSG/Nitride
PSG: 7 ±1.4kÅ
Nitride: 8 ±1.2kÅ
METALLIZATION:
Type: Pure Aluminum
Thickness: 10 ±1kÅ
PROCESS:
CMOS Metal Gate
Metallization Mask Layout
AD7521, AD7531
PIN 7
BIT 4
PIN 6
BIT 3
PIN 5
BIT 2
PIN 4
BIT 1
(MSB)
PIN 3
GND
PIN 2
IOUT2
PIN 8
BIT 5
PIN 1
IOUT1
PIN 9
BIT 6
PIN 10
BIT 7
PIN 18
RFEEDBACK
PIN 11
BIT 8
PIN 17
VREF
PIN 16
V+
PIN 12
BIT 9
PIN 13
BIT 10
PIN 14
BIT 11
10-14
PIN 15
BIT 12
(LSB)
AD7520, AD7530, AD7521, AD7531
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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10-15
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