FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16310-1E
32-Bit Microcontroller
CMOS
FR30 Series
MB91F127/F128
■ DESCRIPTION
This model, designed on the basis of 32-bit RISC CPU (FR30 series), is a standard single-chip micro controller
with built-in I/O resources and bus control functions. The functions are suitable for built-in control that requires
high-speed CPU processing.
MB91F127 includes 256 Kbytes built-in flash memory and 14 Kbytes built-in RAM. MB91F128 includes 510 Kbytes
built-in flash memory and 14 Kbytes built-in RAM.
The specifications of the devices are best suited for applications requiring high-level CPU processing capabilities,
such as navigation system, high-performance FAX, and printer controller.
■ FEATURES
FR-CPU
• 32-bit RISC (FR30), load/store architecture, 5-step pipeline
• Operating frequency : Internal 25 MHz
• General register : 32bit x 16 registers
• 16-bit fixed-length instructions (primitives), 1 instruction/1 cycle
• Instructions of memory-to-memory transfer, bit processing, and barrel shift : Instructions suitable for built-in
control
(Continued)
■ PACKAGE
100 pin, Plastic LQFP
(FPT-100P-M05)
MB91F127/F128
• Function entry/exit instructions, multi load/store instruction for register data : High-level language compatible
instructions
• Register interlock functions : Simple description of assembler language
• Branch instructions with delay slot : Reduced overhead on branching process
• Built-in multiplier/ Supporting at instruction level
Signed 32-bit multiplying : 5 cycles
Signed 16-bit multiplying : 3 cycles
• Interrupt (saving PC and PS) : 6 cycles, 16 priority levels
Bus interface
• Maximum of 25 MHz internal operation rate
• 25-bit address bus (32 MB space)
• 16-bit address output, 8/16-bit data input/output
• Basic bus cycle : 2-clock cycle
• Chip selection outputs specifiable in a minimum of 64 Kbytes steps : 6 outputs
• Automatic wait cycle : Specifiable flexibly from 0 cycle to 7 cycles for each area
• Supporting time-division input/output interface for address/data (for area 1 only)
• Unassigned data/address terminals are available as input/output ports
• Supporting little endian mode (selecting one area from area 1 to area 5)
DMAC (DMA controller)
• 8 channels
• Transfer factor : Interrupt request of built-in resources
• Transfer sequence : Step transfer/Block transfer/Burst transfer/Consecutive transfer
• Transfer data length : Selectable among 8 bits, 16 bits, and 32 bits
• Pausing is allowed by interrupt request
UART
• 3 channels
• Full-duplex double buffer
• Data length : 7 to 9 bits (no parity), 6 to 8 bits (with parity)
• Asynchronous (start-stop synchronization) or CLK synchronous communication is selectable
• Multi processor mode
• Built-in 16-bit timer (U-Timer) used as a baud-rate generator : Generates an arbitrary baud rate
• External clock is available as a transfer clock
• Error detection : parity, frame, and overrun
A/D converter (sequential transducer)
• 8/10-bit resolution, 8 channels
• Sequential comparison and transducer : At 25 MHz, 5.2 µs
• Built-in sample and hold circuit
• Conversion mode : Selectable among single conversion, scan conversion, and repeat conversion
• Activation : Selectable among software, external trigger, and built-in timer
Reload timer
• 16-bit timer : 3 channels
• Internal clock : 2-clock cycle resolution, selectable among 2/8/32 dividing and external clock
(Continued)
2
MB91F127/F128
(Continued)
Other interval timers
• 16-bit timer : 3 channels (U-Timer)
• PPG timer : 4 channels
• 16-bit OCU : 4 channels, ICU : 4 channels, Free-run timer : 1 channel
• Watchdog timer: 1 channel
Flash memory 510 KB
• 510 KB FLASH ROM: Read/Write/Erase is allowed with a same power
Built- in RAM 14 KB
• D-bus RAM 12 KB, C-bus RAM 2 KB
Bit search module
• Position of a first bit that changes between “1” and “0” is searched in one cycle, within an MSB of one word.
Interrupt controller
• External interrupt input : Normal interrupt×6 (INT0 to INT5)
• Internal interrupt factors : UART, DMAC, A/D, Reload timer, UTIMER, delay interrupt, PPG, ICU, and OCU
• Priority levels are programmable (16 levels)
Reset factors
• Power-on reset/watchdog timer/software reset/external reset
Low power consumption mode
• Sleep/stop mode
Clock control
• Built-in PLL circuit, selectable among 1-multiplication, and 2-multiplication
• Gearing function : Operation clock frequencies are freely and independently specifiable for CPU and
peripherals.
Gear clocks are selectable among 1/1, 1/2, 1/4, and 1/8 (or among 1/2, 1/4, 1/8, and 1/16).
Upper limit of peripheral operations is 25 MHz.
Others
• Package : LQFP-100
• CMOS technology : 0.35 µm
• Power supply voltage : 3.3 V±0.3 V
■ SERIES CONFIGURATION
Model name
MB91F127
MB91F128
MB91FV129
Quantity production
Quantity production
Evaluation product
FLASH memory
256 KB
510 KB
510 KB
D-bus RAM
12 KB
12 KB
16 KB
C-bus RAM
2 KB
2 KB
2 KB
Outline
3
MB91F127/F128
■ PIN ASSIGNMENT
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P21/D17
P22/D18
P23/D19
P24/D20
P25/D21
P26/D22
P27/D23
P30/D24
P31/D25
P32/D26
P33/D27
P34/D28
P35/D29
P36/D30
VSS
P37/D31
P40/A00
VCC
P41/A01
P42/A02
P43/A03
P44/A04
P45/A05
P46/A06
P47/A07
PG5/OC1
PG6/OC2
PG7/OC3
VCC
PA6/CLK
PA5/CS5/SC1
PA4/CS4/SI1
PA3/CS3/SO1
PA2/CS2
PA1/CS1
PA0/CS0
P86/ALE
HST
RST
VSS
MD0
MD1
MD2
P80/RDY
P81/BGRNT/IN0
P82/BRQ/IN1
P83/RD
P84/WR0
P85/WR1
P20/D16
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PG4/OC0
PG3/OCPA3
PG2/OCPA2
PG1/OCPA1
PG0/OCPA0
PE0/INT0
PE1/INT1
VCC
X0
X1
VSS
PE2/INT2
PE3/INT3
PE4/INT4/TCI1
PE5/INT5/SC0
PE6/SI0
PE7/SO0
PF3/SC2/ATG
PF2/SO2
PF1/SI2
PF0/TCI0
PJ7/AN7
PJ6/AN6
PJ5/AN5
PJ4/AN4
(TOP VIEW)
(FPT-100P-M05)
4
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PJ3/AN3
PJ2/AN2
PJ1/AN1
PJ0/AN0
AVSS/AVRL
AVRH
AVCC
P70/A24/FRCK/TCI2
P67/A23/IN3
P66/A22/IN2
VSS
P65/A21
P64/A20
P63/A19
P62/A18
P61/A17
P60/A16
P57/A15
P56/A14
P55/A13
P54/A12
P53/A11
P52/A10
P51/A09
P50/A08
MB91F127/F128
■ PIN DESCRIPTION
Note that the numbers in the table are not pin numbers on a package.
Input/output
No.
Pin name
Description
circuit type
1
2
3
4
5
6
7
8
D16/P20
D17/P21
D18/P22
D19/P23
D20/P24
D21/P25
D22/P26
D23/P27
D
Bit 16 through bit 23 of external data bus.
The terminals are available as general I/O ports (P20 through
P27) when external bus width is specified at 8 bits or in singlechip mode.
9
10
11
12
13
14
15
16
D24/P30
D25/P31
D26/P32
D27/P33
D28/P34
D29/P35
D30/P36
D31/P37
D
Bit 24 through bit 31 of external data bus.
The terminals are available as general I/O ports (P30 through
P37) when the terminals are not used.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A00/P40
A01/P41
A02/P42
A03/P43
A04/P44
A05/P45
A06/P46
A07/P47
A08/P50
A09/P51
A10/P52
A11/P53
A12/P54
A13/P55
A14/P56
A15/P57
D
Bit 00 through bit 15 of external address bus.
The terminals are available as general I/O ports (P40 through
P47 and P50 through P57) when the terminals are not used as
address buses.
33
34
35
36
37
38
39
40
A16/P60
A17/P61
A18/P62
A19/P63
A20/P64
A21/P65
A22/P66/IN2
A23/P67/IN3
D
Bit 16 through bit 23 of external address bus.
The terminals are available as general I/O ports (P60 through
P67) when the terminals are not used as address busses.
[IN2,IN3]: Input terminals of input capture.
This function is active when input capture is operating.
(Continued)
5
MB91F127/F128
No.
Pin name
Input/output
circuit type
Description
41
A24/P70/FRCK/
TCI2
D
Bit 24 of external address bus.
[P70] A24, FRCK and TCI2 are available as general input ports
when they are not used.
[FRCK] External clock input of free-run timer. This function is
active when external clock input of free-run timer is used.
[TCI2] External clock input of timer 2. This function is active
when external clock input of timer 2 is used.
42
RDY/P80
D
External ready input. Enter “0” when bus cycle under execution
does not complete. This terminal is available as general input/
output port when it is not used.
D
External bus open receive output. This terminal outputs “L”
when an external bus is released. This terminal is available as
general input/output port when it is not used.
[IN0] Input capture input.
This function is active when input capture is under input operation.
43
BGRNT/P81/IN0
44
BRQ/P82/IN1
D
External bus open request input. Enter “1” when releasing external bus. This terminal is available as general input/output port
when it is not used.
[IN1] Input capture input.
This function is active when input capture is under input operation.
45
RD/P83
D
External bus read strobe.
This terminal is available as general input/output port when it is
not used.
46
WR0/P84
D
47
WR1/P85
D
External bus write strobe.Control signals and data bus byte positions are related as the following :
16-bit bus
width
8-bit bus width
Single chip
mode
D31 to D24
WR0
WR0
(port allowed)
D23 to D16
WR1
(port allowed)
(port allowed)
Note : WR1 is set to Hi-z during resetting.
For using with 16-bit bus width, use an external pull-up
resistor.
[P84 or P85] Available as general input/output ports when WR0
and WR1 are not used.
48
49
50
CS0/PA0
CS1/PA1
CS2/PA2
D
Chip select 0 output (Low active)
Chip select 1 output (Low active)
Chip select 2 output (Low active)
[PA0,1,or 2] Available as general input/output ports when CS0,
CS1 and CS2 are not used.
(Continued)
6
MB91F127/F128
Input/output
circuit type
Description
CS3/PA3/SO1
CS4/PA4/SI1
CS5/PA5/SC1
D
Chip select 3, 4, 5 output (Low active).
[PA3,4,5] Available as general input/output ports when channel
1 of chip select UART is not used.
[SO1,SI1,SC1] Data output, data input, and clock terminals of
UART1. Active when UART1 operation is allowed.
54
CLK/PA6
D
System clock output. Outputs a same clock as the same frequency of external bus operation.
[PA6] Available as general input/output ports it is not used.
55
56
57
58
59
60
61
62
OCPA0/PG0
OCPA1/PG1
OCPA2/PG2
OCPA3/PG3
OC0/PG4
OC1/PG5
OC2/PG6
OC3/PG7
D
[OCPA0 to 3] PPG timer outputs. The function is active when
PPG timer output is allowed.
[OC0 to 3] Output comparison output. The function is active
when output comparison output is allowed. [PB0-7] Available as
general input/output ports it is not used.
63
64
65
MD0
MD1
MD2
B
Mode terminals 0 through 2. The terminals specify basic operation mode of MCU.
Use the terminals by connecting them directly to VCC or VSS.
66
67
X0
X1
A
Clock (oscillation) input.
Clock (oscillation) output.
68
RST
C
External reset input.
69
HST
C
Hardware standby input.
70
P86/ALE
D
[ALE] Address latch signal output. The function is active when
ALE output of EPCR is allowed.
71
72
INT0/PE0
INT1/PE1
INT2/PE2
INT3/PE3
No.
Pin name
51
52
53
75
76
INT4/PE4/TCI1
INT5/PE5/SC0
D
[INT0,1,2,3] External interrupt request inputs. The input is used
whenever necessary if external interrupt is allowed. Output of
other functions must be suspended if not on purpose.
[PE0,1,2,3] General input/output port
D
[INT4,5] External interrupt request inputs.The input is used
whenever necessary if concerned external interrupt is allowed.
Output of other functions must be suspended if not on purpose.
[TCI1] External clock input of timer 1. [SC0] Clock input of
UART0.
[PE4,5] General input/output port
77
SI0/PE6
D
[SI0] Data input of UART0.This function is active when data input of UART0 is allowed.
[PE6]General input/output port
78
SO0/PE7
D
[SO0] Data output of UART0.This function is active when data
output of UART0 is allowed.
[PE7] General input/output port
(Continued)
7
MB91F127/F128
(Continued)
No.
Pin name
Input/output
circuit type
79
PF0/TCI0
D
80
SI2/PF1
D
Description
[TCI0] External clock input of timer 0.
[PF0] General input/output port
[SI2] Data input of UART2.This function is active when data input of UART2 is allowed.
[PF1] General input/output port
81
82
SO2/PF2
SC2/PF3/ATG
D
D
[SO2] Data output of UART2.This function is active when data
output of UART2 is allowed.
[PF2] General input/output port. This function is active when
data output of UART2 is disallowed.
[SC2] Clock input of UART2
[ATG]External trigger input of A/D converter The input is used
whenever necessary if a function concerned is selected.
Output of other functions must be suspended if not on purpose.
[PF3] General input/output port
AN0/PJ0
AN1/PJ1
AN2/PJ2
AN3/PJ3
AN4/PJ4
AN5/PJ5
AN6/PJ6
AN7/PJ7
E
91
AVCC
VCC power supply for A/D converter
92
AVRH
Reference voltage of A/D converter (high potential side). Be
sure to turn on or off this terminal with a potential higher than
AVRH applied to VCC.
93
AVSS/AVRL
A/D converter VSS power source and reference voltage (low potential side).
94 to 96
VCC
Power sources of digital circuits. Be sure to connect power
source to all terminals when the device is used.
97 to 100
VSS
Ground level of digital circuits.
83 to 90
[AN0 to AN7] Analog input of A/D converter.
This function is active when analog input is specified in AIC register.
[PJ0 through PJ7] General input/output ports
Note : Most of the above terminals multiplex inputs and outputs of I/O ports and resources, as indicated as “XXXX/
PXX”. If the outputs of ports and resources conflict with each other on the terminals, resources take preferences.
8
MB91F127/F128
■ INPUT/OUTPUT CIRCUIT TYPE
Type
Circuit
Remarks
Clock input
X1
A
• For 25 MHz system
• Oscillation feedback register :
Approx. 1MΩ
• Standby control is available.
X0
STANDBY
• CMOS level input
• High-voltage control is available for FLASH test.
B
Control
signal
Mode input
Diffused resistor
P-channel transistor
C
• CMOS level hysteresis input
• Standby control is not available.
N-channel transistor
Diffused
resistor
Digital input
CMOS
Digital output
D
Diffused
resistor
STANDBY
Digital output
Digital input
Digital output
E
Diffused
resistor
• CMOS level output
• CMOS level hysteresis input
• Standby control is available
•
•
•
•
Standby control is available
CMOS level output
CMOS level hysteresis input
Analog input
Digital output
Analog input
STANDBY
Digital input
9
MB91F127/F128
■ HANDLING DEVICES
1. Preventing latch up
On a CMOS IC, latch up may occur when a voltage higher than VCC or a voltage lower than VSS is applied to
input terminal or output terminal, or when a voltage exceeding rated level is applied across VCC and VSS. Latch
up causes drastic increase of power source current, which may result in destruction of the element by heat.
Take extra care not to exceed maximum rating in use. Also, take extra care so that analog terminal does not
exceed digital power source.
2. Treatment of unused input terminals
Leaving unused terminals open may cause malfunction. Apply pull-up or pull-down treatment on unused
terminals.
3. External reset input
Complete resetting of internal system requires inputting “L” level signal to RST terminal for a minimum of
5 machine cycles.
4. Notes on using external clock
When using an external clock, supply a clock signal to X0 terminal and supply its antiphase clock to X1 terminal
simultaneously. In this case, do not use STOP mode (oscillation stop mode). (Because X1 terminal halts with
"H" output under STOP status.)
Under a 12.5 MHz frequency, the device operates with a clock supplied to X0 terminal only.
Figures show examples of using an external clock.
Example of using external clock (normal)
X0
X1
Note : STOP mode (oscillation stop mode) is not available.
Example of using external clock (allowed under operation at 12.5 MHz or lower frequency)
X0
OPEN
10
X1
MB91F127/F128
5.
Connecting power supply terminals (VCC, VSS)
If two or more VCC, VSS terminals are used, the terminals to be placed under the same potentials are connected
with each other internally for preventing malfunctions such as latch up. However, for reducing unwanted radiation,
preventing malfunctions of strobe signals and observing total power and current ratings, be sure to connect all
of these terminals to power supply and ground externally.
Connecting power supply to VCC - VSS in impedance as low as possible is desirable.
6. Crystal oscillator circuit
Noises around X0 and X1 terminals causes malfunction of the device. Design printed wiring so that X0, X1,
and crystal oscillator (or ceramic oscillator), and bypass capacitor to the ground are aligned as close as possible
one another. Also the wiring of those elements should not cross with other wiring if possible. Printed wiring
with ground wires around X0 and X1 terminals ensures more stable operations. Such designing is strongly
recommended.
7. Treating NC terminals
Be sure to leave NC terminals open.
8. Mode terminals (MD0 through MD2)
Do not connect the mode terminals directly to VCC or VSS.
For preventing malfunctions caused by noises, make printed traces between the mode terminals and VCC or
VSS as short as possible, and connect the elements in lower impedance.
9. Turning power on
Be sure to turn on the power of the device with RST terminal placed under "L" level. Ensure a period at a
minimum of 5 cycles of internal operation clock before placing the terminal under "H" level.
10. Terminal status upon turning on power
Status upon turning on the power is indefinite. Upon turning on the power, oscillation starts and the circuit is
initialized.
11. Oscillation input upon turning on power
Upon turning on the power, be sure to input a clock signal until oscillation stabilizing wait status is released.
12. Initializing power-on reset
The device includes some built-in registers that are initialized only with power-on reset operation. For initializing
the registers, perform power-on reset by turning on the power again.
13. Recovery from Sleep/Stop status
For recovering from Sleep/Stop status initiated by a program in C-Bus RAM, reset the device instead of
recovering by an interrupt process.
11
MB91F127/F128
■ BLOCK DIAGRAM
Bit search module
I-bus (16 bits)
RAM (12 Kbytes)
D-bus (32 bits)
FR CPU
Bus converter
(Harvard - Princeton)
DMA controller
(8 ch.)
16
25
Bus converter (32 bits - 16 bits)
2
X0
X1
RST
HST
6
AN0 to AN7
AVCC
AVSS/AVRL
AVRH
ATG
8
10-bit
A/D converter
(8 ch.)
3
3
3
3
FRCK
Reload timer (3 ch)
4
OCPA0 to OCPA3
4
4
UART (3 ch)
6
ALE
R-bus (16 bits)
Interrupt control unit
SI0 to SI2
SO0 to SO2
SC0 to SC2
OC0 to OC3
IN0 to IN3
C-bus (32 bits)
Clock control unit
(Watchdog timer)
INT0 to
INT5
TCI0 to TCI2
Bus
controller
D16 to D31
A00 to A24
RD
WR0, WR1
RDY
CLK
BRQ
BGRNT
CS0 to CS5
Port2, 3, 4, 5, 6,
7, 8, A
RAM (2 Kbytes)
PPG
ICU, OCU
Free run timer
Flash memory
MB91F127:256 KB
MB91F128:510 KB
Port E, F, G, J
Notes : • Terminals are described in functional groups (actual terminals are partially multiplexed).
• For using REALOS, perform time management by external interrupt or built-in timer.
12
MB91F127/F128
■ CPU CORE MEMORY SPACE
• MB91F127
External ROM
External bus mode
Internal ROM
External bus mode
Single-chip mode
0000 0000H
I/O
I/O
I/O
I/O
I/O
I/O
Access inhibit
Access inhibit
Access inhibit
Internal RAM
12 KB
Internal RAM
12 KB
Internal RAM
12 KB
Access inhibit
Access inhibit
Access inhibit
0000 0400H
Direct
addressing
areas
I/O map
0000 0800H
0000 1000H
0000 4000H
0001 0000H
0001 0000H
External area
Access inhibit
Internal RAM
2 KB
Internal RAM
2 KB
0008 0000H
0008 0800H
External area
Access inhibit
Access inhibit
000C 0000H
FLASH ROM
256 KB
FLASH ROM
256 KB
0010 0000H
External area
FFFF FFFFH
Access inhibit
FFFF FFFFH
Note : External area is not accessible in single-chip mode. When accessing to external areas, select the internal
ROM external bus mode in mode register.
Direct addressing areas
The areas described below are used for I/O processes. The areas, referred to as “direct addressing areas,”
allow specifying an operand address directly by an instruction. The direct addressing areas varies as the
following, depending on size of the data to be accessed.
• Byte-data access : 0 to 0FFH
• Half-word data access : 0 to 1FFH
• Word-data access : 0 to 3FFH
13
MB91F127/F128
• MB91F128
External ROM
External bus mode
Internal ROM
External bus mode
Single-chip mode
0000 0000H
I/O
I/O
I/O
I/O
I/O
I/O
Access inhibit
Access inhibit
Access inhibit
Internal RAM
12 KB
Internal RAM
12 KB
Internal RAM
12 KB
Access inhibit
Access inhibit
Access inhibit
0000 0400H
Direct
addressing
areas
I/O map
0000 0800H
0000 1000H
0000 4000H
0001 0000H
0001 0000H
External area
Access inhibit
Internal RAM
2 KB
Internal RAM
2 KB
0008 0000H
0008 0800H
External area
FLASH ROM
510 KB
FLASH ROM
510 KB
0010 0000H
External area
FFFF FFFFH
Access inhibit
FFFF FFFFH
Note : External area is not accessible in single-chip mode. When accessing to external areas, select the internal
ROM external bus mode in mode register.
Direct addressing areas
The areas described below are used for I/O processes. The areas, referred to as “direct addressing areas,”
allow specifying an operand address directly by an instruction. The direct addressing areas varies as the
following, depending on size of the data to be accessed.
• Byte-data access : 0 to 0FFH
• Half-word data access : 0 to 1FFH
• Word-data access : 0 to 3FFH
14
MB91F127/F128
■ LEGEND OF I/O MAP
address
000000H
Register
+0
+1
+2
+3
PDR3 [R/W]
XXXXXXXX
PDR2 [R/W]
XXXXXXXX
--------
--------
Internal resource
Port Data Register
Read/write attribute
Initial register value after reset
Register name (the register listed in the first column is at address 4n, the register listed in
the second column is at address 4n + 1, - - - )
Leftmost register address (the first column register is on the MSB side of data in word access mode)
Note : Register bit values indicate initial values as shown below :
“1” : Initial value“1”
“0” : Initial value“0”
“X” : Initial value “X”
“-” : Register does not exist physically in this position.
15
MB91F127/F128
■ I/O MAP
Address
Register
+0
+1
+2
+3
000000H
PDR3 [R/W]
XXXXXXXX
PDR2 [R/W]
XXXXXXXX
000004H
PDR7 [R/W]
-------X
PDR6 [R/W]
XXXXXXXX
PDR5 [R/W]
XXXXXXXX
PDR4 [R/W]
XXXXXXXX
000008H
PDRA [R/W]
XXXXXXXX
PDR8[R/W]
- - XXXXXX
Internal resource
Port data Register
00000CH
000010H
PDRE [R/W]
XXXXXXXX
PDRF [R/W]
XXXXXXXX
000014H
PDRG [R/W]
XXXXXXXX
PDRJ [R/W]
XXXXXXXX
000018H
Reserved
00001CH
SSR [R/W]
00001- 00
SIDR [R/W]
XXXXXXXX
SCR [R/W]
00000100
SMR [R/W]
00 - - 0 - 00
UART0
000020H
SSR [R/W]
00001- 00
SIDR [R/W]
XXXXXXXX
SCR [R/W]
00000100
SMR [R/W]
00 - - 0 - 00
UART1
000024H
SSR [R/W]
00001- 00
SIDR [R/W]
XXXXXXXX
SCR [R/W]
00000100
SMR [R/W]
00 - - 0 - 00
UART2
000028H
TMRLR [W]
XXXXXXXX XXXXXXXX
TMR [W]
XXXXXXXX XXXXXXXX
00002CH
TMCSR [R/W]
- - - - 0000 00000000
000030H
TMRLR [W]
XXXXXXXX XXXXXXXX
TMR [W]
XXXXXXXX XXXXXXXX
000034H
TMCSR [R/W]
- - - - 0000 00000000
000038H
00003CH
TMRLR [W]
XXXXXXXX XXXXXXXX
TMR [W]
XXXXXXXX XXXXXXXX
000040H
TMCSR [R/W]
- - - - 0000 00000000
000044H
IPCP1[R]
XXXXXXXX XXXXXXXX
IPCP0[R]
XXXXXXXX XXXXXXXX
000048H
IPCP3[R]
XXXXXXXX XXXXXXXX
IPCP2[R]
XXXXXXXX XXXXXXXX
00004CH
000050H
ICS23[R/W]
00000000
ADCR [W]
00101-XX XXXXXXXX
Reload Timer 0
Reload Timer 1
Reserved
Reload Timer 2
16 bit ICU
ICS01[R/W]
00000000
ADCS [R/W]
000000000 00000000
A/D converter
(Serially compared)
(Continued)
16
MB91F127/F128
Address
Register
+0
+1
+2
+3
Internal resource
000054H
OCCP1[R/W]
XXXXXXXX XXXXXXXX
OCCP0[R/W]
XXXXXXXX XXXXXXXX
000058H
OCCP3[R/W]
XXXXXXXX XXXXXXXX
OCCP2[R/W]
XXXXXXXX XXXXXXXX
00005CH
000060H
000064H
OCS2, 3[R/W]
XXX00000 0000XX00
OCS0, 1[R/W]
XXX00000 0000XX00
16 bit OCU
000068H
Reserved
00006CH
TCDT [R/W]
00000000 00000000
TCCS [R/W]
0 - - - - - - - 00000000
Free run timer
000070H
Reserved
000074H
Reserved
000078H
UTM/UTIMR [R/W]
00000000 00000000
UTIMC[R/W]
0 - - 00001
U-Timer0
00007CH
UTM/UTIMR [R/W]
00000000 00000000
UTIMC[R/W]
0 - - 00001
U-Timer1
000080H
UTM/UTIMR [R/W]
00000000 00000000
UTIMC[R/W]
0 - - 00001
U-Timer2
000084H
000088H
00008CH
000090H
000094H
EIRR [R/W]
00000000
ENIR [R/W]
00000000
000098H
EHVR [R/W]
- - - - 0000
ELVR [R/W]
00000000
16 bit OCU
Reserved
Reserved
Reserved
External interrupt/
NMI
(Continued)
17
MB91F127/F128
Address
Register
+0
+1
+2
00009CH
0000A0H
0000A4H
0000A8H
0000ACH
0000B0H
0000B4H
0000B8H
0000BCH
0000C0H
0000C4H
0000C8H
0000CCH
+3
Internal resource
Reserved
0000D0H
DDRE [W]
00000000
DDRF [W]
00000000
Port direction
register
0000D4H
AIC3[W]
11111111
A/D converter
0000D8H
DDRG [W]
00000000
DDRJ [W]
00000000
Port direction register
--------
GCN2[R/W]
00000000
PPG ctl
0000DCH
GCN1 [R/W]
00110010 00010000
0000E0H
PTMR0 [R]
11111111 11111111
0000E4H
PDUT0 [W]
XXXXXXXX XXXXXXXX
0000E8H
PTMR1 [R]
11111111 11111111
0000ECH
PDUT1 [W]
XXXXXXXX XXXXXXXX
0000F0H
PTMR2 [R]
11111111 11111111
0000F4H
PDUT2 [W]
XXXXXXXX XXXXXXXX
0000F8H
PTMR3 [R]
11111111 11111111
0000FCH
PDUT3 [W]
XXXXXXXX XXXXXXXX
PCSR0 [W]
XXXXXXXX XXXXXXXX
PCNH0[R/W]
0000000 -
PCNL0[R/W]
00000000
PCSR1 [W]
XXXXXXXX XXXXXXXX
PCNH1[R/W]
0000000 -
PCNL1[R/W]
00000000
PCSR2 [W]
XXXXXXXX XXXXXXXX
PCNH2[R/W]
0000000 -
PCNL2[R/W]
00000000
PCSR3 [W]
XXXXXXXX XXXXXXXX
PCNH3[R/W]
0000000 -
PCNL3[R/W]
00000000
PPG0
PPG1
PPG2
PPG3
(Continued)
18
MB91F127/F128
Address
Register
+0
+1
+2
+3
Internal resource
000100H
to
0001FCH
000200H
DPDP
[R/W]
- - - - - - - - - - - - - - - - - - - - - - - - -0000000
000204H
DACSR
[R/W]
00000000 00000000 00000000 00000000
000208H
DATCR
[R/W]
- - - - - - - - - - XX0000 - - XX0000 - - XX0000
00020CH
000210H
to
0002FCH
Reserved
000300H
to
0003ECH
Reserved
0003F0H
BSD0
[W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F4 H
BSD1
[R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F8H
BSDC
[W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003FCH
BSRR
[R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reserved
DMAC
Bit search module
(Continued)
19
MB91F127/F128
Address
Register
+0
+1
+2
+3
000400H
ICR00 [R/W]
- - -11111
ICR01[R/W]
- - -11111
ICR02[R/W]
- - -11111
ICR03[R/W]
- - -11111
000404H
ICR04[R/W]
- - -11111
ICR05[R/W]
- - -11111
ICR06[R/W]
- - -11111
ICR07[R/W]
- - -11111
000408H
ICR08 [R/W]
- - -11111
ICR09[R/W]
- - -11111
ICR10[R/W]
- - -11111
ICR11[R/W]
- - -11111
00040CH
ICR12[R/W]
- - -11111
ICR13[R/W]
- - -11111
ICR14[R/W]
- - -11111
ICR15[R/W]
- - -11111
000410H
ICR16[R/W]
- - -11111
ICR17[R/W]
- - -11111
ICR18[R/W]
- - -11111
ICR19[R/W]
- - -11111
000414H
ICR20[R/W]
- - -11111
ICR21[R/W]
- - -11111
ICR22[R/W]
- - -11111
ICR23[R/W]
- - -11111
000418H
ICR24 [R/W]
- - -11111
ICR25[R/W]
- - -11111
ICR26[R/W]
- - -11111
ICR27[R/W]
- - -11111
00041CH
ICR28[R/W]
- - -11111
ICR29[R/W]
- - -11111
ICR30[R/W]
- - -11111
ICR31[R/W]
- - -11111
000420H
ICR32[R/W]
- - -11111
ICR33[R/W]
- - -11111
ICR34[R/W]
- - -11111
ICR35[R/W]
- - -11111
000424H
ICR36[R/W]
- - -11111
ICR37[R/W]
- - -11111
ICR38[R/W]
- - -11111
ICR39[R/W]
- - -11111
000428H
ICR40[R/W]
- - -11111
ICR41[R/W]
- - -11111
ICR42[R/W]
- - -11111
ICR43[R/W]
- - -11111
00042CH
ICR44[R/W]
- - -11111
ICR45[R/W]
- - -11111
ICR46[R/W]
- - -11111
ICR47[R/W]
- - -11111
000430H
DICR [R/W]
-------0
HRCL [R/W]
- - -11111
000434H
to
00047CH
RSRR/WTCR
[R/W]
1XXXX - 00
STCR [R/W]
000111- -
PDDR [R/W]
- - - - 0000
CTBR [W]
XXXXXXXX
000484H
GCR [R/W]
110011 - 1
WPR [W]
XXXXXXXX
000488H
PTCR [R/W]
00 - - 0 - - -
Interrupt controller
Delay interrupt
Reserved
000480H
00048CH
to
0005FCH
Internal resource
Clock controller
block
PLL controller
block
Reserved
(Continued)
20
MB91F127/F128
(Continued)
Address
Register
+0
+1
+2
+3
000600H
DDR3 [W]
00000000
DDR2 [W]
00000000
000604H
DDR7 [W]
-------0
DDR6 [W]
00000000
DDR5 [W]
00000000
DDR4 [W]
00000000
000608H
DDRA [W]
-0000000
DDR8 [W]
- - 000000
00060CH
ASR1 [W]
00000000 00000001
AMR1 [W]
00000000 00000000
000610H
ASR2 [W]
00000000 00000010
AMR2 [W]
00000000 00000000
000614H
ASR3 [W]
00000000 00000011
AMR3 [W]
00000000 00000000
000618H
ASR4 [W]
00000000 00000100
AMR4 [W]
00000000 00000000
00061CH
ASR5 [W]
00000000 00000101
AMR5 [W]
00000000 00000000
000620H
AMD0 [R/W]
- - - XX111
AMD1 [R/W]
0 - - 00000
000624H
AMD5[R/W]
0 - - 00000
DSCR [W]
00000000
AMD32[R/W]
00000000
EPCR1 [W]
- - - - - - - 1 11111111
00062CH
DMCR4 [R/W]
00000000 0000000-
DMCR5 [R/W]
00000000 0000000
FSTR [R/W]
000XXXX0
0007C4H
to
0007F8H
0007FCH
Reserved
External bus interface
RFCR [R/W]
--XXXXXX 00 - - - 000
EPCR0 [W]
- - 1 - 1100 -1111111
0007C0H
Data direction register
AMD4 [R/W]
0 - - 00000
000628H
000630H
to
0007BCH
Internal resource
Flash memory
Reserved
LER [W]
- - - - - 000
MODR [W]
XXXXXXXX
Little endian register mode register
Note : Do not issue RMW instructions to a register with write-only bit.
RMW instructions (RMW : Read modify write)
AND Rj, @Ri
OR Rj, @Ri
EOR Rj, @Ri
ANDH Rj, @Ri
ORH Rj, @Ri
EORH Rj, @Ri
ANDB Rj, @Ri
ORB Rj, @Ri
EORB Rj, @Ri
BANDL #u4, @Ri BORL #u4, @Ri BEORL #u4, @Ri
BANDH #u4, @Ri BORH #u4, @Ri BEORH #u4, @Ri
Data in “Reserved” or “-” area is indefinite.
21
MB91F127/F128
■ INTERRUPT CAUSES, INTERRUPT VECTORS AND INTERRUPT CONTROL REGISTER ALLOCATIONS
Interrupt causes
Interrupt number
Decimal
Interrupt level
Hexadecimal Register*1
Offset
TBR default
Address*2
Reset
0
00
3FCH
000FFFFCH
Reserved by system
1
01
3F8H
000FFFF8H
Reserved by system
2
02
3F4H
000FFFF4H
Reserved by system
3
03
3F0H
000FFFF0H
Reserved by system
4
04
3ECH
000FFFECH
Reserved by system
5
05
3E8H
000FFFE8H
Reserved by system
6
06
3E4H
000FFFE4H
Reserved by system
7
07
3E0H
000FFFE0H
Reserved by system
8
08
3DCH
000FFFDCH
Reserved by system
9
09
3D8H
000FFFD8H
Reserved by system
10
0A
3D4H
000FFFD4H
Reserved by system
11
0B
3D0H
000FFFD0H
Reserved by system
12
0C
3CCH
000FFFCCH
Reserved by system
13
0D
3C8H
000FFFC8H
Undefined instruction exception
14
0E
3C4H
000FFFC4H
NMI request
15
0F
15 (FH)
fixed
3C0H
000FFFC0H
External interrupt 0
16
10
ICR00
3BCH
000FFFBCH
External interrupt 1
17
11
ICR01
3B8H
000FFFB8H
External interrupt 2
18
12
ICR02
3B4H
000FFFB4H
External interrupt 3
19
13
ICR03
3B0H
000FFFB0H
UART 0 reception complete
20
14
ICR04
3ACH
000FFFACH
UART 1 reception complete
21
15
ICR05
3A8H
000FFFA8H
UART 2 reception complete
22
16
ICR06
3A4H
000FFFA4H
UART 0 transmission complete
23
17
ICR07
3A0H
000FFFA0H
UART 1 transmission complete
24
18
ICR08
39CH
000FFF9CH
UART 2 transmission complete
25
19
ICR09
398H
000FFF98H
(Continued)
22
MB91F127/F128
Interrupt number
Interrupt level
Decimal
Hexadecimal
Register*1
Offset
TBR default
Address*2
DMAC 0 (end, error)
26
1A
ICR10
394H
000FFF94H
DMAC 1 (end, erro)
27
1B
ICR11
390H
000FFF90H
DMAC 2 (end, erro)
28
1C
ICR12
38CH
000FFF8CH
DMAC 3 (end, erro)
29
1D
ICR13
388H
000FFF88H
DMAC 4 (end, erro)
30
1E
ICR14
384H
000FFF84H
DMAC 5 (end, erro)
31
1F
ICR15
380H
000FFF80H
DMAC 6 (end, erro)
32
20
ICR16
37CH
000FFF7CH
DMAC 7 (end, erro)
33
21
ICR17
378H
000FFF78H
A/D (sequential type)
34
22
ICR18
374H
000FFF74H
Reload timer 0
35
23
ICR19
370H
000FFF70H
Reload timer 1
36
24
ICR20
36CH
000FFF6CH
Reload timer 2
37
25
ICR21
368H
000FFF68H
External interrupt 4
38
26
ICR22
364H
000FFF64H
External interrupt 5
39
27
ICR23
360H
000FFF60H
Reserved by system
40
28
ICR24
35CH
000FFF5CH
Reserved by system
41
29
ICR25
358H
000FFF58H
U-TIMER 0
42
2A
ICR26
354H
000FFF54H
U-TIMER 1
43
2B
ICR27
350H
000FFF50H
U-TIMER 2
44
2C
ICR28
34CH
000FFF4CH
FLASH memory
45
2D
ICR29
348H
000FFF48H
Reserved by system
46
2E
ICR30
344H
000FFF44H
Reserved by system
47
2F
ICR31
340H
000FFF40H
PPG0
48
30
ICR32
33CH
000FFF3CH
PPG1
49
31
ICR33
338H
000FFF38H
PPG2
50
32
ICR34
334H
000FFF34H
PPG3
51
33
ICR35
330H
000FFF30H
ICU0 (capture)
52
34
ICR36
32CH
000FFF2CH
ICU1 (capture)
53
35
ICR37
328H
000FFF28H
ICU2 (capture)
54
36
ICR38
324H
000FFF24H
ICU3 (capture)
55
37
ICR39
320H
000FFF20H
Interrupt causes
(Continued)
23
MB91F127/F128
(Continued)
Interrupt causes
Interrupt number
Decimal
Interrupt level
Hexadecimal Register*1
Offset
TBR default
Address*2
OCU0 (match)
56
38
ICR40
31CH
000FFF1CH
OCU1 (match)
57
39
ICR41
318H
000FFF18H
OCU2 (match)
58
3A
ICR42
314H
000FFF14H
OCU3 (match)
59
3B
ICR43
310H
000FFF10H
Reserved by system
60
3C
ICR44
30CH
000FFF0CH
16 bit free-run timer
61
3D
ICR45
308H
000FFF08H
Reserved by system
62
3E
ICR46
304H
000FFF04H
Delay interrupt cause bit
63
3F
ICR47
300H
000FFF00H
Reserved by system
(used by REALOS) *3
64
40
2FCH
000FFEFCH
Reserved by system
(used by REALOS) *3
65
41
2F8H
000FFEF8H
Used by INT
66
to
255
42
to
FF
2F4H
to
000H
000FFEF4H
to
000FFC00H
*1 : ICR specifies interrupt levels for interrupt requests, using the registers in interrupt controller.
ICR is provided for each interrupt request.
*2 : TBR is a register that indicates a head address of the vector table for EIT.
An address that is found by adding offset values defined by TBR and EIT cause, is a vector address.
*3 : If REALOS/FR is used, 0x40 and 0x41 interrupts are used for system code.
Information : An 1 Kbyte area starting with an address indicated by TBR is the vector area for EIT. Size of the area
for one vector is 4 byte. Relation between a vector number and a vector address is as follows:
vctadr = TBR + vctofs
= TBR + ( 3FCH − 4 × vct)
Vctadr Vector address, vctofs: Vector offset, vct: Vector number
24
MB91F127/F128
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
(VSS = AVSS = 0 V)
Symbol
Rating
Min
Max
Unit
Remarks
Power supply voltage
VCC
VSS − 0.3
VSS + 4.0
V
Analog supply voltage
AVCC
VSS − 0.3
VSS + 4.0
V
*1
Analog reference voltage
AVRH
VSS − 0.3
VSS + 4.0
V
*1
Input voltage
VI
VSS − 0.3
VCC + 0.3
V
Analog input voltage
VIA
VSS − 0.3
AVCC + 0.3
V
Output voltage
VO
VSS − 0.3
VCC + 0.3
V
ICLAMP
− 2.0
+ 2.0
mA
*5
Σ | ICLAMP |
20
mA
*5
IOL
10
mA
*2
“L” level average output current
IOLAV
4
mA
*3
“L” level maximum total output current
ΣIOL
100
mA
“L” level average total output current
ΣIOLAV
50
mA
*4
“H” level maximum output current
IOH
−10
mA
*2
“H” level average output current
IOHAV
−4
mA
*3
“H” level maximum total output current
ΣIOH
−50
mA
“H” level average total output current
ΣIOHAV
−20
mA
Power consumption
Pd
500
mW
Operating temperature
TA
−30
+70
°C
Tstg
−55
+150
°C
Maximum clamp current
Total maximum clamp current
“L” level maximum output current
Storage temperature
*4
*1 : Care must be taken that AVCC, AVRH do not exceed VCC + 0.3 V. Also, care must be taken that AVRH do not
exceed AVCC.
*2 : Maximum output current defines a peak value of a specific terminal.
*3 : Average output current defines a mean value of current flow within a period of 100 ms in a specific terminal.
*4 : Average total output current defines a mean value of current flow within a period of 100 ms in all terminals.
*5 : • Aplicable to pins : D16 to D31, A00 to A24, RDY, BGRNT, BRQ, RD, WR0, WR1, CS0 to CS5, CLK, OCPA0
to OCPA3, OC0 to OC3, ALE, INT0 to INT5, SI0, SI2, SO0, SO2, TCI0, SC2
• Use within recommended operating conditions.
• Use at DC voltage (current) .
• The +B signal should always be applied with a limiting resistance placed between the +B signal and the
microcontroller.
(Continued)
25
MB91F127/F128
(Continued)
• The value of the limiting resistance should be set so that when the signal is applied the input current to the
microcontroller pins does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is
provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power suplly is provided from the pins and the resulting
supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the input pin open.
• Sample recommended circuits
• Input/Output equivalent circuits
Protective diode
VCC
P-ch
Limiting
resistance
+B input (0 V to 16 V)
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
26
MB91F127/F128
2. Recommended Operating Conditions
Parameter
Symbol
Power supply
VCC
Analog supply voltage
Analog reference voltage
Operating temperature
(VSS = AVSS = 0 V)
Value
Min
Max
3.0
3.6
Unit
Remarks
Normal operation
V
2.0
3.6
AvCC
VSS − 0.3
VSS + 3.6
V
AVRH
AVSS
AVCC
V
TA
−30
+70
°C
Retain RAM data
under “stop” condition
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
27
MB91F127/F128
3. DC Characteristics
Parameter
Symbol
(AVCC = VCC = 3.3 V ± 0.3 V, AVSS = VSS = 0 V, TA = −30 °C to +70 °C)
Pin name
Condition
Min
Typ
Max
Unit Remarks
“H” level input
voltage
VIHS
Hysteresis
input terminal
0.8 × VCC
VCC + 0.3
V
*
“L” level input
voltage
VILS
Hysteresis
input terminal
VSS−0.3
0.2 × VCC
V
*
“H” level output
voltage
VOH
Port2 to PortJ
VCC = 3.3 V
IOH = −4.0 mA
VCC−0.5
V
“L” level output
voltage
VOL
Port2 to PortJ
VCC = 3.3 V
IOL = 4.0 mA
0.4
V
ILI
Port2 to PortJ
VCC = 3.6 V
VSS < VI < VCC
±5
µA
ICC
25 MHz
VCC = 3.3 V
75
100
mA
ICC
25 MHz
VCC = 3.3 V
85
120
mA
FLASH
writing
ICCS
25 MHz
VCC = 3.3 V
60
85
mA
Sleeping
ICCH
TA = 25 °C
VCC = 3.3 V
10
150
µA
Stopping
10
pF
Input leak
current
Power supply
current
Input capacity
VCC
CIN
Other than
AVCC, AVSS,
AVRH, VCC,
VSS
* : Refer to “■ INPUT/OUTPUT CIRCUIT TYPE”.
28
Value
MB91F127/F128
4. AC Characteristics
(1) Clock Timing Ratings
Parameter
(VCC = 3.3 V ± 0.3 V, AVSS = VSS = 0 V, TA = −30 °C to +70 °C)
Symbol
Condition
Clock frequency
(High speed, automatic oscillation)
Clock frequency
(High speed, PLL used)
fC
Value
Unit
Max
10
25
MHz
Self oscillation allowable
range
10
25
MHz
PLL-use allowable area for
self oscillation and external
clock input
*1
10
25
MHz
External clock input
allowable range
Clock frequency
(High speed, 1/2 division input)
Clock cycle time
tC
40
100
ns
Frequency regulation
(when locked)
∆f
10
%
Input clock pulse width
Input clock rise and fall time
CPU
Internal operation system
clock frequency
Peripheral
system
CPU
Internal operation system
clock cycle time
Peripheral
system
Remarks
Min
PWH, PWL
9.5
ns
tCR
tCF
8
ns
fCP
0.625 *3
25
MHz
fCPP
0.625 *3
25
MHz
tCP
40
1600 *3
ns
tLCPP
40
1600 *3
ns
*2
(tCR + tCF)
*1 : Although PLL allows selection among x1 and x2 multiplication modes, the selection is limited by oscillation
frequency as follows:
Specifying "x2 multiplication" is not allowed if oscillation frequency exceeds 12.5 MHz.
*2 : Frequency regulation indicates a maximum fluctuation from a specified center frequency under locked frequency
multiplication.
∆f =
α
fO
+α
× 100 (%)
fO
−α
29
MB91F127/F128
*3 : This is a value in the case where 10 MHz signal, a minimum value of clock frequency, is input to X0 and where
1/2-division in oscillation circuit and 1/8-gear are used.
tC
0.8 VCC
0.2 VCC
PWH
PWL
tcr
tcf
Source voltage (V)
Operation-guaranteed area
(TA = −30 °C to +70 °C)
3.6
3.0
25
Frequency (MHz)
30
MB91F127/F128
(2) Clock Output Timing
Parameter
(VCC = 3.3 V ± 0.3 V, AVSS = VSS = 0 V, TA = −30 °C to +70 °C)
Symbol
Pin name
Cycle time
tCYC
CLK
CLK↑ →CLK↓
tCHCL
CLK
CLK↓ →CLK↑
tCLCH
CLK
Value
Condition
Min
Max
tCP
Unit
Remarks
ns
*1
1 / 2 × tCYC − 10 1 / 2 × tCYC + 10
ns
*2
1 / 2 × tCYC − 10 1 / 2 × tCYC + 10
ns
*3
*1 : tCYC is a frequency of 1 clock cycle indicating gear cycle.
*2 : The values indicate specifications where x1 gear cycle is used.
If gear cycle of 1/2, 1/4, or 1/8 is specified, calculate in the formula below by substituting 1/2, 1/4, or 1/8 into n.
Min : (1 − n / 2) × tCYC − 10
Max : (1 − n / 2) × tCYC + 10
*3 : The values indicate specifications where x1 gear cycle is used.
If gear cycle of 1/2, 1/4, or 1/8 is specified, calculate in the formula below by substituting 1/2, 1/4, or 1/8 into n.
Min : n / 2 × tCYC − 10
Max : n / 2 × tCYC + 10
Clock output timing
tCYC
tCHCL
tcLCH
VOH
CLK
VOL
(3) Reset Input Ratings
Parameter
Reset input time
VOH
(VCC = 3.3 V ± 0.3 V, AVSS = VSS = 0 V, TA = −30 °C to +70 °C)
Symbol
Pin name
Condition
tRSTL
RST
Value
Min
Max
tCP × 5
Unit
Remarks
ns
tRSTL
RST
0.2 VCC
31
MB91F127/F128
(4) Power-on Reset
(VCC = 3.3 V ± 0.3 V, VSS = 0 V, TA = −30 °C to +70 °C)
Symbol
Pin
name
Condition
Power supply rise
time
tR
VCC
Power supply shut
off time
tOFF
Oscillation stabilizing wait time
tOSC
Parameter
Value
Unit
Remarks
20
ms
VCC < 0.2 V
before turning on
power
2
ms
2 × tC × 221
+ 100 µs
ns
Min
Max
VCC = 3.3 V
VCC
tR
0.9 VCC
VCC
0.2 V
tOFF
A sudden change of supply voltage may activate the power-on reset function. It is recommended that
power voltage should be changed smoothly with less fluctuation of voltages.
3.3 V
VCC
2.0 V
Retaining RAM data
The rising slope is recommended
to be less than 50 mV / ms.
VSS
VCC
tOSC
RST
tRSTL
32
Be sure to turn on the power while keeping
RST terminal at L level first. When the power
becomes VCC level, rise the voltage to H level
after a period of tRSTL.
MB91F127/F128
(5) Normal Bus Access Read/Write Operation
Parameter
Symbol
Pin name
(VCC = 3.3 V ± 0.3 V, VSS = 0 V, TA = −30 °C to +70 °C)
Condition
Value
Unit
Min
Max
15
ns
15
ns
Remarks
CS0 to CS5 delay
time
tCHCSL
CS0 to CS5 delay
time
tCHCSH
Address delay time
tCHAV
CLK
A24 to A00
15
ns
Data delay time
tCHDV
CLK
D31 to D16
15
ns
RD delay time
tCLRL
15
ns
RD delay time
tCLRH
15
ns
WR0, 1 delay time
tCLWL
15
ns
WR0, 1 delay time
tCLWH
15
ns
Valid address→
Valid data input time
tAVDV
3 / 2 × tcyc − 25
ns
*1
*2
RD↓→
Valid data input time
tRLDV
tcyc − 25
ns
*1
Data setup
→RD↑ Time
tDSRH
25
ns
RD↑→
Data hold time
tRHDX
0
ns
CLK
CS0 to CS5
CLK
RD
CLK
WR0, 1
A24 to A00
D31 to D16
RD
D31 to D16
*1 : If the bus is expanded by automatic wait insertion or RDY input, add time (tcyc × the number of expanded
cycles) to the rated value.
*2 : The ratings are based on conditions with “gear cycle × 1”. If gear cycle of 1/2, 1/4, or 1/8 is specified, calculate
in the formula below by substituting 1/2, 1/4, or 1/8 into n.
Formula : (2 − n / 2) × tCYC − 25
33
MB91F127/F128
tCYC
2.4 V
CLK
2.4 V
2.4 V
0.8 V
0.8 V
tCHCSH
tCHCSL
2.4 V
CS0 ~ CS5
0.8 V
tCHAV
A24 ~ A00
2.4 V
2.4 V
0.8 V
0.8 V
tCLRH
tCLRL
2.4 V
RD
tRLDV
tAVDV
2.4 V
D31 ~ D16
CLK
tRHDX
tDSRH
Read
0.8 V
2.4 V
0.8 V
0.8 V
tCLWH
tCLWL
WR
2.4 V
(WR0 ~ WR1)
A24 ~ A00
2.4 V
2.4 V
0.8 V
0.8 V
tCHDV
2.4 V
D31 ~ D16
34
0.8 V
write data
2.4 V
0.8 V
MB91F127/F128
(6) Timeshared Bus Access Read/Write Operations
Parameter
Symbol
Pin name
ALE delay time
tCLLH2
ALE delay time
tCLLL2
CLK
ALE
CS1 delay time
tCHCSL2
CS1 delay time
tCHCSH2
Address delay time
tCHAV2
Data delay time
tCHDV2
RD delay time
tCLRL2
RD delay time
tCLRH2
WR0, 1 delay time
tCLWL2
WR0, 1 pulse width
tCLWH2
RD↓→
Valid data input time
tRLDV2
Data setup
→RD↑time
tDSRH2
RD↑→
Data hold time
tRHDX2
(VCC = 3.3 V ± 0.3 V, VSS = 0 V, TA = −30 °C to +70 °C)
Condition
CLK
CS1
CLK
D31 to D16
CLK
RD
CLK
WR0
WR1
Value
Max
10
10
15
15
ns
15
ns
15
ns
10
ns
10
ns
10
ns
10
ns
RD
D31 to D16
Unit
Min
tCYC − 25
25
ns
0
ns
Remarks
*
* : If the bus is expanded by automatic wait insertion or RDY input, add time (tcyc x the number of expanded cycles)
to the rated value.
35
MB91F127/F128
tCYC
MA1
CLK
2.4 V
MA1
2.4 V
0.8 V
BA1
2.4 V
2.4 V
0.8 V
0.8 V
0.8 V
tCLLL2
tCLLH2
2.4 V
ALE
BA1
0.8 V
tCHCSH2
tCHCSL2
CS1
D31-D16
Multiplex bus
for reading
2.4 V
0.8 V
2.4 V
0.8 V
Address
2.4 V
0.8 V
2.4 V
0.8 V
tCHAV2
0.8 V
2.4 V
0.8 V
Address
2.4 V
0.8 V
tCLRH2
Write
tCHDV2
2.4 V
WR0 - WR1
0.8 V
tCLWL2
36
Read
2.4 V
tCLRL2
A15-A08
for
non-multi
2.4 V
0.8 V
tRHDX2
tCHAV2
RD
D31-D16
Multiplex bus
for writing
tDSRH2
tRLDV2
2.4 V
0.8 V
tCHAV2
tCLWH2
MB91F127/F128
(7) Ready Input Timing
Parameter
(VCC = 3.3 V ± 0.3 V, AVSS = VSS = 0 V, TA = −30 °C to +70 °C)
Symbol
Pin name
RDY setup time
RCLK↓
tRDYS
RDY
CLK
CLK↓→
RDY hold time
tRDYH
CLK
RDY
Condition
Value
Unit
Min
Max
15
ns
0
ns
Remarks
tCYC
2.4 V
CLK
tRDYS
RDY
With
waiting
2.4 V
0.8 V
0.8 V
0.8 V
tRDYH
tRDYS tRDYH
2.4 V
RDY
2.4 V
Without
waiting
0.8 V
37
MB91F127/F128
(8) Hold Timing
(VCC = 3.0 V ± 0.3 V, AVSS = VSS = 0 V, TA = −30 °C to +70 °C)
Parameter
Symbol
Pin name
BGRNT delay time
tCHBGL
BGRNT delay time
tCHBGH
CLK
BGRNT
Terminal floating
→BGRNT↓ time
tXHAL
BGRNT↑
→Terminal valid time
tHAHV
Value
Condition
Unit
Min
Max
10
ns
10
ns
tCYC − 10
tCYC + 10
ns
tCYC − 10
tCYC + 10
ns
BGRNT
Note : More than one cycle is required for BGRNT to change after BRQ is input.
tCYC
2.4 V
2.4 V
2.4 V
2.4 V
CLK
BRQ
tCHBGL
2.4 V
BGRNT
0.8 V
tHAHV
tXHAL
Each pin
High-Z
38
tCHBGH
Remarks
MB91F127/F128
(9) UART Timing
(VCC = 3.3 V ± 0.3 V, VSS = 0 V, TA = −30 °C to +70 °C)
Parameter
Symbol Pin name
Condition
Value
Unit
Min
Max
8 tCYCP*
ns
−10
+50
ns
50
ns
Serial clock cycle time
tSCYC
SC↓ → SO delay time
tSLOV
Valid SI → SC↑
tIVSH
SC↑ → Valid SI hold time
tSHIX
50
ns
Serial clock “H” pulse width
tSHSL
4 tCYCP* − 10
ns
Serial clock “L” pulse width
tSLSH
4 tCYCP* − 10
ns
SC↓ → SO delay time
tSLOV
0
50
ns
Valid SI → SC↑
tIVSH
50
ns
SC↑ → Valid SI hold time
tSHIX
50
ns
Serial busy time
tBUSY
6 tCYCP*
ns
CS↓ → SC, SO delay time
tCLZO
50
ns
CS↓ → SC input mask time
tCLSL
3 tCYCP*
ns
SC↑ → SC, SO Hi-z time
tCHOZ
50
ns
Internal shift
clock mode
External shift
clock mode
Remarks
* : tCYCP is a cycle time of peripheral system clock.
Internal shift clock mode
tSCYC
SC
tSLOV
SO
SI
tSHIX
tIVSH
External shift clock mode
tCLZO
tSLSH
tSHSL
tBUSY
tCHOZ
SC
tSLOV
SO
SI
tIVSH
tSHIX
CS
tCLSL
39
MB91F127/F128
(10) Trigger Input Timing
Parameter
Input pulse width
(VCC = 3.3 V ± 0.3 V, VSS = 0 V, TA = −30 °C to +70 °C)
Symbol
Pin name
Condition
tTRGH
tTRGL
ATG,
INT0, 1, 2, 3
INT4, 5
Value
Min
Max
5 tCYCP*
* : tCYCP is a cycle time of peripheral system clock.
ATG
INT0, 1, 2, 3
INT4, 5
40
tTRGH
tTRGL
Unit
ns
Remarks
MB91F127/F128
(11) A/D Converter Block Electrical Characteristics
(VCC = 3.3 V ± 0.3 V, AVSS = VSS = 0 V, TA = −30 °C to +70 °C)
Parameter
Symbol
Pin name
Resolution
Total error
Value
Unit
Min
Typ
Max
10
10
BIT
±4.0
LSB
Linearity error
±3.5
LSB
Differential linearity error
±2.0
LSB
Zero transition voltage
V0t
AN0 to AN7
AVSS
− 1.5 LSB
AVSS
+ 0.5 LSB
AVSS
+ 2.5 LSB
mV
VFST
AN0 to AN7
AVRH
− 5.5 LSB
AVRH
− 1.5 LSB
AVRH
+ 0.5 LSB
mV
Conversion time
5.3
µs
Analog input current
IAIN
AN0 to AN7
0.1
10
µA
Analog input voltage
VAIN
AN0 to AN7
AVSS
AVRH
V
AVRH
AVSS
AVCC
V
3.0
5.0
mA
5.0
µA
100
150
µA
10
µA
4
LSB
Full-scale transition voltage
Reference voltage
Power supply current
IA
IAH
IR
Reference voltage supply
current
IRH
Variation among channels
AVCC
AVRH
AN0 to AN7
Remarks
Notes : • Relatively, the errors increase as |AVRH| value becomes smaller.
• Define an output impedance of external circuit analog input under the following conditions :
Output impedance of external circuit ≤ 2 (kΩ)
If an output impedance of external circuit is exceedingly high, sampling time for analog voltage may run
short.
41
MB91F127/F128
Analog input circuit model diagram
Cin = Approx 30 pF
Rin
Analog
input
Comparator
Approx.
3.6 kΩ
Comparator
AVRH
Be switched on,
only while A/D
conversion is
performed.
Comparator
Note : Use the values shows as guides only.
AVSS/
AVRL
42
MB91F127/F128
5. A/D Converter Block Electrical Characteristics
• Resolution
Analog variations recognized by an A/D converter.
• Linearity error
Deviation of actual conversion characteristics from an ideal line, which is across zero-transition point (“00 0000
0000”←→ “00 0000 0001”) and full-scale transition point (“11 1111 1110”←→ “11 1111 1111”)
• Differential linearity error
Deviation from ideal value of input voltage, which is required for changing output code by 1 LSB.
• Total error
Difference between actual value and ideal value. The error includes zero-transition error, full-scale transition
error, and linearity error.
Total error
3FF
Actual
characteristics
3FE
Digital output
3FD
1.5 LSB’
{1 LSB’ ( N − 1 ) + 0.5 LSB’}
004
VNT
(Actual measured value)
003
Actual
characteristics
Ideal characteristics
002
001
0.5 LSB’
AVSS
1 LSB’ (Ideal value) =
AVRH − AVSS
1024
Total error of digital output N =
Analog input
AVRH
[V]
VNT − {1 LSB’ × (N − 1) + 0.5 LSB’}
1 LSB’
VNT : Transition voltage for digital output to change from (N+1) to N.
VOT’ (Ideal value) = AVSS + 0.5 LSB’
[V]
VFST’ (Ideal value) = AVRH − 1.5 LSB’ [V]
(Continued)
43
MB91F127/F128
(Continued)
Linearity error
Differential linearity error
Actual conversion
characteristics
3FF
Actual conversion
characteristics
3FE
N+1
Digital output
3FD
VFST
(Actual
measured
value)
Digital output
{1 LSB' ( N − 1 ) + VOT}
004
VNT (Actual
measured value)
003
002
N
Ideal
characteristics
VFST
N−1
(Actual measured value)
VNT (Actual
measured value)
N−2
Actual conversion
characteristics
Actual conversion
characteristics
Ideal characteristics
001
VOT (Actual measured value)
AVSS
AVRH
Analog input
Linearity error of digital output N =
VNT − {1 LSB’ × (N − 1) + VOT}
1 LSB’
Differential linearity error of digital output N =
1 LSB =
VFST − VOT
1022
V (N + 1) T − VNT}
1 LSB’
Analog input
AVSS
−1
[LSB]
[LSB]
[V]
VOT : Transition voltage for digital output to change from (000)H to (001)H.
VFST : Transition voltage for digital output to change from (3FE)H to (3FF)H.
44
AVRH
MB91F127/F128
■ FLASH MEMORY WRITE/ERASE CHARACTERISTICS
Parameter
Condition
Sector erase time
Chip erase time
TA = +25 °C,
VCC = 3.3 V
Half byte (16 bit
width) writing time
Value
Unit
Remarks
Min
Typ
Max
1
15
s
Not including time for internal
writing before deletion.
4
s
Not including time for internal
writing before deletion.
16
3600
µs
Not including system-level overhead time.
Write/erase cycle
10,000
cycle
Data holding time
100,000
h
45
MB91F127/F128
■ EXAMPLE CHARACTERISTICS
• Power Supply Current
Power Supply Current vs.
Power Supply Voltage
Power Supply Current (sleeping)
vs. Power Supply Voltage
fc = 25 MHz
80
70
50
ICCS (mA)
60
ICC (mA)
fc = 25 MHz
60
50
40
30
40
30
20
20
10
10
0
2.7
0
3
3.3
3.6
3.9
2.7
3
VCC (V)
Power Supply Current (stopping)
vs. Power Supply Voltage
fc = 25 MHz
3
3.3
3.6
3.9
VCC (V)
IR (µA)
A/D Reference Power Supply Current
vs. Power Supply Voltage
180
160
140
120
100
80
60
40
20
0
2.7
fc = 25 MHz
3
3.3
VCC (V)
46
3.6
3.9
A/D Power Supply Current vs.
Power Supply Voltage
10
9
8
7
6
5
4
3
2
1
0
-1
2.7
fc = 25 MHz
IA (mA)
ICCH (µA)
100
90
80
70
60
50
40
30
20
10
0
-10
2.7
3.3
VCC (V)
3.6
3.9
3
3.3
VCC (V)
3.6
3.9
MB91F127/F128
• Output Voltage
“L” Output Voltage vs.
Power Supply Voltage
300
270
VOL (mV)
4
3.8
3.6
3.4
3.2
3
2.8
2.6
2.4
2.2
2
2.7
240
210
180
3
3.3
3.6
3.9
VCC (V)
150
2.7
3
3.3
VCC (V)
3.6
3.9
Pull-up resistance vs.
Power Supply Voltage
100
R (kΩ)
VOH (V)
“H” Output Voltage vs.
Power Supply Voltage
10
2.7
3
3.3
3.6
3.9
VCC (V)
47
MB91F127/F128
■ ORDERING INFORMATION
Part number
48
Package
MB91F127PFV
100-pin plastic LQFP
(FPT-100P-M05)
MB91F128PFV
100-pin plastic LQFP
(FPT-100P-M05)
Remarks
MB91F127/F128
■ PACKAGE DIMENSIONS
100-pin plastic LQFP
(FPT-100P-M05)
*Pins width and pins thickness include plating thickness.
16.00±0.20(.630±.008)SQ
14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
+0.20
100
26
1
25
C
0.20±0.05
(.008±.002)
0.08(.003)
M
0.10±0.10
(.004±.004)
(Stand off)
0°~8°
"A"
0.50(.020)
+.008
1.50 –0.10 .059 –.004
(Mounting height)
INDEX
0.145±0.055
(.0057±.0022)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
2000 FUJITSU LIMITED F100007S-3c-5
Dimensions in mm (inches)
49
MB91F127/F128
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0201
FUJITSU LIMITED Printed in Japan