OKI MSM9005-XX Dot matrix lcd controller with 8-dot common driver and 65-dot segment driver Datasheet

FEDL9005-03
¡ Semiconductor
MSM9005-xx
¡ Semiconductor
FEDL9005-03
This version:
Sep. 2000
MSM9005-xx
Previous version: Nov. 1997
DOT MATRIX LCD CONTROLLER WITH 8-DOT COMMON DRIVER AND 65-DOT SEGMENT
DRIVER
GENERAL DESCRIPTION
The MSM9005-xx is a controller/driver which displays 13 alphanumerics and symbols (5x7 dots)
and 65 arbitrators on a dot matrix LCD panel that has 8 common inputs and 65 segment inputs.
Command and display data are written by 8-bit serial transfer.
A maximum of 256 types of alphanumerics and symbols can be displayed using an internal
character display ROM. The character display ROM is reprogrammable. The general purpose
code is -01.
FEATURES
• Logic power supply (VDD)
: 2.5 to 5.5V
• LCD bias power supply (VBI)
: 4.0 to 8.0V
• LCD output resistance
Common driver
(C1 to C8)
: 6 kW
Segment driver
(S1 to S65)
: 18 kW
• Display content
Number of display characters
: 13 characters, 1 line
Arbitrator
: 65 dots
• Display control functions
Character blink
: Characters all on or all off can be selected
Arbitrator blink
: 1-dot unit or 5-dot units can be selected
All off setting possible
• 5 interfaces with microcomputer, CS, SI, SO, C/D and SHT (6 interfaces if RST is included)
• Internal character display ROM
: 5 ¥ 7 dots ¥ 256 types (reprogrammable)
• Internal oscillation circuit
: External R, C
• Package:
100-pin plastic QFP (QFP 100-P-1420-0.65-BK) (Product name: MSM9005-xxGS-BK)
xx indicates code number.
1/30
VLCD2
OSC1
Timing
OSC
OSC2
generator
VLCD3
OSC3
RST
5
VLCD4
Address
CG ROM address
pointer
8
generator
(CGA RAM)
(CG ROM)
5¥7¥256 bits
SO
Arbitrator RAM
5
1
SI
Character blink
2/30
VSS
(ABB RAM)
5
S65
FEDL9005-03
5
RAM
65
MSM9005-xx
TEST3
Arbitrator blink
65
Segment driver
65
65-bit segment latch
(CHB RAM)
TEST1
5
C8
S1
1
65-bit shift register
5
5
(AB RAM)
RAM
TEST2
Common driver
SHT
5
C1
F/F GATE
Serial/parallel interface
C/D
Character
RAM
5
CS
8
¡ Semiconductor
VLCD1
BLOCK DIAGRAM
VDD
VSS
FEDL9005-03
¡ Semiconductor
MSM9005-xx
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
NC
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
NC
PIN CONFIGURATION (TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
S64
S65
NC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VLCD4
NC
VLCD3
VLCD2
VLCD1
VDD
RST
CS
C/D
SI
SHT
SO
NC
OSC3
OSC2
OSC1
TEST1
TEST2
TEST3
VSS
NC
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
NC
C8
C7
C6
C5
C4
C3
C2
C1
NC
NC : No connection
100-Pin Plastic QFP
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FEDL9005-03
¡ Semiconductor
MSM9005-xx
PIN DESCRIPTIONS
Pin
2 to 20,
52 to 79
82 to 99
22 to 29
Symbol Type Connected to
Description
S1 to S65
O
LCD segment
LCD segment outputs. Output resistance: £18 kW
C1 to C8
O
LCD common
LCD common outputs. Output resistance: £6kW
Serial data input. Serial data is input through this pin in 8-bit
40
SI
I
Microcontroller
units from the MSB side. For details on the configuration of
input data, see "Command Configuration" and "Input Display
Data Configuration".
Command/data select input. When this pin is at the "H" level,
39
C/D
I
Microcontroller
serial input data from SI is recognized as a command. When
this pin is at the "L" level, serial input data from SI is recognized
as display data.
Shift clock input. Data at SI and C/D pins are read synchronizing
41
SHT
I
Microcontroller
with the rising edge of this clock.
Display data is output to the S0 pin synchronizing with the
falling edge of this clock.
Serial data output. This pin outputs display data. For details on
42
SO
I
Microcontroller
the configuration of output data, see "Output Display Data
Configuration". This pin can be set to high impedance by the
SOE/D command.
Chip select input. When this pin is at the "H" level, chip is
selected, and command and display data can be transferred.
38
CS
I
Microcontroller
When this pin is at the "L" level, SO output is set to high
impedance, SHT input is set to the "H" level, and SI and C/D
inputs are set to the "L" level, and command and display data
transfer are disabled.
37
RST
47
TEST1
48
TEST2
49
TEST3
I
Microcontroller
Reset input.
Setting this pin at the "L" level resets to initial status.
Test signal inputs. Set these pins to the same potential as VSS or
I
—
unconnected. An error may occur by another setting.
Pins for an 80 kHz RC oscillation circuit. Connect resistors and a
46
OSC1
I
45
OSC2
O
44
OSC3
O
—
capacitor as shown below.
10kW
OSC1
56pF
OSC2
62±10kW
OSC2
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FEDL9005-03
¡ Semiconductor
Pin
MSM9005-xx
Symbol Type Connected to
36
VDD
50
VSS
—
—
Description
These are power pins. Set VDD = 2.5 to 5.5V and VSS = 0V.
These are bias power pins for driving the LCD. Set the bias
voltage as follows.
35
4 V £ VDD – VLCD4 £ 8 V
VLCD1
34
VLCD2
33
VLCD3
31
VLCD4
—
—
1
–V
)
4 (VDD LCD4
2
VLCD2=VDD –
(VDD–VLCD4)
4
3
VLCD3=VDD –
(VDD–VLCD4)
4
VLCD1=VDD –
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FEDL9005-03
¡ Semiconductor
MSM9005-xx
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
Power Supply Voltage
VDD
Bias Voltage
VBI
Input Voltage
Power Dissipation
Storage Temperature
Rating
Unit
Ta=25°C
–0.3 to +7.0
V
Ta=25°C
VDD–10 to VDD+0.3
V
VI
Ta=25°C
–0.3 to VDD+0.3
V
VILCD
Ta=25°C
VBI–0.3 to VDD+0.3
V
PD
Ta=85°C
620
mW
TSTG
—
–55 to +150
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Condition
Range
Unit
Power Supply Voltage
Parameter
VDD
*1
2.5 to 5.5
V
Bias Voltage
VBI
*1, *2
VDD–8.0 to VDD–4.0
V
Operating Frequency
fop
—
60 to 110
kHz
Operating Temperature
Top
—
–40 to +85
°C
*1: Voltage values are with respect to VSS.
*2: Add the following voltages to VLCD1, VLCD2, VLCD3 and VLCD4, respectively.
1
4
2
VLCD2=VDD–
4
3
VLCD3=VDD–
4
4
VLCD4=VDD–
4
VLCD1=VDD–
(VDD–VBI)
(VDD–VBI)
(VDD–VBI)
(VDD–VBI)=VBI
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FEDL9005-03
¡ Semiconductor
MSM9005-xx
ELECTRICAL CHARACTERISTICS
DC Characteristics (1)
Parameter
"H" Input Voltage
"L" Input Voltage
"H" Input Current
(Ta=–40 to +85°C, VDD=2.5 to 4.5V, VBI=(VDD–8V) to (VDD–4V))
Symbol
Condition
Min.
Typ.
Max. Unit Applicable pin
VIH1
—
0.8VDD
—
VDD
V
VIH2
—
0.8VDD
—
VDD
V
VIL1
—
0.0
—
0.2VDD
V
VIL2
—
0.0
—
0.2VDD
V
than OSC1
OSC1
Input pins other
than OSC1
OSC1
Input pins other
IIH1
VIN=VDD
—
—
1
mA
IIH2
VDD, VIN=2.5V
5
—
500
mA
TEST
All input pins
IIL
VIN=0V
—
—
–1
mA
"H" Output Voltage
VOH
IOH=–0.5mA
VDD–0.5
—
—
V
"L" Output Voltage
VOL
IOL=0.5mA
—
—
0.5
V
VIN=VDD
—
—
1
mA
VIN=0V
—
—
–1
mA
"L" Input Current
Input pins other
Output Off Leakage Current
IOFF
than TEST
SO
OSC "H" Output Current
IOH
VOH=VDD–0.5V
—
—
–0.15
mA
OSC2,
OSC "L" Output Current
IOL
VOL=0.5V
0.15
—
—
mA
OSC3
COM Output Resistance
RC
IO=+/–50mA
—
—
6
kW
C1 to C8
SEG Output Resistance
RS
IO=+/–10mA
—
—
18
kW
S1 to S65
—
—
0.2
mA
VSS
—
—
50
mA
VLCD4
ISS
Supply Current
IBI
VDD=2.5V, VBI=VDD–8V,
fOSC=80kHz
(External resistor, capacitor)
C=56pF, RS=10kW,
R=66kW
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FEDL9005-03
¡ Semiconductor
MSM9005-xx
DC Characteristics (2)
(Ta=–40 to +85°C, VDD=4.5 to 5.5V, VBI=(VDD–8V) to (VDD–4V))
Parameter
"H" Input Voltage
"L" Input Voltage
"H" Input Current
Symbol
Condition
Min.
Typ.
Max. Unit Applicable pin
VIH1
—
0.8VDD
—
VDD
V
VIH2
—
0.8VDD
—
VDD
V
VIL1
—
0.0
—
0.2VDD
V
VIL2
—
0.0
—
0.2VDD
V
than OSC1
OSC1
Input pins other
than OSC1
OSC1
Input pins other
IIH1
VIN=VDD
—
—
1
mA
IIH2
VDD, VIN=5.5V
5
—
1000
mA
TEST
All input pins
IIL
VIN=0V
—
—
–1
mA
"H" Output Voltage
VOH
IOH=–0.5mA
VDD–0.5
—
—
V
"L" Output Voltage
VOL
IOL=0.5mA
—
—
0.5
V
VIN=VDD
—
—
1
mA
"L" Input Current
Input pins other
Output Off Leakage Current
IOFF
OSC "H" Output Current
IOH
OSC "L" Output Current
COM Output Resistance
SEG Output Resistance
than TEST
SO
VIN=0V
—
—
–1
mA
VOH=VDD–0.5V
—
—
–0.15
mA
OSC2,
IOL
VOL=0.5V
0.15
—
—
mA
OSC3
RC
IO=+/–50mA
—
—
6
kW
C1 to C8
RS
IO=+/–10mA
—
—
18
kW
S1 to S65
—
—
0.8
mA
VSS
—
—
50
mA
VLCD4
ISS
Supply Current
IBI
VDD=5.5V, VBI=VDD–8V,
fOSC=80kHz
(External resistor, capacitor)
C=56pF, RS=10kW,
R=66kW
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FEDL9005-03
¡ Semiconductor
MSM9005-xx
AC Characteristics
(Ta=–40 to +85°C, VDD=2.5 to 5.5V, VBI=(VDD–8V) to (VDD–4V))
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
tCS
—
300
—
—
ns
CS Hold Time
tCH
—
200
—
—
ns
CS "L" Time
tCSL
—
500
—
—
ns
CS Setup Time
SO ON Delay Time
tON
CL=45pF
—
—
200
ns
SO OFF Delay Time
tOFF
CL=45pF
—
—
200
ns
SO Output Delay Time
tDLY
CL=45pF
0
—
200
ns
tIS
—
200
—
—
ns
Input Setup Time
Input Hold Time
tIH
—
200
—
—
ns
Input Rise, Fall Time
tr/tf
All inputs
—
—
50
ns
RST Pulse Width
tRT
—
5
—
—
ms
Wait Time After RST Pulse
trDLY
—
500
—
—
ns
SHT Frequency
fSHT
—
—
—
2
MHz
SHT Pulse Width
tSHT
—
200
—
—
ns
RST
0.8VDD
tRT
0.2VDD
trDLY
CS
tf
0.8VDD
tCSL
0.2VDD
tr
tCH
0.8VDD
SI
0.2VDD
0.8VDD
C/D
tCS
tIS
tSHT
SHT
0.2VDD
tIH
0.8VDD
tSHT
0.2VDD
tON
tDLY
* "HZ"
SO
tOFF
*"H Z "
VDD–0.5V
0.5V
* "HZ " : High impedance.
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FEDL9005-03
¡ Semiconductor
MSM9005-xx
FUNCTIONAL DESCRIPTION
General Description of Block Diagram
1. Address Pointer
An address pointer is a 5-bit counter which assigns the write destination or read destination
address of CGA RAM and AB RAM, and the write destination address of CHB RAM and ABB
RAM. The value of the address pointer can be set by the LPA command. The value of the
address pointer is automatically incremented by 1 after executing the AINC and CHB
commands, or after transferring input display data.
2. Character Generator Address RAM (CGA RAM)
The character generator address RAM stores 8-bit character codes of the character generator
ROM. A maximum of thirteen 8-bit character codes can be stored.
3. Arbitrator RAM (AB RAM)
The arbitrator RAM stores the lighting data of the arbitrator. Lighting data is stored in 5 dot
units, and a maximum of 65 dots of lighting data can be stored.
4. Character Blink RAM (CHB RAM)
The character blink RAM stores character blink data. A maximum of 13 characters of blink
data can be stored.
5. Arbitrator Blink RAM (ABB RAM)
The arbitrator blink RAM stores blink data of the arbitrator. Blink data is stored in 5 dot units,
and a maximum of 65 dots of blink data can be stored.
6. Character Generator ROM (CG ROM)
The character generator ROM generates character patterns with 5 ¥ 7 dots. This ROM can store
a maximum of 256 types of characters, numerics, and symbols.
When an 8-bit character code of CG ROM is written to CGA RAM, character patterns with
5 ¥ 7 dots corresponding to 8-bit character code are displayed at the LCD display position
corresponding to the CGA RAM address.
Relationship between display screen, LCD output and memory address
Arbitrator
C1
C2
C3
C4
C5
C6
C7
C8
Screen
Character
S1
RAM Arbitrator
Address Character
map
S5 S6
S10 S11
S15 S16
S20 S21
S25 S26
S30 S31
S35 S36
S40 S41
S45 S46
S50 S51
S55 S56
S60 S61
S65
10000b 10001b 10010b 10011b 10100b 10101b 10110b 10111b 11000b 11001b 11010b 11011b 11100b
00000b 00001b 00010b 00011b 00100b 00101b 00110b 00111b 01000b 01001b 01010b 01011b 01100b
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FEDL9005-03
¡ Semiconductor
MSM9005-xx
Command Configuration
Command
Mnemonic
1 LPA
Operation
Load Pointer
Address
Input data
MSB
LSB
Comment
D7 D6 D5 D4 D3 D2 D1 D0
1
1
* A4 A3 A2 A1 A0
Sets address pointer value
A0, A1, A2, A3 A4: address pointer value
(binary)
2 DISP
DISPlay on/off
1
0
0
*
1
0
0 DI
Sets on/off of LCD panel
Panel is on when DI = "1"
Panel is off when DI = "0"
3 CHB
4 ABBC 1/5
CHaracter Blink
on/off
ArBitrator Blink
Control 1/5 dot
Sets blink in 5 dot units
0
*
*
*
0
0 CB * Blink starts in 5 dot units when CB = "1"
Blink is cleared when CB = "0"
Sets writing method to arbitrator blink RAM
1
0
0
1
1
1
0 BC Writing in 1 dot unit is enabled when BC = "1"
Writing in 5 dot unit is enabled when BC = "0"
Sets start/stop of writing to arbitrator blink RAM
5 ABB
6 BPC
7 AINC
8 LOT
9 SOE/D
ArBitrator Blink
Blink Pattern
Control
Address
INCrement
Load OpTion
Serial Out
Enable/Disable
1
0
0
0
1
1
0 AB Writing in 1 dot unit starts when AB = "1"
Writing in 1 dot unit stops when AB = "0"
Sets blink pattern of characters
1
0
0
*
0
0
1 BP When BP = 1, all off ´ character blink
When BP = 0, all on ´ character blink
1
0
0
*
1
*
1
* Increments address pointer value by 1
1
0
1
1
*
* I1 I0 Sets additional function of AINC command
1
0
0
*
0
1
Set SO pin
1
S SO pin is a CMOS output when S = "1"
SO pin is in a high impedance state when S = "0"
*: Don't care
The commands listed above requires the wait time (21 ¥ 1/fOSC).
The address pointer value is incremented by 1 when CG ROM code data, arbitrator display data
and arbitrator blink data are input and when AINC and CHB commands are executed.
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FEDL9005-03
¡ Semiconductor
MSM9005-xx
Input Display Data Configuration
Command
Input data
MSB
LSB
Comment
D7 D6 D5 D4 D3 D2 D1 D0
1 CG ROM code data
C7 C6 C5 C4 C3 C2 C1 C0 C0 to C7: CG ROM address
2 Arbitrator display data
*
Relationship between AB0 to AB4 and
3 Arbitrator blink data
*
*
*
* AB4 AB3 AB2 AB1 AB0 segments pins is as follows.
S5n+1
S5n+5
AB4
AB0
* AB4 AB3 AB2 AB1 AB0
n = 0 to 12
*: Don't care
Output Display Data Configuration
Command
Input data
MSB
LSB
Comment
D7 D6 D5 D4 D3 D2 D1 D0
1 CG ROM code data
C7 C6 C5 C4 C3 C2 C1 C0 C0 to C7: CG ROM address
Relationship between RD0 to RD4 and
segment pins is as follows.
2 Arbitrator display data
0
0
0 RD4 RD3 RD2 RD1 RD0
S5n+1
S5n+5
RD4
RD0
n = 0 to 12
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FEDL9005-03
¡ Semiconductor
MSM9005-xx
How to Write Command and Display Data
• Input a command and display data into the SI pin sequentially from MSB in 8-bit units (MSB
first).
• Setting CS pin at "H" level enables transfer of a command and display data.
• Setting CS pin at a "L" level disables data transfer.
• As shown in the figure below, data is shifted at the rising edge of the shift clock that is input
to the SHT pin. When 8 shift clocks are input, internal load signals are automatically generated
and a command or display data is loaded. It is unnecessary to provide load signals externally.
• Loaded 8-bit data is recognized as a command if the C/D pin is set at "H" level, and is
recognized as display data if the C/D pin is set at "L" level on the rising edge of the 8th shift
clock input to the SHT pin.
Write timing is shown below.
(Example) Writing CG ROM address data The wait time of 21 × 1/fOSC is required
CS
C/D
21 x 1/fOSC
WAIT
Don't Care
21 x 1/fOSC
WAIT
Don't Care
tCH
Don't Care
SHT
Address
pointer
SI
00h
01h
1 1 * 0 0 0 0 0
C7 C6 C5 C4 C3 C2 C1 C0
C7 C6 C5 C4 C3 C2 C1 C0
MSB
LSB
LPA command
(Sets address pointer
to 00h)
MSB
LSB
CG ROM code data
MSB
LSB
CG ROM code data at
the next address
02h
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FEDL9005-03
¡ Semiconductor
MSM9005-xx
How to Read Display Data
• Display data is output sequentially from MSB in 8-bit units (MSB first).
• Setting S = "1" by the SOE/D command after setting the CS pin at "H" level enables the output
of display data from the SO pin.
• Setting the CS pin at "L" level or setting S = "0" by the SOE/D command sets the SO pin to high
impedance and disables output of display data.
• CGARAM or ABRAM data corresponding to the address pointer value is output.
• Display data is output from MSB on the falling edge of the shift clock that is input to the SHT
pin, as shown in the figure below.
Read timing is shown below.
(Example) Reading by AINC command The wait time of 21 × 1/fOSC is required
21 x 1/fOSC
CS
C/D
SI
WAIT
WAIT
21 x 1/fOSC
Don't Care
Don't Care
1 1 * 0 0 0 0 1
1
0
SOE/D command
0
*
Don't Care
1
*
1
*
1
0
AINC command
0
*
1
*
1
*
AINC command
SHT
Address
pointer
SO
00h
"HZ"
01h
0
MSB
RD4 RD3 RD2 RD1 RD
0
LSB
Display data at address
00h of CGA RAM
0
0
0
MSB
RD4 RD3 RD2 RD1 RD
0
LSB
Display data at address
01h of CGA RAM
0
0
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MSM9005-xx
Reset Function
Reset is enabled when the RST pin is set at "L" level at such timing as at power-on, which
initializes all functions and turns off the LCD panel.
The initial state after reset is as follows.
Data of each RAM ........... All contents are held. (Contents are undefined when power is turned
on.)
Arbitrator blink ............... Writing in 5 dot units is set.
Character blink ................ Repeat of all display-on and character display is set.
Display on and
all display off ................... All display off mode is selected.
Segment output ............... All segment outputs go to VDD level.
Common output.............. All common outputs go to VDD level.
SO pin ............................... High impedance state
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MSM9005-xx
Command Description
1. Load pointer address command (LPA command)
This command is used to set the value of the address pointer. Execute this command before
transferring other commands, CG ROM code data and arbitrator display data.
After this command is executed, setting the C/D pin from "1" to "0" enables writing CG ROM
code data to CG ROM address RAM (CGA RAM) and arbitrator display data to arbitrator
RAM (ABRAM). After CG ROM code data or arbitrator display data is transferred, the
address pointer is automatically incremented (+1), and CG ROM code data and arbitrator
display data can be transferred continuously.
[How to transfer LPA command and CG ROM code data]
LPA
command
D8 D7 D6 D5 D4 D3 D2 D1
1
1
*
0
0
0
0
0
Specify address pointer value
(Example: Set address pointer value to 00H.)
*: Don't care
CG ROM
D8 D7 D6 D5 D4 D3 D2 D1
code data
C7 C6 C5 C4 C3 C2 C1 C0
CG ROM code data is written to CGA RAM address 00H, and
the character corresponding to the specified CG ROM code
is displayed in segments 1 to 5.
After this data transfer is executed, the address pointer value
becomes 01H.
CG ROM
D8 D7 D6 D5 D4 D3 D2 D1
code data
C7 C6 C5 C4 C3 C2 C1 C0
CG ROM code data is written to CGA RAM address 01H, and
the character corresponding to the specified CG ROM code
is displayed at segments 6 to 10.
After this data transfer is executed, the address pointer value
becomes 02H.
CG ROM
D8 D7 D6 D5 D4 D3 D2 D1
code data
C7 C6 C5 C4 C3 C2 C1 C0
CG ROM code data is written to CGA RAM address 02H, and
the character corresponding to the specified CG ROM code
can be displayed at segments 11 to15.
After this data transfer is executed, the address pointer value
becomes 03H.
(Repeats eight times.)
CG ROM
D8 D7 D6 D5 D4 D3 D2 D1
code data
C7 C6 C5 C4 C3 C2 C1 C0
CG ROM code data is written to CGA RAM address 0BH, and
the character corresponding to the specified CG ROM code
can be displayed at segments 56 to 60.
After this data transfer is executed, the address pointer value
becomes 0CH.
16/30
FEDL9005-03
¡ Semiconductor
CG ROM
D8 D7 D6 D5 D4 D3 D2 D1
code data
C7 C6 C5 C4 C3 C2 C1 C0
MSM9005-xx
CG ROM code data is written to CGA RAM address 0CH, and
the character corresponding to the specified CG ROM code
can be displayed at segments 61 to 65.
After this data transfer is executed, the address pointer value
becomes 0DH.
CG ROM
D8 D7 D6 D5 D4 D3 D2 D1
code data
C7 C6 C5 C4 C3 C2 C1 C0
CGA RAM address is only 00H to 0CH. The address
pointer value becomes 0DH. However, this CG
ROM data is ignored.
17/30
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MSM9005-xx
[How to transfer LPA command and arbitrator display data]
LPA
D8 D7 D6 D5 D4 D3 D2 D1
1
command
1
*
1
0
0
0
0
Specify address pointer value
(Example: Set address pointer value to 10H.)
Arbitrator
D8 D7 D6 D5 D4 D3 D2 D1
*
display data
*
*
A4 A3 A2 A1 A0
Arbitrator display data is written to AB RAM address 10H,
and the specified arbitrator of segments 1 to 5 can be
displayed.
After this data transfer is executed, the address pointer value
becomes 11H.
Arbitrator
D8 D7 D6 D5 D4 D3 D2 D1
*
display data
*
*
A4 A3 A2 A1 A0
Arbitrator display data is written to AB RAM address 11H,
and the specified arbitrator of segments 6 to 10 can be
displayed.
After this data transfer is executed, the address pointer value
becomes 12H.
Arbitrator
D8 D7 D6 D5 D4 D3 D2 D1
*
display data
*
*
A4 A3 A2 A1 A0
Arbitrator display data is written to AB RAM address 12H,
and the specified arbitrator of segments 11 to 15 can be
displayed.
After this data transfer is executed, the address pointer value
becomes 13H.
(Repeats eight times.)
Arbitrator
D8 D7 D6 D5 D4 D3 D2 D1
*
display data
*
*
A4 A3 A2 A1 A0
Arbitrator display data is written to AB RAM address 1BH,
and the specified arbitrator of segments 59 to 60 can be
displayed.
After this data transfer is executed, the address pointer value
becomes 1CH.
Arbitrator
D8 D7 D6 D5 D4 D3 D2 D1
*
display data
*
*
A4 A3 A2 A1 A0
Arbitrator display data is written to AB RAM address 1CH,
and the specified arbitrator of segments 61 to 65 can be
displayed.
After this data transfer is executed, the address pointer value
becomes 1DH.
Arbitrator
D8 D7 D6 D5 D4 D3 D2 D1
display data
*
*
*
A4 A3 A2 A1 A0
AB RAM address is only 10H to 1CH. The address
pointer value becomes 1DH. However, this
arbitrator display data is ignored.
*: Don't care
18/30
FEDL9005-03
¡ Semiconductor
MSM9005-xx
2. Display on/off command (DISP command)
This command is used to select LCD panel display-on mode and display-off mode. Setting
DI = "0" enters display-off mode. At this time, the output voltage of all segments and common
output pins go to VDD level and the LCD panel goes out. Setting DI = "1" enters display-on
mode. At this time, the LCD panel restarts the status display before entering display-off
mode.
[DISP command format]
DISP
command
D8 D7 D6 D5 D4 D3 D2 D1
1
0
0
*
1
0
0
DI
Display-off mode is set when DI = “0”
Display-on mode is set when DI = “1”
*: Don't care
3. Arbitrator Blink Control 1/5 command (ABBC 1/5 command)
This command is used to select the type of writing arbitrator blink data to the Arbitrator Blink
RAM (ABB RAM). This command is used along with the Character Blink on/off command
or with the Arbitrator Blink command, explained below.
Setting BC = "0" enables writing arbitrator blink data in 5-bit units using the CHB command.
Setting BC = "1" enables writing arbitrator blink data in 1 bit unit using the ABB command.
[ABBC 1/5 command format]
DISP
command
D8 D7 D6 D5 D4 D3 D2 D1
1
0
0
1
1
1
0
BC
BC = "0" enables writing in 5-bit unit.
BC = "1" enables writing in 1-bit unit.
4. Character Blink on/off command (CHB command)
This command is used to blink a character and arbitrator in 5-dot units. Blinking can be set
for each address pointer value. This command is used with the ABBC 1/5 command,
explained above.
If CB = "0" is set when the address pointer value is 00H to 0CH, "0" is written to Character Blink
RAM (CHB RAM), and the blinking of a character displayed in the segments corresponding
to the address pointer value stops. If CB = "1" is set, "1" is written to CHB RAM, and the
character displayed in the segments corresponding to the address pointer value starts
blinking.
If CB = "0" is set when the address pointer value is 10H to 1CH, "0" is written to the arbitrator
blink RAM (ABB RAM) and the blinking of the arbitrator displayed in the segments
corresponding to the address pointer value stops. If CB = "1" is set, "1" is written to the ABB
RAM, and the arbitrator displayed in the segments corresponding to the address pointer
value starts blinking.
Set the address pointer value by the LPA command before executing this command.
Transfer the LPA command, ABBC 1/5 command and CHB command as follows.
19/30
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¡ Semiconductor
MSM9005-xx
[How to transfer LPA command, ABBC 1/5 command and CHB command (character blink
setting)]
LPA
command
D8 D7 D6 D5 D4 D3 D2 D1
1
1
*
0
0
0
0
0
Specify the address pointer value.
(Example: Set the address pointer value to 00H.)
CHB
command
D8 D7 D6 D5 D4 D3 D2 D1
0
*
*
*
0
0
CB
*
CB value is written to CHB RAM address 00H and the
blinking of characters displayed in segments 1 to 5 is set.
After this command is executed, the address pointer value
CHB
command
D8 D7 D6 D5 D4 D3 D2 D1
0
*
*
*
0
0
CB
becomes 01H.
*
CB value is written to CHB RAM address 01H, and the
blinking of characters displayed in segments 6 to 10 is set.
After this command is executed, the address pointer value
becomes 02H.
(Repeats nine times.)
CHB
command
D8 D7 D6 D5 D4 D3 D2 D1
0
*
*
*
0
0
CB
*
CB value is written to CHB RAM address 0BH and the
blinking of characters displayed in segments 56 to 60 is set.
After this command is executed, the address pointer value
becomes 0CH.
CHB
command
D8 D7 D6 D5 D4 D3 D2 D1
0
*
*
*
0
0
CB
*
CB value is written to CHB RAM address 0CH, and the
blinking of characters displayed in segments 61 to 65 is set.
After this command is executed, the address pointer value
becomes 0DH.
CHB
command
D8 D7 D6 D5 D4 D3 D2 D1
0
*
*
*
0
0
CB
*
CHB RAM address is only 00H to 0CH. The address
pointer value becomes 0DH. However, this CHB
command is ignored.
*: Don't care
20/30
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¡ Semiconductor
MSM9005-xx
[How to transfer LPA command, ABBC 1/5 command and CHB command (arbitrator blink
setting)]
LPA
command
D8 D7 D6 D5 D4 D3 D2 D1
1
1
*
1
0
0
0
0
Specify address pointer value
(Example: Set address pointer value to 10H.)
ABBC1/5
command
CHB
command
D8 D7 D6 D5 D4 D3 D2 D1
1
0
0
1
1
1
0
0
Set BC = “0” to enable writing in 5-dot units.
D8 D7 D6 D5 D4 D3 D2 D1
0
*
*
*
0
0
CB
*
CB value is written to ABB RAM address 10H, and the
blinking of arbitrator displayed in segments 1 to 5 is set.
After this command is executed, the address pointer value
becomes 11H.
CHB
command
D8 D7 D6 D5 D4 D3 D2 D1
0
*
*
*
0
0
CB
*
CB value is written to ABB RAM address 11H, and the
blinking of arbitrator displayed in segments 6 to 10 is set.
After this command is executed, the address pointer value
becomes 12H.
(Repeats nine times.)
CHB
command
D8 D7 D6 D5 D4 D3 D2 D1
0
*
*
*
0
0
CB
*
CB value is written to ABB RAM address 1BH, and the
blinking of arbitrator displayed in segments 56 to 60 is set.
After this command is executed, the address pointer value
becomes 1CH.
CHB
command
D8 D7 D6 D5 D4 D3 D2 D1
0
*
*
*
0
0
CB
*
CB value is written to ABB RAM address 1CH and the
blinking of arbitrator displayed in segments 61 to 65 is set.
After this command is executed, the address pointer value
becomes 1DH.
CHB
command
D8 D7 D6 D5 D4 D3 D2 D1
0
*
*
*
0
0
CB
*
ABB RAM address is only 10H to 1CH. The address
pointer value becomes 1DH. However, this CHB
command is ignored.
*: Don't care
21/30
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¡ Semiconductor
MSM9005-xx
5. Arbitrator Blink command (ABB command)
This command is used to start writing arbitrator blink data to ABB RAM in 1-dot unit. This
command is used with the ABB 1/5 command described above.
After setting AB = "1", setting the C/D pin from "1" to "0" enables writing arbitrator blink data
to ABB RAM in 1-dot unit. After arbitrator blink data is transferred, the address pointer is
automatically incremented by 1, and arbitrator blink data can be transferred continuously.
Set the address pointer value by the LPA command before executing this command. Transfer
the ABBC 1/5 command, ABB command and arbitrator blink data as follows.
[How to transfer LPA command, ABBC 1/5 command, ABB command and arbitrator blink data]
LPA
command
D8 D7 D6 D5 D4 D3 D2 D1
1
1
*
0
0
0
0
0
Specify the address pointer value.
(Example: Set the address pointer to 10H.)
ABBC1/5
command
ABB
command
Arbitrator
blink data
D8 D7 D6 D5 D4 D3 D2 D1
1
0
0
1
1
1
0
1
Set BC = “1” to enable writing in 1-dot unit.
D8 D7 D6 D5 D4 D3 D2 D1
1
0
0
0
1
1
0
1
Set AB = “1” to start writing in 1-dot unit.
D8 D7 D6 D5 D4 D3 D2 D1
*
*
* AB4 AB3 AB2 AB1 AB0 Arbitrator blink data is written to ABB RAM address 10H,
and the arbitrator specified in segments 1 to 5 starts blinking.
After this command is executed, the address pointer value
becomes 11H.
Arbitrator
blink data
D8 D7 D6 D5 D4 D3 D2 D1
*
*
* AB4 AB3 AB2 AB1 AB0 Arbitrator blink data is written to ABB RAM address 11H,
and the arbitrator specified in segments 6 to 10 starts blinking.
After this command is executed, the address pointer value
becomes 12H.
(Repeats nine times.)
Arbitrator
blink data
D8 D7 D6 D5 D4 D3 D2 D1
*
*
* AB4 AB3 AB2 AB1 AB0 Arbitrator blink data is written to ABB RAM address 1BH,
and the arbitrator specified in segments 59 to 60 starts
blinking.
After this command is executed, the address pointer value
becomes 1CH.
*: Don't care
22/30
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¡ Semiconductor
Arbitrator
blink data
MSM9005-xx
D8 D7 D6 D5 D4 D3 D2 D1
*
*
* AB4 AB3 AB2 AB1 AB0 Arbitrator blink data is written to ABB RAM address 1CH,
and the arbitrator specified in segment 61 to 65 starts blinking.
After this command is executed, the address pointer value
becomes 1DH.
Arbitrator
blink data
D8 D7 D6 D5 D4 D3 D2 D1
*
*
* AB4 AB3 AB2 AB1 AB0 ABB RAM address is only 10H to 1CH. The address
pointer value becomes 1DH. However, this
ABB command is ignored.
*: Don't care
23/30
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MSM9005-xx
6. Blink Pattern Control Command (BPC command)
This command is used to select the blink pattern of characters.
If BP = "1" is set, the display repeats all lighting off and character displays. If BP = "0" is set,
the display repeats all light on and character displays.
This command cannot be set for each address pointer value. If this command is executed, 13
characters are set at the same blink pattern.
[BPC Command Format]
D8 D7 D6 D5 D4 D3 D2 D1
1
0
0
*
0
0
1
BP
*: Don't care
When BP = "1"
When BP = "0"
7. Address Increment Command (AINC Command)
This command is used to increment the address pointer value by +1. After this command is
executed, the processing being set by the LOT command, described below, is performed on
the RAM corresponding to the address pointer value before being incremented by +1.
[AINC Command Format]
D8 D7 D6 D5 D4 D3 D2 D1
1
0
0
*
1
*
1
*
*: Don't care
8. Load Option Command (LOT Command)
This command is used to process the display corresponding to the address pointer value
before being incremented by 1 when the AINC command is executed.
If I0 = "1" is set, all "0s" are written to CGA RAM and AB RAM each time the AINC command
is executed. CG ROM code "00h" is displayed on the character display and the arbitrator goes
out.
If I1 = "1" is set, all "0"s are written to CHB RAM and ABB RAM each time the AINC command
is executed. Therefore character and arbitrator blinking is cleared.
I0 and I1 can be set independently. If I0 = "1" and I1 = "1" are set, "0" is written to all CG RAM,
AB RAM, CHB RAM and ABB RAM.
[LOT Command Format]
D8 D7 D6 D5 D4 D3 D2 D1
1
0
1
1
*
*
I1
I0
*: Don't care
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MSM9005-xx
9. Serial Out Enable/Disable Command (SOE/D Command)
This command is used to select the output impedance of the SO pin.
When S = "1" is selected, the S0 pin becomes CMOS output and it outputs displays data. While
S = "0" is selected, the S0 pin becomes high impedance status.
[SOE/D Command Format]
D8 D7 D6 D5 D4 D3 D2 D1
1
0
0
*
0
1
1
S
*: Don't care
25/30
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MSM9005-xx
Initial Setting Operation Flow Chart
* Power on and RST signal input
Start
All display OFF
* All output status by RST signal input
LPA command
* Set address pointer value
ABB1/5
command
ABB1/5
command
Address is automatically
incremented
ABB
command
CHB
command
Address is automatically
incremented
CG ROM
code data
writing
NO
Address is automatically
incremented
Address is automatically
incremented
Writing end
YES
Arbitrator
display data
writing
NO
Writing end
YES
Arbitrator
blink data
writing
NO
Writing end
YES
NO
Writing end
YES
Other RAM
setting
NO
BPC command
DISP command
Note: Normal operation status (display ON)
End
26/30
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MSM9005-xx
MSM9005-01 CG ROM Code
MSB
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
LSB
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
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MSM9005-xx
REFERENCE DATA
Oscillation Circuit Characteristics
RC oscillation characteristics
(R=65.5kW fixed)
Oscillation frequency (kHz)
140
120
100
80
C=29.4pF
60
C=56.6pF
40
C=121pF
20
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
Oscillation frequency (kHz)
VDD (V)
RC oscillation characteristics
(C=56.6pF fixed)
200
150
R=26.6kW
100
R=65.5kW
50
R=104kW
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VDD (V)
28/30
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MSM9005-xx
PACKAGE DIMENSIONS
(Unit : mm)
QFP100-P-1420-0.65-BK
.
Mirror finish
Oki Electric Industry Co., Ltd.
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5 mm)
1.29 TYP.
4/Nov. 28, 1996
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
29/30
FEDL9005-03
¡ Semiconductor
MSM9005-xx
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
6.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
9.
MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 2000 Oki Electric Industry Co., Ltd.
Printed in Japan
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