Fujitsu MB84VD23280EE-90-PBS 64m (x8/x16) flash memory & 8m (x8/x16) static ram Datasheet

FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50211-1E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
64M (×8/×16) FLASH MEMORY &
8M (×8/×16) STATIC RAM
MB84VD23280EA-90/MB84VD23280EE-90
■ FEATURES
• Power supply voltage of 2.7 V to 3.3 V
• High performance
90 ns maximum access time (Flash)
70 ns maximum access time (SRAM)
• Operating Temperature
–25 °C to +85 °C
• Package 101-ball BGA
(Continued)
■ PRODUCT LINEUP
Flash Memory
Ordering Part No.
VCCf, VCCs = 3.0 V
+0.3V
–0.3 V
SRAM
MB84VD23280EA-90/MB84VD23280EE-90
Max. Address Access Time (ns)
90
70
Max. CE Access Time (ns)
90
70
Max. OE Access Time (ns)
35
35
■ PACKAGE
101-pin plastic FBGA
BGA-101P-M01
MB84VD23280EA-90/MB84VD23280EE-90
(Continued)
— FLASH MEMORY
• Simultaneous Read/Write operations (flex bank)
Two virtual Banks are chosen from the combination of four physical banks
Host system can program or erase in one bank, then read immediately and simultaneously read from the other
bank between read and write operations
Read-while-erase
Read-while-program
• Minimum 100,000 write/erase cycles
• Sector erase architecture
Sixteen 4 K words and one hundred twenty-six 32 K word.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Embedded EraseTM* Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM* Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready-Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode.
• Low VCC write inhibit ≤ 2.5 V
• Hidden ROM (Hi-ROM) region
256 byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC input pin
At VIL, allows protection of 2 of 8 Kbytes on both ends of each boot sector, regardless of sector protection/
unprotection status.
At VIH, allows removal of boot sector protection
At VACC, increases program performance
• Program Suspend/Resume
Suspends the program operation to allow a read in another address
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
• Please refer to “MBM29DL640E” data sheet in detailed function
— SRAM
• Power dissipation
Operating : 50 mA Max.
Standby : 25 µA Max.
• Power down features using CE1s and CE2s
• Data retention supply voltage: 1.5 V to 3.3 V
• CE1s and CE2s Chip Select
• Byte data control: LBs (DQ7-DQ0), UBs (DQ15-DQ8)
*: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
2
MB84VD23280EA-90/MB84VD23280EE-90
■ PIN ASSIGNMENT
(TOP View)
Marking Side
A12
B12
C12
M12
N12
P12
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
A11
B11
C11
G11
H11
M11
N11
P11
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
A10
B10
C10
E10
F10
G10
H10
J10
K10
M10
N10
P10
N.C.
N.C.
N.C.
A15
A21
N.C.
A16
CIOf
Vss
N.C.
N.C.
N.C.
D9
E9
F9
G9
H9
J9
K9
L9
A11
A12
A13
A14
SA
DQ15/A-1
DQ7
DQ14
D8
E8
F8
G8
H8
J8
K8
L8
A8
A19
A9
A10
DQ6
DQ13
DQ12
DQ5
C7
D7
E7
F7
J7
K7
L7
M7
N.C.
WE
CE2s
A20
DQ4
Vccs
CIOs
N.C.
C6
D6
E6
F6
J6
K6
L6
M6
N.C.
WP/ACC
RESET
RY/BY
DQ3
Vccf
DQ11
N.C.
D5
E5
F5
G5
H5
J5
K5
L5
LBs
UBs
A18
A17
DQ1
DQ9
DQ10
DQ2
D4
E4
F4
G4
H4
J4
K4
L4
A7
A6
A5
A4
Vss
OE
DQ0
DQ8
A3
B3
C3
E3
F3
G3
H3
J3
K3
M3
N3
P3
N.C.
N.C.
N.C.
A3
A2
A1
A0
CEf
CE1s
N.C.
N.C.
N.C.
A2
B2
C2
D2
G2
H2
M2
N2
P2
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
A1
B1
C1
M1
N1
P1
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
(BGA-101P-M01)
3
MB84VD23280EA-90/MB84VD23280EE-90
■ PIN DESCRIPTION
4
Pin name
Input/
Output
A18 to A0
I
Address Inputs (Common)
A21 to A19, A–1
I
Address Inputs (Flash)
SA
I
Address Input (SRAM)
DQ15 to DQ0
I/O
CEf
I
Chip Enable (Flash)
CE1s
I
Chip Enable (SRAM)
CE2s
I
Chip Enable (SRAM)
OE
I
Output Enable (Common)
WE
I
Write Enable (Common)
RY/BY
O
Ready/Busy Output (Flash) Open Drain Output
UBs
I
Upper Byte Control (SRAM)
LBs
I
Lower Byte Control (SRAM)
CIOf
I
I/O Configuration (Flash)
CIOf = VIH is Word mode (×16), CIOf = VIL is Byte mode (×8)
CIOs
I
I/O Configuration (SRAM)
CIOs = VIH is Word mode (×16), CIOs = VIL is Byte mode (×8)
RESET
I
Hardware Reset Pin/Sector Protection Unlock (Flash)
WP/ACC
I
Write Protect / Acceleration (Flash)
N.C.
—
VSS
Power
Device Ground (Common)
VCCf
Power
Device Power Supply (Flash)
VCCs
Power
Device Power Supply (SRAM)
Description
Data Inputs/Outputs (Common)
No Internal Connection
MB84VD23280EA-90/MB84VD23280EE-90
■ BLOCK DIAGRAM
VCCf
VSS
A21 to A0
RY/BY
A21 to A0
A–1
WP/ACC
RESET
CEf
CIOf
64 M bit
Flash Memory
DQ15/A–1 to DQ0
DQ15/A–1 to DQ0
VCCs
VSS
A18 to A0
DQ15 to DQ0
SA
LBs
UBs
WE
OE
CE1s
CE2s
CIOs
8 M bit
Static RAM
5
MB84VD23280EA-90/MB84VD23280EE-90
■ DEVICE BUS OPERATIONS
Table 1. 1 User Bus Operations (Flash = Word mode; CIOf = VCCf, SRAM = Word mode; CIOs = VCCs)
Operation (1), (3) CEf CE1s CE2s OE
Full Standby
H
H
Output Disable
L
Read from Flash
(2)
L
Write to Flash
L
Read from SRAM
Write to SRAM
H
H
Temporary Sector
Group
Unprotection(4)
X
Flash Hardware
Reset
X
Boot Block Sector
Write Protection
X
H
X
X
L
L
H
H
X
X
L
H
X
X
L
H
X
X
L
L
L
H
H
X
X
H
X
X
L
X
X
WE
WP/
SA LBs UBs DQ7 to DQ0 DQ15 to DQ8 RESET ACC
(6)
(5)
X
X
X
X
X
HIGH-Z
HIGH-Z
H
H
X
X
X
HIGH-Z
HIGH-Z
X
X
X
H
H
HIGH-Z
HIGH-Z
H
H
X
X
X
HIGH-Z
HIGH-Z
L
H
X
X
X
DOUT
H
L
X
X
X
L
L
X
H
L
X
X
H
X
H
X
DOUT
H
X
DIN
DIN
H
X
L
DOUT
DOUT
H
L
HIGH-Z
DOUT
H
X
L
H
DOUT
HIGH-Z
L
L
DIN
DIN
H
L
HIGH-Z
DIN
H
X
L
H
DIN
HIGH-Z
X
X
X
X
X
X
X
VID
X
X
X
X
X
X
HIGH-Z
HIGH-Z
L
X
X
X
X
X
X
X
X
X
L
Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels.
Notes:
6
1. Other operations except for indicated this column are inhibited.
2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
3. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time.
4. It is also used for the extended sector group protections.
5. Protect of 2 of 8 Kbytes on both ends of each boot sector.
6. SA; Don’t care or Open.
MB84VD23280EA-90/MB84VD23280EE-90
Table 1. 2 User Bus Operations (Flash = Word mode; CIOf = VCCf, SRAM = Byte mode; CIOs = VSS)
Operation (1), (3) CEf CE1s CE2s OE
Full Standby
H
H
Output Disable
L
H
X
X
L
L
H
H
X
X
L
H
X
X
L
H
X
X
L
WE
WP/
UBs DQ7 to DQ0 DQ15 to DQ8 RESET ACC
SA LBs
(6) (6)
(5)
X
X
X
X
X
HIGH-Z
HIGH-Z
H
X
H
H
X
X
X
HIGH-Z
HIGH-Z
X
X
X
X
X
HIGH-Z
HIGH-Z
H
X
H
H
X
X
X
HIGH-Z
HIGH-Z
L
H
X
X
X
DOUT
DOUT
H
X
H
L
X
X
X
DIN
DIN
H
X
Read from Flash
(2)
L
Write to Flash
L
Read from SRAM
H
L
H
L
H
SA
X
X
DOUT
HIGH-Z
H
X
Write to SRAM
H
L
H
X
L
SA
X
X
DIN
HIGH-Z
H
X
Temporary Sector
Group
Unprotection(4)
X
X
X
X
X
X
X
X
X
X
VID
X
Flash Hardware
Reset
X
H
X
X
L
X
X
X
X
X
HIGH-Z
HIGH-Z
L
X
Boot Block Sector
Write Protection
X
X
X
X
X
X
X
X
X
X
X
L
Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels.
Notes:
1. Other operations except for indicated this column are inhibited.
2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
3. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time.
4. It is also used for the extended sector group protections.
5. Protect of 2 of 8 Kbytes on both ends of each boot sector.
6. LBS , UBS; Don’t care or Open.
7
MB84VD23280EA-90/MB84VD23280EE-90
Table 1. 3 User Bus Operations (Flash = Byte mode; CIOf = VSS, SRAM = Byte mode; CIOs = VSS)
UBs
Operation (1), (3) CEf CE1s CE2s DQ15/A–1 OE WE SA LBs
(6) (6)
Full Standby
H
H
Output Disable
L
H
X
X
L
L
H
H
X
X
L
H
X
X
L
H
X
X
L
DQ7 to
DQ0
WP/
DQ14 to RESET ACC
DQ8
(5)
X
X
X
X
X
X
HIGH-Z
HIGH-Z
H
X
X
H
H
X
X
X
HIGH-Z
HIGH-Z
X
X
X
X
X
X
HIGH-Z
HIGH-Z
H
X
A–1
H
H
X
X
X
HIGH-Z
HIGH-Z
A–1
L
H
X
X
X
DOUT
X
H
X
A–1
H
L
X
X
X
DIN
X
H
X
Read from Flash
(2)
L
Write to Flash
L
Read from SRAM
H
L
H
X
L
H
SA
X
X
DOUT
HIGH-Z
H
X
Write to SRAM
H
L
H
X
X
L
SA
X
X
DIN
HIGH-Z
H
X
Temporary Sector
Group
Unprotection(4)
X
X
X
X
X
X
X
X
X
X
X
VID
X
Flash Hardware
Reset
X
H
X
X
L
X
X
X
X
X
X
HIGH-Z
HIGH-Z
L
X
Boot Block Sector
Write Protection
X
X
X
X
X
X
X
X
X
X
X
X
L
Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels.
Notes:
8
1. Other operations except for indicated this column are inhibited.
2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
3. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time.
4. It is also used for the extended sector group protections.
5. Protect of 2 of 8 Kbytes on both ends of each boot sector.
6. LBS , UBS; Don’t care or Open.
MB84VD23280EA-90/MB84VD23280EE-90
■ FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY
• Sixteen 4K words, and one hundred twenty-six 32 K words.
• Individual-sector, multiple-sector, or bulk-erase capability.
Bank A
Bank B
SA0 : 8KB (4KW)
SA1 : 8KB (4KW)
SA2 : 8KB (4KW)
SA3 : 8KB (4KW)
SA4 : 8KB (4KW)
SA5 : 8KB (4KW)
SA6 : 8KB (4KW)
SA7 : 8KB (4KW)
SA8 : 64KB (32KW)
SA9 : 64KB (32KW)
SA10 : 64KB (32KW)
SA11 : 64KB (32KW)
SA12 : 64KB (32KW)
SA13 : 64KB (32KW)
SA14 : 64KB (32KW)
SA15 : 64KB (32KW)
SA16 : 64KB (32KW)
SA17 : 64KB (32KW)
SA18 : 64KB (32KW)
SA19 : 64KB (32KW)
SA20 : 64KB (32KW)
SA21 : 64KB (32KW)
SA22 : 64KB (32KW)
SA23 : 64KB (32KW)
SA24 : 64KB (32KW)
SA25 : 64KB (32KW)
SA26 : 64KB (32KW)
SA27 : 64KB (32KW)
SA28 : 64KB (32KW)
SA29 : 64KB (32KW)
SA30 : 64KB (32KW)
SA31 : 64KB (32KW)
SA32 : 64KB (32KW)
SA33 : 64KB (32KW)
SA34 : 64KB (32KW)
SA35 : 64KB (32KW)
SA36 : 64KB (32KW)
SA37 : 64KB (32KW)
SA38 : 64KB (32KW)
SA39 : 64KB (32KW)
SA40 : 64KB (32KW)
SA41 : 64KB (32KW)
SA42 : 64KB (32KW)
SA43 : 64KB (32KW)
SA44 : 64KB (32KW)
SA45 : 64KB (32KW)
SA46 : 64KB (32KW)
SA47 : 64KB (32KW)
SA48 : 64KB (32KW)
SA49 : 64KB (32KW)
SA50 : 64KB (32KW)
SA51 : 64KB (32KW)
SA52 : 64KB (32KW)
SA53 : 64KB (32KW)
SA54 : 64KB (32KW)
SA55 : 64KB (32KW)
SA56 : 64KB (32KW)
SA57 : 64KB (32KW)
SA58 : 64KB (32KW)
SA59 : 64KB (32KW)
SA60 : 64KB (32KW)
SA61 : 64KB (32KW)
SA62 : 64KB (32KW)
SA63 : 64KB (32KW)
SA64 : 64KB (32KW)
SA65 : 64KB (32KW)
SA66 : 64KB (32KW)
SA67 : 64KB (32KW)
SA68 : 64KB (32KW)
SA69 : 64KB (32KW)
SA70 : 64KB (32KW)
Word Mode Byte Mode
000000h
000000h
002000h
001000h
004000h
002000h
006000h
003000h
008000h
004000h
00A000h
005000h
00C000h
006000h
00E000h
007000h
010000h
008000h
020000h
010000h
030000h
018000h
040000h
020000h
050000h
028000h
060000h
030000h
070000h
038000h
080000h
040000h
090000h
048000h
0A0000h
050000h
0B0000h
058000h
0C0000h
060000h
0D0000h
068000h
0E0000h
070000h
0F0000h
078000h
100000h
080000h
110000h
088000h
120000h
090000h
130000h
098000h
140000h
0A0000h
158000h
0A8000h
160000h
0B0000h
170000h
0B8000h
180000h
0C0000h
190000h
0C8000h
1A0000h
0D0000h
1B0000h
0D8000h
1C0000h
0E0000h
1D0000h
0E8000h
1E0000h
0F0000h
1F0000h
0F8000h
200000h
100000h
210000h
108000h
220000h
110000h
230000h
118000h
240000h
120000h
250000h
128000h
260000h
130000h
270000h
138000h
280000h
140000h
290000h
148000h
2A0000h
150000h
2B0000h
158000h
2C0000h
160000h
2D0000h
168000h
2E0000h
170000h
2F0000h
178000h
300000h
180000h
310000h
188000h
320000h
190000h
330000h
198000h
340000h
1A0000h
350000h
1A8000h
360000h
1B0000h
370000h
1B8000h
380000h
1C0000h
390000h
1C8000h
3A0000h
1D0000h
3B0000h
1D8000h
3C0000h
1E0000h
3D0000h
1E8000h
3E0000h
1F0000h
3F0000h
1F8000h
1FFFFFh 3FFFFFh
Bank C
Bank D
SA71 : 64KB (32KW)
SA72 : 64KB (32KW)
SA73 : 64KB (32KW)
SA74 : 64KB (32KW)
SA75 : 64KB (32KW)
SA76 : 64KB (32KW)
SA77 : 64KB (32KW)
SA78 : 64KB (32KW)
SA79 : 64KB (32KW)
SA80 : 64KB (32KW)
SA81 : 64KB (32KW)
SA82 : 64KB (32KW)
SA83 : 64KB (32KW)
SA84 : 64KB (32KW)
SA85 : 64KB (32KW)
SA86 : 64KB (32KW)
SA87 : 64KB (32KW)
SA88 : 64KB (32KW)
SA89 : 64KB (32KW)
SA90 : 64KB (32KW)
SA91 : 64KB (32KW)
SA92 : 64KB (32KW)
SA93 : 64KB (32KW)
SA94 : 64KB (32KW)
SA95 : 64KB (32KW)
SA96 : 64KB (32KW)
SA97 : 64KB (32KW)
SA98 : 64KB (32KW)
SA99 : 64KB (32KW)
SA100 : 64KB (32KW)
SA101 : 64KB (32KW)
SA102 : 64KB (32KW)
SA103 : 64KB (32KW)
SA104 : 64KB (32KW)
SA105 : 64KB (32KW)
SA106 : 64KB (32KW)
SA107 : 64KB (32KW)
SA108 : 64KB (32KW)
SA109 : 64KB (32KW)
SA110 : 64KB (32KW)
SA111 : 64KB (32KW)
SA112 : 64KB (32KW)
SA113 : 64KB (32KW)
SA114 : 64KB (32KW)
SA115 : 64KB (32KW)
SA116 : 64KB (32KW)
SA117 : 64KB (32KW)
SA118 : 64KB (32KW)
SA119 : 64KB (32KW)
SA120 : 64KB (32KW)
SA121 : 64KB (32KW)
SA122 : 64KB (32KW)
SA123 : 64KB (32KW)
SA124 : 64KB (32KW)
SA125 : 64KB (32KW)
SA126 : 64KB (32KW)
SA127 : 64KB (32KW)
SA128 : 64KB (32KW)
SA129 : 64KB (32KW)
SA130 : 64KB (32KW)
SA131 : 64KB (32KW)
SA132 : 64KB (32KW)
SA133 : 64KB (32KW)
SA134 : 8KB (4KW)
SA135 : 8KB (4KW)
SA136 : 8KB (4KW)
SA137 : 8KB (4KW)
SA138 : 8KB (4KW)
SA139 : 8KB (4KW)
SA140 : 8KB (4KW)
SA141 : 8KB (4KW)
Word Mode
200000h
208000h
210000h
218000h
220000h
228000h
230000h
238000h
240000h
248000h
250000h
258000h
260000h
268000h
270000h
278000h
280000h
288000h
290000h
298000h
2A0000h
2A8000h
2B0000h
2B8000h
2C0000h
2C8000h
2D0000h
2D8000h
2E0000h
2E8000h
2F0000h
2F8000h
300000h
308000h
310000h
318000h
320000h
328000h
330000h
338000h
340000h
348000h
350000h
358000h
360000h
368000h
370000h
378000h
380000h
388000h
390000h
398000h
3A0000h
3A8000h
3B0000h
3B8000h
3C0000h
3C8000h
3D0000h
3D8000h
3E0000h
3E8000h
3F0000h
3F8000h
3F9000h
3FA000h
3FB000h
3FC000h
3FD000h
3FE000h
3FF000h
3FFFFFh
Byte Mode
400000h
410000h
420000h
430000h
440000h
450000h
460000h
470000h
480000h
490000h
4A0000h
4B0000h
4C0000h
4D0000h
4E0000h
4F0000h
500000h
510000h
520000h
530000h
540000h
550000h
560000h
570000h
580000h
590000h
5A0000h
5B0000h
5C0000h
5D0000h
5E0000h
5F0000h
600000h
610000h
620000h
630000h
640000h
650000h
660000h
670000h
680000h
690000h
6A0000h
6B0000h
6C0000h
6D0000h
6E0000h
6F0000h
700000h
710000h
720000h
730000h
740000h
750000h
760000h
770000h
780000h
790000h
7A0000h
7B0000h
7C0000h
7D0000h
7E0000h
7F0000h
7F2000h
7F4000h
7F6000h
7F8000h
7FA000h
7FC000h
7FE000h
7FFFFFh
MB84VD23280EA/EE Sector Architecture
9
MB84VD23280EA-90/MB84VD23280EE-90
Table 2 Example of Virtual Banks Combination
Bank 1
Bank
Splits Volume Combination
Bank 2
Sector Size
Volume Combination
Sector Size
Bank B
+
Bank C
+
Bank D
8 of 8 Kbyte / 4 K word
+
111 of 64 Kbyte / 32 K word
1
8M bit
Bank A
8 of 8 Kbyte / 4 K word
+
56 Mbit
15 of 64 Kbyte / 32 K word
2
16 Mbit
Bank A
+
Bank D
16 of 8 Kbyte / 4 K word
+
48 Mbit
30 of 64 Kbyte / 32 K word
Bank B
+
Bank C
96 of 64 Kbyte / 32 K word
16 of 8 Kbyte / 4 K word
+
78 of 64 Kbyte / 32 K word
8 of 8 Kbyte / 4 K word
+
63 of 64 Kbyte / 32 K word
3
24 Mbit
Bank B
48 of 64 Kbyte / 32 K word 40 Mbit
Bank A
+
Bank C
+
Bank D
4
32 Mbit
Bank A
+
Bank B
8 of 8 Kbyte / 4 K word
+
32 Mbit
63 of 64 Kbyte / 32 K word
Bank C
+
Bank D
BankA: Address 000000h to 07FFFFh (Word) , 000000h to 0FFFFFh (Byte)
BankB: Address 080000h to 1FFFFFh (Word) , 100000h to 3FFFFFh (Byte)
BankC: Address 200000h to 37FFFFh (Word) , 400000h to 6FFFFFh (Byte)
BankD: Address 380000h to 3FFFFFh (Word) , 700000h to 7FFFFFh (Byte)
Table 3 Sector Address Tables
Sector Address
Bank
Bank A
Sector Bank Address
A21 A20 A19 A18
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Address Range
A17
A16
A15
A14
A13
A12
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Byte Mode
Word Mode
000000h to 001FFFh
002000h to 003FFFh
004000h to 005FFFh
006000h to 007FFFh
008000h to 009FFFh
00A000h to 00BFFFh
00C000h to 00DFFFh
00E000h to 00FFFFh
010000h to 01FFFFh
020000h to 02FFFFh
030000h to 03FFFFh
040000h to 04FFFFh
050000h to 05FFFFh
060000h to 06FFFFh
070000h to 07FFFFh
080000h to 08FFFFh
090000h to 09FFFFh
0A0000h to 0AFFFFh
0B0000h to 0BFFFFh
0C0000h to 0CFFFFh
0D0000h to 0DFFFFh
0E0000h to 0EFFFFh
0F0000h to 0FFFFFh
000000h to 000FFFh
001000h to 001FFFh
002000h to 002FFFh
003000h to 003FFFh
004000h to 004FFFh
005000h to 005FFFh
006000h to 006FFFh
007000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
(Continued)
10
MB84VD23280EA-90/MB84VD23280EE-90
(Continued)
Sector Address
Bank
Bank B
Sector Bank Address
A21 A20 A19 A18
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Address Range
A17
A16
A15
A14
A13
A12
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Byte Mode
Word Mode
100000h to 10FFFFh
110000h to 11FFFFh
120000h to 12FFFFh
130000h to 13FFFFh
140000h to 14FFFFh
150000h to 15FFFFh
160000h to 16FFFFh
170000h to 17FFFFh
180000h to 18FFFFh
190000h to 19FFFFh
1A0000h to 1AFFFFh
1B0000h to 1BFFFFh
1C0000h to 1CFFFFh
1D0000h to 1DFFFFh
1E0000h to 1EFFFFh
1F0000h to 1FFFFFh
200000h to 20FFFFh
210000h to 21FFFFh
220000h to 22FFFFh
230000h to 23FFFFh
240000h to 24FFFFh
250000h to 25FFFFh
260000h to 26FFFFh
270000h to 27FFFFh
280000h to 28FFFFh
290000h to 29FFFFh
2A0000h to 2AFFFFh
2B0000h to 2BFFFFh
2C0000h to 2CFFFFh
2D0000h to 2DFFFFh
2E0000h to 2EFFFFh
2F0000h to 2FFFFFh
300000h to 30FFFFh
310000h to 31FFFFh
320000h to 32FFFFh
330000h to 33FFFFh
340000h to 34FFFFh
350000h to 35FFFFh
360000h to 36FFFFh
370000h to 37FFFFh
380000h to 38FFFFh
390000h to 39FFFFh
3A0000h to 3AFFFFh
3B0000h to 3BFFFFh
3C0000h to 3CFFFFh
3D0000h to 3DFFFFh
3E0000h to 3EFFFFh
3F0000h to 3FFFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0FFFFFh
100000h to 107FFFh
108000h to 10FFFFh
110000h to 117FFFh
118000h to 11FFFFh
120000h to 127FFFh
128000h to 12FFFFh
130000h to 137FFFh
138000h to 13FFFFh
140000h to 147FFFh
148000h to 14FFFFh
150000h to 157FFFh
158000h to 15FFFFh
160000h to 167FFFh
168000h to 16FFFFh
170000h to 177FFFh
178000h to 17FFFFh
180000h to 187FFFh
188000h to 18FFFFh
190000h to 197FFFh
198000h to 19FFFFh
1A0000h to 1A7FFFh
1A8000h to 1AFFFFh
1B0000h to 1B7FFFh
1B8000h to 1BFFFFh
1C0000h to 1C7FFFh
1C8000h to 1CFFFFh
1D0000h to 1D7FFFh
1D8000h to 1DFFFFh
1E0000h to 1E7FFFh
1E8000h to 1EFFFFh
1F0000h to 1F7FFFh
1F8000h to 1FFFFFh
(Continued)
11
MB84VD23280EA-90/MB84VD23280EE-90
(Continued)
Sector Address
Bank
Bank C
Sector Bank Address
A21 A20 A19 A18
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Address Range
A17
A16
A15
A14
A13
A12
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Byte Mode
Word Mode
400000h to 40FFFFh
410000h to 41FFFFh
420000h to 42FFFFh
430000h to 43FFFFh
440000h to 44FFFFh
450000h to 45FFFFh
460000h to 46FFFFh
470000h to 47FFFFh
480000h to 48FFFFh
490000h to 49FFFFh
4A0000h to 4AFFFFh
4B0000h to 4BFFFFh
4C0000h to 4CFFFFh
4D0000h to 4DFFFFh
4E0000h to 4EFFFFh
4F0000h to 4FFFFFh
500000h to 50FFFFh
510000h to 51FFFFh
520000h to 52FFFFh
530000h to 53FFFFh
540000h to 54FFFFh
550000h to 55FFFFh
560000h to 56FFFFh
570000h to 57FFFFh
580000h to 58FFFFh
590000h to 59FFFFh
5A0000h to 5AFFFFh
5B0000h to 5BFFFFh
5C0000h to 5CFFFFh
5D0000h to 5DFFFFh
5E0000h to 5EFFFFh
5F0000h to 5FFFFFh
600000h to 60FFFFh
610000h to 61FFFFh
620000h to 62FFFFh
630000h to 63FFFFh
640000h to 64FFFFh
650000h to 65FFFFh
660000h to 66FFFFh
670000h to 67FFFFh
680000h to 68FFFFh
690000h to 69FFFFh
6A0000h to 6AFFFFh
6B0000h to 6BFFFFh
6C0000h to 6CFFFFh
6D0000h to 6DFFFFh
6E0000h to 6EFFFFh
6F0000h to 6FFFFFh
200000h to 207FFFh
208000h to 20FFFFh
210000h to 217FFFh
218000h to 21FFFFh
220000h to 227FFFh
228000h to 22FFFFh
230000h to 237FFFh
238000h to 23FFFFh
240000h to 247FFFh
248000h to 24FFFFh
250000h to 257FFFh
258000h to 25FFFFh
260000h to 267FFFh
268000h to 26FFFFh
270000h to 277FFFh
278000h to 27FFFFh
280000h to 287FFFh
288000h to 28FFFFh
290000h to 297FFFh
298000h to 29FFFFh
2A0000h to 2A7FFFh
2A8000h to 2AFFFFh
2B0000h to 2B7FFFh
2B8000h to 2BFFFFh
2C0000h to 2C7FFFh
2C8000h to 2CFFFFh
2D0000h to 2D7FFFh
2D8000h to 2DFFFFh
2E0000h to 2E7FFFh
2E8000h to 2EFFFFh
2F0000h to 2F7FFFh
2F8000h to 2FFFFFh
300000h to 307FFFh
308000h to 30FFFFh
310000h to 317FFFh
318000h to 31FFFFh
320000h to 327FFFh
328000h to 32FFFFh
330000h to 337FFFh
338000h to 33FFFFh
340000h to 347FFFh
348000h to 34FFFFh
350000h to 357FFFh
358000h to 35FFFFh
360000h to 367FFFh
368000h to 36FFFFh
370000h to 377FFFh
378000h to 37FFFFh
(Continued)
12
MB84VD23280EA-90/MB84VD23280EE-90
(Continued)
Sector Address
Bank
Bank D
Sector Bank Address
A21 A20 A19 A18
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Address Range
A17
A16
A15
A14
A13
A12
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
Byte Mode
Word Mode
700000h to 70FFFFh
710000h to 71FFFFh
720000h to 72FFFFh
730000h to 73FFFFh
740000h to 74FFFFh
750000h to 75FFFFh
760000h to 76FFFFh
770000h to 77FFFFh
780000h to 78FFFFh
790000h to 79FFFFh
7A0000h to 7AFFFFh
7B0000h to 7BFFFFh
7C0000h to 7CFFFFh
7D0000h to 7DFFFFh
7E0000h to 7EFFFFh
7F0000h to 7F1FFFh
7F2000h to 7F3FFFh
7F4000h to 7F5FFFh
7F6000h to 7F7FFFh
7F8000h to 7F9FFFh
7FA000h to 7FBFFFh
7FC000h to 7FDFFFh
7FE000h to 7FFFFFh
380000h to 387FFFh
388000h to 38FFFFh
390000h to 397FFFh
398000h to 39FFFFh
3A0000h to 3A7FFFh
3A8000h to 3AFFFFh
3B0000h to 3B7FFFh
3B8000h to 3BFFFFh
3C0000h to 3C7FFFh
3C8000h to 3CFFFFh
3D0000h to 3D7FFFh
3D8000h to 3DFFFFh
3E0000h to 3E7FFFh
3E8000h to 3EFFFFh
3F0000h to 3F7FFFh
3F8000h to 3F8FFFh
3F9000h to 3F9FFFh
3FA000h to 3FAFFFh
3FB000h to 3FBFFFh
3FC000h to 3FCFFFh
3FD000h to 3FDFFFh
3FE000h to 3FEFFFh
3FF000h to 3FFFFFh
13
MB84VD23280EA-90/MB84VD23280EE-90
Table 4 Sector Group Addresses (MB84VD23280EA/EE)
14
Sector Group
SGA0
SGA1
SGA2
SGA3
SGA4
SGA5
SGA6
SGA7
A21
0
0
0
0
0
0
0
0
A20
0
0
0
0
0
0
0
0
A19
0
0
0
0
0
0
0
0
A18
0
0
0
0
0
0
0
0
A17
0
0
0
0
0
0
0
0
SGA8
0
0
0
0
0
SGA9
SGA10
SGA11
SGA12
SGA13
SGA14
SGA15
SGA16
SGA17
SGA18
SGA19
SGA20
SGA21
SGA22
SGA23
SGA24
SGA25
SGA26
SGA27
SGA28
SGA29
SGA30
SGA31
SGA32
SGA33
SGA34
SGA35
SGA36
SGA37
SGA38
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
SGA39
1
1
1
1
1
SGA40
SGA41
SGA42
SGA43
SGA44
SGA45
SGA46
SGA47
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A16
0
0
0
0
0
0
0
0
0
0
1
A15
0
0
0
0
0
0
0
0
0
1
0
A14
0
0
0
0
1
1
1
1
A13
0
0
1
1
0
0
1
1
A12
0
1
0
1
0
1
0
1
Sectors
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
X
X
X
SA8 to SA10
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA11 to SA14
SA15 to SA18
SA19 to SA22
SA23 to SA26
SA27 to SA30
SA31 to SA34
SA35 to SA38
SA39 to SA42
SA43 to SA46
SA47 to SA50
SA51 to SA54
SA55 to SA58
SA59 to SA62
SA63 to SA66
SA67 to SA70
SA71 to SA74
SA75 to SA78
SA79 to SA82
SA83 to SA86
SA87 to SA90
SA91 to SA94
SA95 to SA98
SA99 to SA102
SA103 to SA106
SA107 to SA110
SA111 to SA114
SA115 to SA118
SA119 to SA122
SA123 to SA126
SA127 to SA130
0
0
1
1
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
1
1
X
X
X
SA131 to SA133
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
MB84VD23280EA-90/MB84VD23280EE-90
Table 5 Flash Memory Autoselect Codes
A21 to A12
Type
Manufacture’s Code
Device Code
Byte
Word
Byte
Extended Device
Code *4
Word
Byte
Word
Sector Group Protection
A6
A3
A2
A1
A0
A-1*1
Code (HEX)
3
VIL
VIL
VIL
VIL
VIL
VIL
04h
BA*3
VIL
VIL
VIL
VIL
VIH
VIL
7Eh
X
227Eh
BA*3
VIL
VIH
VIH
VIH
VIL
VIL
02h
X
2202h
BA*3
VIL
VIH
VIH
VIH
VIH
VIL
01h
X
2201h
Sector Group
Addresses
VIL
VIL
VIL
VIH
VIL
VIL
01h*2
BA*
*1 : A-1 is for Byte mode.
*2 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.
*3 : When VID is applied, both Bank 1 and Bank 2 become Autoselect mode, which leads to the simultaneous operation
unable to be executed. Consequently, specifying the bank address is not demanded. However, the bank address
needs to be indicated when Autoselect mode is read out at command mode; because then it becomes OK to
activate simultaneous operation.
*4 : At WORD mode, a read cycle at address (BA) 01h (at BYTE mode, (BA) 02h) outputs device code. When 227Eh
(at BYTE mode, 7Eh) was output, this indicates that there will require two additional codes, called Extended
Device Codes. Therefore the system may continue reading out these Extended Device Codes at the address of
(BA) 0Eh (at BYTE mode, (BA) 1Ch) , as well as at (BA) 0Fh (at BYTE mode, (BA) 1Eh) .
15
MB84VD23280EA-90/MB84VD23280EE-90
Table 6 Flash Memory Command Definitions
Command
Sequence
Read/Reset
Read/Reset
Word
Byte
Word
Byte
Bus
Write
Cycles
Req’d
1
3
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
XXXh
555h
AAAh
3
Autoselect
Byte
AAh
4
—
2AAh
555h
AAh
555h
AAAh
—
55h
2AAh
AAAh
Byte
Word
F0h
555h
Word
Program
Bus
First Bus Second Bus Third Bus Fourth
Fifth Bus
Sixth Bus
Read/Write
Write Cycle Write Cycle Write Cycle
Write Cycle Write Cycle
Cycle
55h
555h
AAh
2AAh
555h
55h
—
555h
AAAh
(BA)
555h
(BA)
AAAh
555h
AAAh
—
—
—
—
—
—
—
F0h
RA
RD
—
—
—
—
90h
—
—
—
—
—
—
A0h
PA
PD
—
—
—
—
Program Suspend
1
BA
B0h
—
—
—
—
—
—
—
—
—
—
Program Resume
1
BA
30h
—
—
—
—
—
—
—
—
—
—
Chip Erase
Sector Erase
Word
Byte
Word
Byte
6
6
555h
AAAh
555h
AAAh
AAh
AAh
2AAh
555h
2AAh
555h
55h
55h
555h
AAAh
555h
AAAh
80h
80h
555h
AAAh
555h
AAAh
AAh
AAh
2AAh
555h
2AAh
555h
55h
555h
AAAh
10h
55h
SA
30h
Erase Suspend
1
BA
B0h
—
—
—
—
—
—
—
—
—
—
Erase Resume
1
BA
30h
—
—
—
—
—
—
—
—
—
—
4
XXXh
60h
SPA
60h
SPA
40h
SPA
SD
—
—
—
—
20h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
88h
—
—
—
—
—
—
PA
PD
—
—
—
—
XXXh
00h
—
—
—
—
Extended
Sector Group
Protection *2
Set to
Fast Mode
Word
Byte
Word
Byte
Fast
Program *1
Word
Reset from
Fast Mode *1
Word
Byte
Byte
3
2
2
Word
1
Query
Byte
Hi-ROM
Entry
Hi-ROM
Program *3
Hi-ROM
Exit *3
Word
Byte
Word
Byte
3
4
555h
AAAh
XXXh
XXXh
BA
BA
(BA)
55h
(BA)
AAh
555h
AAAh
555h
AAAh
A0h
90h
98h
AAh
AAh
555h
Word
4
Byte
AAh
2AAh
555h
PA
XXXh
PD
*4
XXXh
F0h
—
—
2AAh
555h
2AAh
555h
55h
55h
55h
555h
555h
AAAh
555h
AAAh
555h
AAAh
A0h
(HRA)
(HRBA)
2AAh
AAh
AAAh
55h
555h
(HRBA)
90h
AAAh
(Continued)
16
MB84VD23280EA-90/MB84VD23280EE-90
(Continued)
*1: This command is valid while Fast Mode.
*2: This command is valid while RESET = VID.
*3: This command is valid while Hi-ROM mode.
*4: The data “00h” is also acceptable.
Notes: 1. Address bits A21 to A11 = X = “H” or “L” for all address commands except or Program Address (PA),
Sector Address (SA), and Bank Address (BA), and Sector Group Address (SPA).
2. Bus operations are defined in Tables 3 and 4.
3. RA =Address of the memory location to be read
PA = Address of the memory location to be programmed
Addresses are latched on the falling edge of the write pulse.
SA = Address of the sector to be erased. The combination of A21, A20, A19, A18, A17, A16, A15, A14, A13, and
A12 will uniquely select any sector.
BA = Bank Address (A21, A20, A19)
4. RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the falling edge of write pulse.
5. SPA =Sector group address to be protected. Set sector group address and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0).
SD = Sector group protection verify data. Output 01h at protected sector group addresses and output
00h at unprotected sector group addresses.
6. HRA = Address of the Hi-ROM area Word Mode:000000h to 00007Fh
Byte Mode:000000h to 0000FFh
7. HRBA = Bank Address of the Hi-ROM area (A21 = A20 = A19 = VIL)
8. The system should generate the following address patterns:
Word Mode: 555h or 2AAh to addresses A10 to A0
Byte Mode: AAAh or 555h to addresses A10 to A0, and A-1
9. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
17
MB84VD23280EA-90/MB84VD23280EE-90
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Symbol
Unit
Min.
Max.
Tstg
–55
+125
°C
Ta
–25
+85
°C
VIN, VOUT
–0.3
VCCf +0.3
V
VCCs +0.3
V
VCCf, VCCs
–0.3
+4.0
V
A9 and OE *
VIN
–0.3
+ 13.0
V
RESET *2
VIN
–0.5
+ 13.0
V
WP/ACC *3
VIN
–0.5
+10.5
V
Storage Temperature
Ambient Temperature with Power Applied
Voltage with Respect to Ground All pins
except A9,OE,RESET,WP/ACC *1
VCCf/VCCs Supply *
1
2
*1 Minimum DC voltage on input or I/O pins is –0.3 V. During voltage transitions, input or I/O pins may undershoot
VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf + 0.3 V or VCCs + 0.3
V. During voltage transitions, input or I/O pins may overshoot to VCCf + 2.0 V or VCCs + 2.0 V for periods of up to
20 ns.
*2: Minimum DC input voltage on A9 and OE pin is –0.3 V. Minimum DC input voltage on RESET pin is –0.5 V. During
voltage transitions, A9, OE, and RESET pins may undershoot VSS to –2.0 V for periods of up to 20 ns.
Voltage difference between input and supply voltage (VIN-VCCf or VCCs) does not exceed +9.0 V.
Maximum DC input voltage on A9, OE, and RESET pins is +13.0 V which may overshoot to +14.0 V for periods
of up to 20 ns.
*3: Minimum DC input voltage on WP/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may undershoot
Vss to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may
overshoot to +12.0 V for periods of up to 20 ns, when VCCf is applied.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Ambient Temperature
VCCf/VCCs Supply Voltages
Symbol
Value
Unit
Min.
Max.
Ta
–25
+85
°C
VCCf, VCCs
+2.7
+3.3
V
Note: Operating ranges define those limits between which the functionality of the device is guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
18
MB84VD23280EA-90/MB84VD23280EE-90
■ ELECTRICAL CHARACTERRISTICS
1. DC Characteristics
Parameter
Value
Conditions
Symbol
Min.
Typ.
Max.
Unit
Input Leakage Current
ILI
VIN = VSS to VCCf, VCCs
–1.0
—
+1.0
µA
Output Leakage Current
ILO
VOUT = VSS to VCCf, VCCs
–1.0
—
+1.0
µA
RESET Inputs Leakage
Current
ILIT
VCCf = VCCf Max., VCCs = VCCs Max.,
RESET = 12.5 V
—
—
35
µA
ACC Input Leakage Current
ILIA
VCCf = VCCf Max., VCCs = VCCs Max.,
WP/ACC = VACC Max.
—
—
20
mA
tCYCLE = 5 MHz Byte
—
—
16
tCYCLE = 5 MHz Word
—
—
18
tCYCLE = 1 MHz Byte
—
—
7
tCYCLE = 1 MHz Word
—
—
7
—
—
35
Byte
—
—
51
Word
—
—
53
Byte
—
—
51
Word
—
—
53
—
—
35
mA
tCYCLE =10 MHz
—
—
50
mA
tCYCLE = 10 MHz
—
—
50
mA
tCYCLE = 1 MHz
—
—
10
mA
Flash VCC Active Current
(Read) *1
ICC1f
CEf = VIL,
OE = VIH
mA
mA
Flash VCC Active Current
(Program/Erase) *2
ICC2f
CEf = VIL, OE = VIH
Flash VCC Active Current
(Read-While-Program) *5
ICC3f
CEf = VIL, OE = VIH
Flash VCC Active Current
(Read-While-Erase) *5
ICC4f
CEf = VIL, OE = VIH
Flash VCC Active Current
(Erase-Suspend-Program)
ICC5f
CEf = VIL, OE = VIH
SRAM VCC Active Current
ICC1s
VCCs = VCC Max.,
CE1s = VIL,
CE2s = VIH
SRAM VCC Active Current
ICC2s
CE1s = 0.2 V,
CE2s = VCCs –
0.2 V
Flash VCC Standby Current
ISB1f
VCCf = VCCf Max., CEf = VCCf ± 0.3 V
RESET = VCCf ± 0.3 V,
WP/ACC = VCCf± 0.3 V
—
—
5
µA
Flash VCC Standby Current
(RESET)
ISB2f
VCCf = VCCf Max., RESET = VSS ± 0.3 V,
WP/ACC = VCCf± 0.3 V
—
—
5
µA
Flash VCC Current (Automatic Sleep Mode) *3
ISB3f
VCCf = VCCf Max., CEf = VSS ± 0.3 V
RESET = VCCf ± 0.3 V,
WP/ACC = VCCf± 0.3 V,
VIN = VCCf± 0.3 V or VSS ± 0.3 V
—
—
5
µA
SRAM VCC Standby
Current
ISB1s
CE1s > VCCs – 0.2 V, CE2s > VCCs – 0.2 V
—
—
25
µA
SRAM VCC Standby
Current
ISB2s
CE2s < 0.2V
—
—
25
µA
mA
mA
mA
(Continued)
19
MB84VD23280EA-90/MB84VD23280EE-90
(Continued)
Symbol
Conditions
Input Low Level
VIL
Input High Level
Voltage for Sector Protection,
and Temporary Sector Unprotection (RESET) *4
Parameter
Value
Unit
Min.
Typ.
Max.
—
–0.3
—
0.5
VIH
—
2.4
—
VCC+0.3 *
VID
—
11.5
—
12.5
V
Voltage for Program
Acceleration (WP/ACC) *4
VACC
—
8.5
9.0
9.5
V
Output Low Voltage Level
VOL
Flash
—
—
0.45
V
VCCs = VCCs Min., IOL=1.0 mA SRAM
—
—
0.4
V
VCCf = VCCf Min., IOH=–0.1 mA Flash
VCCf–
0.4
—
—
V
2.2
—
—
V
2.3
—
2.5
V
Output High Voltage Level
VOH
VCCf = VCCf Min., IOL=4.0 mA
VCCs = VCCs Min., IOH=–0.5 mA
Flash Low VCCf Lock-Out
Voltage
VLKO
SRAM
—
V
6
*1: The ICC current listed includes both the DC operating current and the frequency dependent component.
*2: ICC active while Embedded Algorithm (program or erase) is in progress.
*3: Automatic sleep mode enables the low power mode when address remains stable for 150 ns.
*4: Applicable for only VCCf applying.
*5: Embedded Alogorithm (program or erase) is in progress. (@5 MHz)
*6: VCC indicates lower of VCCf or VCCs.
20
V
MB84VD23280EA-90/MB84VD23280EE-90
2. AC Characteristics
• CE Timing
Parameter
Symbol
JEDEC
Standard
CE Recover Time
—
tCCR
CE Hold Time
—
tCHOLD
Condition
Value
Unit
Min.
Max.
—
0
—
ns
—
3
—
ns
• Timing Diagram for alternating SRAM to Flash
CEf
tCCR
tCCR
CE1s
WE
tCHOLD
tCCR
tCHOLD
tCCR
CE2s
21
MB84VD23280EA-90/MB84VD23280EE-90
• Read Only Operations Characteristics (Flash)
Symbol
Parameter
JEDEC
Standard
Value (Note)
Min.
Max.
Unit
Read Cycle Time
tAVAV
tRC
—
90
—
ns
Address to Output Delay
tAVQV
tACC
CEf = VIL
OE = VIL
—
90
ns
Chip Enable to Output Delay
tELQV
tCEf
OE = VIL
—
90
ns
Output Enable to Output Delay
tGLQV
tOE
—
—
35
ns
Chip Enable to Output High-Z
tEHQZ
tDF
—
—
30
ns
Output Enable to Output High-Z
tGHQZ
tDF
—
—
30
ns
Output Hold Time From Addresses,
CEf or OE, Whichever Occurs First
tAXQX
tOH
—
0
—
ns
—
tREADY
—
—
20
µs
RESET Pin Low to Read Mode
Note: Test Conditions– Output Load:1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to VCCf
Timing measurement reference level
Input: 0.5×VCCf
Output: 0.5×VCCf
22
Condition
MB84VD23280EA-90/MB84VD23280EE-90
• Read Cycle (Flash)
tRC
Addresses Stable
Address
tACC
CEf
tOE
tDF
OE
tOEH
WE
tCEf
HIGH-Z
DQ
HIGH-Z
Output Valid
tRC
Address
Addresses Stable
tACC
CEf
tRH
tRP
tRH
tCEf
RESET
tOH
DQ
HIGH-Z
Output Valid
23
MB84VD23280EA-90/MB84VD23280EE-90
• Erase/Program Operations (Flash)
Parameter
Symbol
Value
Unit
JEDEC
Standard
Min.
Typ.
Max.
Write Cycle Time
tAVAV
tWC
90
—
—
ns
Address Setup Time (WE to Addr.)
tAVWL
tAS
0
—
—
ns
—
tASO
15
—
—
ns
tWLAX
tAH
45
—
—
ns
—
tAHT
0
—
—
ns
Address Setup Time to CEf Low During Toggle Bit Polling
Address Hold Time (WE to Addr.)
Address Hold Time from CEf or OE High During Toggle Bit Polling
Data Setup Time
tDVWH
tDS
35
—
—
ns
Data Hold Time
tWHDX
tDH
0
—
—
ns
—
tOEH
—
Output Enable Hold Time
Read
Toggle and Data Polling
CEf High During Toggle Bit Polling
OE High During Toggle Bit Polling
0
—
—
ns
10
—
—
ns
tCEPH
20
—
—
ns
—
tOEPH
20
—
—
ns
Read Recover Time Before Write (OE to CEf)
tGHEL
tGHEL
0
—
—
ns
Read Recover Time Before Write (OE to WE)
tGHWL
tGHWL
0
—
—
ns
WE Setup Time (CEf to WE)
tWLEL
tWS
0
—
—
ns
CEf Setup Time (WE to CEf)
tELWL
tCS
0
—
—
ns
WE Hold Time (CEf to WE)
tEHWH
tWH
0
—
—
ns
CEf Hold Time (WE to CEf)
tWHEH
tCH
0
—
—
ns
Write Pulse Width
tWLWH
tWP
35
—
—
ns
CEf Pulse Width
tELEH
tCP
35
—
—
ns
Write Pulse Width High
tWHWL
tWPH
30
—
—
ns
CEf Pulse Width High
Word Programming Operation
tEHEL
tCPH
30
—
—
ns
tWHWH1
tWHWH1
—
16
—
µs
tWHWH2
tWHWH2
—
1
—
s
VCCf Setup Time
—
tVCS
50
—
—
µs
Voltage Transition Time *2
—
tVLHT
4
—
—
µs
Rise Time to VID *2
—
tVIDR
500
—
—
ns
Rise Time to VACC
—
tVACCR
500
—
—
ns
Recover Time from RY/BY
—
tRB
0
—
—
ns
RESET Pulse Width
—
tRP
500
—
—
ns
Delay Time from Embedded Output Enable
—
tEOE
—
—
90
ns
Sector Erase Operation *
1
RESET High Level Period Before Read
—
tRH
200
—
—
ns
Program/Erase Valid to RY/BY Delay
—
tBUSY
—
—
90
ns
Erase Time-out Time *3
—
tTOW
50
—
—
µs
—
tSPD
—
—
20
µs
Erase Suspend Transition Time *
4
*1: This does not include the preprogramming time.
*2: This timing is for Sector group Protection Operation.
*3: The time between writes must be less than “tTOW” otherwise that command will not be accepted and erasure will
start. A time-out or “tTOW” from the rising edge of last CEf or WE whichever happens first will initiate the execution
of the Sector Erase command(s).
*4: When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of “tSPD” to suspend the erase operation.
24
MB84VD23280EA-90/MB84VD23280EE-90
• Write Cycle (WE control) (Flash)
3rd Bus Cycle
Data Polling
555h
Address
tWC
PA
tAS
PA
tRC
tAH
CEf
tCH
tCS
tCEf
OE
tGHWL
tWP
tOE
tWHWH1
tWPH
WE
tOH
tDS
tDH
DQ
Notes: 1.
2.
3.
4.
5.
6.
A0h
PD
DQ7
DOUT
DOUT
PA is address of the memory location to be programmed.
PD is data to be programmed at byte address.
DQ7 is the output of the complement of the data written to the device.
DOUT is the output of the data written to the device.
Figure indicates last two bus cycles out of four bus cycle sequence.
These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
25
MB84VD23280EA-90/MB84VD23280EE-90
• Write Cycle (CEf control) (Flash)
3rd Bus Cycle
Address
Data Polling
PA
555h
tWC
tAS
PA
tAH
WE
tWS
tWH
OE
tGHEL
tCP
tWHWH1
tCPH
CEf
tDS
tDH
DQ
Notes: 1.
2.
3.
4.
5.
6.
26
A0h
PD
DQ7
DOUT
PA is address of the memory location to be programmed.
PD is data to be programmed at byte address.
DQ7 is the output of the complement of the data written to the device.
DOUT is the output of the data written to the device.
Figure indicates last two bus cycles out of four bus cycle sequence.
These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
MB84VD23280EA-90/MB84VD23280EE-90
• AC Waveforms Chip/Sector Erase Operations (Flash)
2AAh
555h
Address
tWC
tAS
555h
SA*
2AAh
555h
tAH
CEf
tCS
tCH
OE
tGHWL
tWP
tWPH
WE
tDS
tDH
AAh
DQ
30h for Sector Erase
55h
80h
AAh
55h
10h/
30h
tVCS
VCCf
*: SA is the sector address for Sector Erase. Addresses = 555h for Chip Erase.
Note: These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
27
MB84VD23280EA-90/MB84VD23280EE-90
• AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)
CEf
tCH
tDF
tOE
OE
tOEH
WE
tCEf
*
DQ7
DQ7 =
Valid Data
DQ7
Data In
High-Z
tWHWH1 or tWHWH2
DQ6 to DQ0
DQ6 to DQ0 = Output Flag
Data In
tBUSY
tEOE
RY/BY
*: DQ7 = Valid Data (The device has completed the Embedded operation.)
28
DQ6 to DQ0
Valid Data
High-Z
MB84VD23280EA-90/MB84VD23280EE-90
• AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash)
Address
tAHT
tASO
tAHT
tAS
CEf
tCEPH
WE
tOEH
tOEH
tOEPH
OE
tDH
DQ6/DQ2
Data
tOE
Toggle
Data
tCEf
Toggle
Data
*
Toggle
Data
Stop
Toggling
Output
Valid
tBUSY
RY/BY
*: DQ6 stops toggling (The device has completed the Embedded operation).
29
MB84VD23280EA-90/MB84VD23280EE-90
• Back-to-back Read/Write Timing Diagram (Flash)
Address
Read
Command
Read
Command
Read
Read
tRC
tWC
tRC
tWC
tRC
tRC
BA1
BA2
(555h)
BA1
BA2
(PA)
BA1
BA2
(PA)
tAS
tACC
tAH
tAS
tAHT
tCEf
CE
tOE
tCEPH
OE
tGHWL
tDF
tOEH
tWP
WE
tDS
DQ
Valid
Output
tDH
Valid
Intput
(A0h)
tDF
Valid
Output
Valid
Intput
(PD)
Valid
Output
Status
Note: This is an example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.
BA1: Address of Bank 1.
BA2: Address of Bank 2.
30
MB84VD23280EA-90/MB84VD23280EE-90
• RY/BY Timing Diagram during Write/Erase Operations (Flash)
CEf
The rising edge of the last write pulse
WE
Entire programming
or erase operations
RY/BY
tBUSY
• RESET, RY/BY Timing Diagram (Flash)
WE
RESET
tRP
tRB
RY/BY
tREADY
31
MB84VD23280EA-90/MB84VD23280EE-90
• Temporary Sector Unprotection (Flash)
VCCf
tVIDR
tVCS
tVLHT
VID
3V
VIH
RESET
CEf
WE
tVLHT
tVLHT
Program or Erase Command Sequence
RY/BY
Unprotection Period
• Acceleration Mode Timing Diagram (Flash)
VCCf
tVACCR
tVCS
tVLHT
VACC
VCC
WP/ACC
CEf
WE
tVLHT
tVLHT
RY/BY
Acceleration Mode Period
32
MB84VD23280EA-90/MB84VD23280EE-90
• Extended Sector Group Protection (Flash)
VCCf
tVCS
RESET
tVLHT
tVIDR
tWC
Address
tWC
SPAX
SPAX
SPAY
A6, A3, A2, A0
A1
CEf
OE
TIME-OUT
tWP
WE
Data
60h
60h
40h
01h
60h
tOE
SPAX: Sector Group Address to be protected
SPAY : Next Group Sector Address to be protected
TIME-OUT : Time-Out window = 250 µs (Min.)
33
MB84VD23280EA-90/MB84VD23280EE-90
• Read Cycle (SRAM)
Parameter
34
Symbol
Value
Min.
Max.
Unit
Read Cycle Time
tRC
70
—
ns
Address Access Time
tAA
—
70
ns
Chip Enable (CE1s) Access Time
tCO1
—
70
ns
Chip Enable (CE2s) Access Time
tCO2
—
70
ns
Output Enable Access Time
tOE
—
35
ns
LBs, UBs to Output Valid
tBA
—
70
ns
Chip Enable (CE1s Low and CE2s High) to Output Active
tCOE
5
—
ns
Output Enable Low to Output Active
tOEE
0
—
ns
UBs, LBs Enable Low to Output Active
tBE
0
—
ns
Chip Enable (CE1s High or CE2s Low) to Output High-Z
tOD
—
25
ns
Output Enable High to Output High-Z
tODO
—
25
ns
UBs, LBs Output Enable to Output High-Z
tBD
—
25
ns
Output Data Hold Time
tOH
10
—
ns
MB84VD23280EA-90/MB84VD23280EE-90
• Read Cycle (SRAM)
tRC
Address
tAA
tOH
tCO1
CE1s
tCOE
tOD
tCO2
CE2s
tOD
tOE
OE
tODO
tOEE
LBs, UBs
tBD
tBA
tBE
tCOE
DQ
VALID DATA OUT
Note: WE remains HIGH for the read cycle.
35
MB84VD23280EA-90/MB84VD23280EE-90
• Write Cycle (SRAM)
Parameter
36
Symbol
Value
Min.
Max.
Unit
Write Cycle Time
tWC
70
—
ns
Write Pulse Width
tWP
55
—
ns
Chip Enable to End of Write
tCW
60
—
ns
Address valid to End of Write
tAW
60
—
ns
UBs, LBs to End of Write
tBW
60
—
ns
Address Setup Time
tAS
0
—
ns
Write Recovery Time
tWR
0
—
ns
WE Low to Output High-Z
tODW
—
25
ns
WE High to Output Active
tOEW
0
—
ns
Data Setup Time
tDS
30
—
ns
Data Hold Time
tDH
0
—
ns
MB84VD23280EA-90/MB84VD23280EE-90
• Write Cycle (Note 3) (WE control) (SRAM)
tWC
Address
tAS
tWP
tWR
WE
tAW
tCW
CE1s
CE2s
tCW
tBW
LBs, UBs
tOEW
tODW
DOUT
Note 1
Note 2
tDS
DIN
Note 4
tDH
VALID DATA IN
Note 4
Notes: 1. If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the
output will remain at high impedance.
2. If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the
output will remain at high impedance.
3. If OE is HIGH during the write cycle, the outputs will remain at high impedance.
4. Because I/O signals may be in the output state at this Time, input signals of reverse
polarity must not be applied.
37
MB84VD23280EA-90/MB84VD23280EE-90
• Write Cycle (Note 1) (CE1s control) (SRAM)
tWC
Address
tAS
tWP
tWR
WE
tAW
tCW
CE1s
CE2s
tCW
tBW
LBs, UBs
tBE
tCOE
tODW
DOUT
tDS
DIN
Note 2
tDH
VALID DATA IN
Notes: 1. If OE is HIGH during the write cycle, the outputs will remain at high impedance.
2. Because I/O signals may be in the output state at this Time, input signals of reverse
polarity must not be applied.
38
MB84VD23280EA-90/MB84VD23280EE-90
• Write Cycle (Note 1) (CE2s Control) (SRAM)
tWC
Address
tAS
tWP
tWR
WE
tCW
CE1s
tAW
CE2s
tCW
tBW
LBs, UBs
tBE
tCOE
tODW
DOUT
tDS
DIN
Note 2
tDH
VALID DATA IN
Notes: 1. If OE is HIGH during the write cycle, the outputs will remain at high impedance.
2. Because I/O signals may be in the output state at this Time, input signals of reverse
polarity must not be applied.
39
MB84VD23280EA-90/MB84VD23280EE-90
• Write Cycle (Note 1) (LBs, UBs Control) (SRAM)
tWC
Address
tWP
tWR
WE
tCW
CE1s
tCW
CE2s
tAW
tAS
tBW
LBs, UBs
tBE
tCOE
tODW
DOUT
tDS
DIN
Note 2
tDH
VALID DATA IN
Notes: 1. If OE is HIGH during the write cycle, the outputs will remain at high impedance.
2. Because I/O signals may be in the output state at this Time, input signals of reverse
polarity must not be applied.
40
MB84VD23280EA-90/MB84VD23280EE-90
■ ERASE AND PROGRAMMING PERFORMANCE (Flash)
Value
Parameter
Unit
Remarks
Min.
Typ.
Max.
Sector Erase Time
—
1
10
s
Excludes programming time
prior to erasure
Byte Programming Time
—
8
300
µs
Excludes system-level
overhead
Word Programming Time
—
16
360
µs
Excludes system-level
overhead
Chip Programming Time
—
—
200
s
Excludes system-level
overhead
100,000
—
—
cycle
Erase/Program Cycle
■ DATA RETENTION CHARACTERISTICS (SRAM)
Parameter
Symbol
Data Retention Supply Voltage
Standby Current
VDH = 3.0 V
Chip Deselect to Data Retention Mode Time
Recovery Time
Note
Value
Unit
Min.
Typ.
Max.
VDH
1.5
—
3.3
V
IDDS2
—
TBD
15
µA
tCDR
0
—
—
ns
tR
tRC
—
—
ns
tRC: Read cycle time
• CE1s Controlled Data Retention Mode (Note 1)
VCCs
DATA RETENTION MODE
2.7 V
VIH
VDH
See Note 2
See Note 2
VCCS – 0.2 V
CE1s
tCDR
tR
GND
41
MB84VD23280EA-90/MB84VD23280EE-90
• CE2s Controlled Data Retention Mode (Note 3)
VCCs
DATA RETENTION MODE
2.7 V
VDH
VIH
tCDR
tR
CE2s
VIL
0.2 V
GND
Notes: 1. In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to Vccs–0.2 V or Vss
to 0.2 V during data retention mode. Other input and input/output pins can be used between –0.3 V to
Vccs+0.3 V.
2. When CE1s is operating at the VIH Min. level, the standby current is given by ISB1s during the transition
of VCCs from 3.3V to VIH Min. level.
3. In CE2s controlled data retention mode, input and input/output pins can be used between
–0.3 V to Vccs+0.3V.
■ PIN CAPACITANCE
Parameter
Symbol
Condition
Value
Min.
Typ.
Max.
Unit
Input Capacitance
CIN
VIN = 0

TBD
TBD
pF
Output Capacitance
COUT
VOUT = 0

TBD
TBD
pF
Control Pin Capacitance
CIN2
VIN = 0

TBD
TBD
pF
WP/ACC Pin Capacitance
CIN3
VIN = 0

TBD
TBD
pF
Note: Test conditions Ta = 25°C, f = 1.0 MHz
■ HANDLING OF PACKAGE
Please handle this package carefully since the sides of packages are right angle.
■ CAUTION
1) The high voltage (VID) can not apply to address pins and control pins except RESET. Therefore, it can not
use autoselect and sector protect function by applying the high voltage (VID) to specific pins.
2) For the sector protection, since the high voltage (VID) can be applied to the RESET, it can be protected the
sector useing “Extended sector protect” command.
42
MB84VD23280EA-90/MB84VD23280EE-90
■ ORDERING INFORMATION
MB84VD23280
EA
-90
-PBS
PACKAGE TYPE
PBS = 101-ball BGA
SPEED OPTION
See Product Selector Guide
Device Revision
EA or EE
DEVICE NUMBER/DESCRIPTION
64Mega-bit (8M × 16-bit or 4M × 16-bit) Dual Operation Flash Memory
3.0V-only Read, Program, and Erase
8Mega-bit(1M × 8-bit or 512K × 16-bit) SRAM
43
MB84VD23280EA-90/MB84VD23280EE-90
■ PACKAGE DIMENSION
101-pin plastic FBGA
(BGA-101P-M01)
+0.15
12.00±0.10(.472±.004)
1.25 ±0.10
+.006
.049 –.004
(Mounting height)
0.39±0.10
(Stand off)
(.015±.004)
11.00±0.10
(.433±.004)
10.40(.409)
7.20(.283)
5.60(.220)REF
0.80
(.031)
12
11
10
9
8
7
6
5
4
3
2
1
5.60(.220)
REF
0.80
8.80(.346) (.031)
P N M L K J H G F E D C B A
INDEX-MARK AREA
+0.10
101-Ø0.45 –0.05
+.004
101-Ø.018 –.002
0.08(.003)
M
0.10(.004)
C
44
2000 FUJITSU LIMITED B101001S-1c-1
Dimensions in mm (inches).
MB84VD23280EA-90/MB84VD23280EE-90
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
Shinjuku Dai-Ichi Seimei Bldg. 7-1,
Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0721, Japan
Tel: +81-3-5322-3347
Fax: +81-3-5322-3386
http://edevice.fujitsu.com/
North and South America
FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, U.S.A.
Tel: +1-408-922-9000
Fax: +1-408-922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: +1-800-866-8608
Fax: +1-408-922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
http://www.fujitsu-fme.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
http://www.fmap.com.sg/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
1702 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100
Fax: +82-2-3484-7111
F0101
 FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.
FUJITSU semiconductor devices are intended for use in standard
applications (computers, office automation and other office
equipments, industrial, communications, and measurement
equipments, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or
where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters,
vehicle operating controls, medical devices for life support, etc.)
are requested to consult with FUJITSU sales representatives before
such use. The company will not be responsible for damages arising
from such use without prior approval.
Any semiconductor devices have inherently a certain rate of failure.
You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required for
export of those products from Japan.
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