MCNIX MX29L1611TC-75 16m-bit [2m x 8/1m x 16] cmos single voltage pagemode flash eeprom Datasheet

PRELIMINARY
MX29L1611
16M-BIT [2M x 8/1M x 16] CMOS
SINGLE VOLTAGE PAGEMODE FLASH EEPROM
FEATURES
• Regulated voltage range 3.0 to 3.6V write, erase and
read(MX29L1611-75/10/12)
• Fast random access/page mode access time: 75/
30ns, 100/30ns, 120/30ns.
• Full voltage range 2.7 to 3.6V write, erase and read
(MX29L1611-90)
• Fast random access/page mode access time: 90/
35ns
• Endurance: 10,000 cycles
• Page access depth: 16 bytes/8 words, page address
A0, A1, A2
• Sector erase architecture
- 32 equal sectors of 64k bytes each
- Sector erase time: 200ms typical
• Auto Erase and Auto Program Algorithms
- Automatically erases any one of the sectors or the
whole chip with Erase Suspend capability
•
•
•
•
•
•
•
- Automatically programs and verifies data at specified
addresses
Status Register feature for detection of program or
erase cycle completion
Low VCC write inhibit < 1.8V
Software and hardware data protection
Page program operation
- Internal address and data latches for 128 bytes/64
words per page
- Page programming time: 5ms typical
Low power dissipation
- 50mA active current
- 20uA standby current
Two independently Protected sectors
Industry standard surface mount packaging
- 44 lead SOP, 48 TSOP(I)
GENERAL DESCRIPTION
To allow for simple in-system reprogrammability, the
MX29L1611 does not require high input voltages for
programming. Three-volt-only commands determine
the operation of the device. Reading data out of the
device is similar to reading from an EPROM.
The MX29L1611 is a 16-mega bit pagemode Flash
memory organized as either 1M wordx16 or 2M bytex8.
The MX29L1611 includes 32 sectors of 64KB(65,536
Bytes or 32,768 words). MXIC's Flash memories offer
the most cost-effective and reliable read/write nonvolatile random access memory and fast page mode
access. The MX29L1611 is packaged 44-pin SOP and
48-TSOP(I). It is designed to be reprogrammed and
erased in-system or in-standard EPROM programmers.
MXIC Flash technology reliably stores memory contents
even after 10,000 cycles. The MXIC's cell is designed
to optimize the erase and programming mechanisms. In
addition, the combination of advanced tunnel oxide
processing and low internal electric fields for erase and
programming operations produces reliable cycling. The
MX29L1611 uses a 2.7V~3.6V VCC supply to perform
the Auto Erase and Auto Program algorithms.
The standard MX29L1611 offers access times as fast as
100ns,allowing operation of high-speed microprocessors
without wait. To eliminate bus contention, the MX29L1611
has separate chip enable CE, output enable (OE), and
write enable (WE) controls.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up
protection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC +1V.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29L1611 uses a command register to manage this
functionality.
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MX29L1611
PIN DESCRIPTION
PIN CONFIGURATIONS
SYMBOL
A0 - A19
Q0 - Q14
Q15/A-1
WE
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
MX29L1611
44 SOP(500mil)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
WP
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
CE
OE
WE
WP*
BYTE
VCC
GND
PIN NAME
Address Input
Data Input/Output
Q15(Word mode)/LSB addr.(Byte
mode)
Chip Enable Input
Output Enable Input
Write Enable Input
Sector Write Protect Input
Word/Byte Selection Input
Power Supply
Ground Pin
*Only for 44-SOP
48 TSOP (NORMAL TYPE)
BYTE
A16
A15
A14
A13
A12
A11
A10
A9
A8
A19
GND
WE
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
MX29L1611
(Normal Type)
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48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
VCC
NC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE
GND
GND
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MX29L1611
BLOCK DIAGRAM
WRITE
WE
OE
WP
BYTE
CONTROL
LOGIC
STATE
HIGH VOLTAGE
MACHINE
(WSM)
LATCH
BUFFER
COMMAND
INTERFACE
REGISTER
(CIR)
MX29L1611
FLASH
ARRAY
ARRAY
Y-DECODER
AND
X-DECODER
ADDRESS
Q15/A-1
A0-A19
PROGRAM/ERASE
INPUT
Y-PASS GATE
SOURCE
HV
COMMAND
DATA
DECODER
SENSE
AMPLIFIER
PGM
DATA
HV
COMMAND
DATA LATCH
Y-select
PROGRAM
DATA LATCH
Q0-Q15/A-1
I/O BUFFER
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MX29L1611
Table1.PIN DESCRIPTIONS
SYMBOL
A0 - A19
TYPE
INPUT
Q0 - Q7
INPUT/OUTPUT
Q8 - Q14
INPUT/OUTPUT
Q15/A -1
INPUT/OUTPUT
CE
INPUT
OE
INPUT
WE
INPUT
WP
INPUT
BYTE
INPUT
VCC
GND
NAME AND FUNCTION
ADDRESS INPUTS: for memory addresses. Addresses are internally
latched during a write cycle.
LOW-BYTE DATA BUS: Input data and commands during Command Interface
Register(CIR) write cycles. Outputs array,status and identifier data in the
appropriate read mode. Floated when the chip is de-selected or the outputs
are disabled.
HIGH-BYTE DATA BUS: Inputs data during x 16 Data-Write operations.
Outputs array, identifier data in the appropriate read mode; not used for status
register reads. Floated when the chip is de-selected or the outputs are
disabled
Selects between high-byte data INPUT/OUTPUT(BYTE = HIGH) and LSB
ADDRESS(BYTE = LOW)
CHIP ENABLE INPUTS: Activate the device's control logic, Input buffers,
decoders and sense amplifiers. With CE high, the device is deselected and
power consumption reduces to Standby level upon completion of any current
program or erase operations. CE must be low to select the device.
OUTPUT ENABLES: Gates the device's data through the output buffers
during a read cycle OE is active low.
WRITE ENABLE: Controls writes to the Command Interface Register(CIR).
WE is active low.
WRITE PROTECT: Top or Bottom sector can be protected by writing a nonvolatile protect-bit for each sector. When WP is high, all sectors can be
programmed or erased regardless of the state of the protect-bits.
BYTE ENABLE: BYTE Low places device in x8 mode. All data is then input
or output on Q0-7 and Q8-14 float. AddressQ15/A-1 selects between the high
and low byte. BYTE high places the device in x16 mode, and turns off the Q15/
A-1 input buffer. Address A0, then becomes the lowest order address.
DEVICE POWER SUPPLY(3.0V~3.6V for MX29L1611-75/10/12 ; 2.7V~3.6V
for MX29L1611-90)
GROUND
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MX29L1611
BUS OPERATION
Flash memory reads, erases and writes in-system via the local CPU . All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
Table 2.1 Bus Operations for Word-Wide Mode (BYTE = VIH)
Mode
Read
Output Disable
Standby
Manufacturer ID
Device ID
Write
Notes
1
1
1
2,4
2,4
1,3
CE
VIL
VIL
VIH
VIL
VIL
VIL
OE
VIL
VIH
X
VIL
VIL
VIH
WE
VIH
VIH
X
VIH
VIH
VIL
A0
X
X
X
VIL
VIH
X
A1
X
X
X
VIL
VIL
X
A9
X
X
X
VID
VID
X
Q0-Q7
DOUT
High Z
High Z
C2H
F8H
DIN
Q8-Q14
DOUT
High Z
HIgh Z
00H
00H
DIN
Q15/A-1
DOUT
HighZ
HighZ
0B
0B
DIN
A1
X
X
X
VIL
VIL
X
A9
X
X
X
VID
VID
X
Q0-Q7
DOUT
High Z
High Z
C2H
F8H
DIN
Q8-Q14
HighZ
High Z
HIgh Z
High Z
High Z
High Z
Q15/A-1
VIL/VIH
X
X
VIL
VIL
VIL/VIH
Table2.2 Bus Operations for Byte-Wide Mode (BYTE = VIL)
Mode
Read
Output Disable
Standby
Manufacturer ID
Device ID
Write
Notes
1
1
1
2,4
2,4
1,3
CE
VIL
VIL
VIH
VIL
VIL
VIL
OE
VIL
VIH
X
VIL
VIL
VIH
WE
VIH
VIH
X
VIH
VIH
VIL
A0
X
X
X
VIL
VIH
X
NOTES :
1. X can be VIH or VIL for address or control pins.
2. A0 and A1 at VIL provide manufacturer ID codes. A0 at VIH and A1 at VIL provide device ID codes. A0 at VIL, A1 at VIH and
with appropriate sector addresses provide Sector Protect Code.(Refer to Table 4)
3. Commands for different Erase operations, Data program operations or Sector Protect operations can only be successfully
completed through proper command sequence.
4. VID = 11.5V- 12.5V.
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MX29L1611
WRITE OPERATIONS
Commands are written to the COMMAND INTERFACE
REGISTER (CIR) using standard microprocessor write
timings. The CIR serves as the interface between the
microprocessor and the internal chip operation. The
CIR can decipher Read Array, Read Silicon ID, Erase
and Program command. In the event of a read command,
the CIR simply points the read path at either the array or
the silicon ID, depending on the specific read command
given. For a program or erase cycle, the CIR informs the
write state machine that a program or erase has been
requested. During a program cycle, the write state
machine will control the program sequences and the
CIR will only respond to status reads. During a sector/
chip erase cycle, the CIR will respond to status reads
and erase suspend. After the write state machine has
completed its task, it will allow the CIR to respond to its
full command set. The CIR stays at read status register
mode until the microprocessor issues another valid
command sequence.
Device operations are selected by writing commands
into the CIR. Table 3 below defines 16 Mbit flash family
command.
TABLE 3. COMMAND DEFINITIONS
Command
Read/
Silicon
Page/Byte
Chip
Sector
Erase
Erase
Read
Clear
Sequence
Reset
ID Read
Program
Erase
Erase
Suspend
Resume
Status Reg.
Status Reg.
Bus Write
4
4
4
6
6
3
3
4
3
Cycles Req'd
First Bus
Addr
5555H
5555H
5555H
5555H
5555H
5555H
5555H
5555H
5555H
Write Cycle
Data
AAH
AAH
AAH
AAH
AAH
AAH
AAH
AAH
AAH
Second Bus
Addr
2AAAH
2AAAH
2AAAH
2AAAH
2AAAH
2AAAH
2AAAH
2AAAH
2AAAH
Write Cycle
Data
55H
55H
55H
55H
55H
55H
55H
55H
55H
Third Bus
Addr
5555H
5555H
5555H
5555H
5555H
5555H
5555H
5555H
5555H
Write Cycle
Data
F0H
90H
A0H
80H
80H
B0H
D0H
70H
50H
Fourth Bus
Addr
RA
00H/01H
PA
5555H
5555H
X
Read/Write Cycle
Data
RD
C2H/F8H
PD
AAH
AAH
SRD
Fifth Bus
Addr
2AAAH
2AAAH
Write Cycle
Data
55H
55H
Sixth Bus
Addr
5555H
SA
Write Cycle
Data
10H
30H
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MX29L1611
TABLE 3. COMMAND DEFINITIONS
Command
Sequence
Bus Write
Sector
Sector
Verify Sector
Abort
Protection
Unprotect
Protect
6
6
4
3
Cycles Req'd
First Bus
Addr
5555H
5555H
5555H
5555H
Write Cycle
Data
AAH
AAH
AAH
AAH
Second Bus
Addr
2AAAH
2AAAH
2AAAH
2AAAH
Write Cycle
Data
55H
55H
55H
55H
Third Bus
Addr
5555H
5555H
5555H
5555H
Write Cycle
Data
60H
60H
90H
E0H
Fourth Bus
Addr
5555H
5555H
*
Read/Write Cycle
Data
AAH
AAH
C2H*
Fifth Bus
Addr
2AAAH
2AAAH
Write Cycle
Data
55H
55H
Sixth Bus
Addr
SA**
SA**
Write Cycle
Data
20H
40H
Notes:
1. Address bit A15 -- A19 = X = Don't care for all address commands except for Program Address(PA) and Sector Address(SA).
5555H and 2AAAH address command codes stand for Hex number starting from A0 to A14.
2. Bus operations are defined in Table 2.
3. RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse.
SA = Address of the sector to be erased. The combination of A15 -- A19 will uniquely select any sector.
4. RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.
SRD = Data read from status register.
5. Only Q0-Q7 command data is taken, Q8-Q15 = Don't care.
* Refer to Table 4, Figure 12.
** Only the top and the bottom sectors have protect- bit feature. SA = (A19,A18,A17,A16,A15) = 00000B or 11111B is valid.
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MX29L1611
DEVICE OPERATION
SILICON ID READ
The manufacturer and device codes may also be read
via the command register, for instances when the
MX29L1611 is erased or programmed in a system
without access to high voltage on the A9 pin. The
command sequence is illustrated in Table 3.
The Silicon ID Read mode allows the reading out of a
binary code from the device and will identify its
manufacturer and type. This mode is intended for use
by programming equipment for the purpose of
automatically matching the device to be programmed
with its corresponding programming algorithm. This
mode is functional over the entire temperature range of
the device.
Byte 0 (A0=VIL) represents the manfacturer's code
(MXIC=C2H) and byte 1 (A0=VIH) the device identifier
code (MX29L1611=F8H).
To activate this mode, the programming equipment
must force VID (11.5V~12.5V) on address pin A9. Two
identifier bytes may then be sequenced from the device
outputs by toggling address A0 from VIL to VIH. All
addresses are don't cares except A0 and A1.
To terminate the operation, it is necessary to write the
read/reset command sequence into the CIR.
Table 4. MX29L1611 Silion ID Codes and Verify Sector Protect Code
Type
A19
A18
A17
A16
A15
A1
A0
Manufacturer Code
X
X
X
X
X
VIL VIL
MX29L1611 Device Code X
X
X
X
X
Verify Sector Protect
Sector Address***
Code(HEX) DQ7
DQ6
DQ5 DQ4
DQ3
DQ2
DQ1 DQ0
C2H*
1
0
0
0
1
1
0
0
VIL VIH
F8H*
1
1
1
1
1
0
0
0
VIH VIL
C2H**
1
1
0
0
0
0
1
0
*
MX29L1611 Manufacturer Code = C2H, Device Code = F8H when BYTE = VIL
MX29L1611 Manufacturer Code = 00C2H, Device Code = 00F8H when BYTE = VIH
** Outputs C2H at protected sector address, 00H at unprotected scetor address.
***Only the top and the bottom sectors have protect-bit feature. Sector address = (A19, A18,A17,A16,A15) = 00000B or 11111B
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MX29L1611
After three-cycle command sequence is given, a
byte(word) load is performed by applying a low pulse on
the WE or CE input with CE or WE low (respectively) and
OE high. The address is latched on the falling edge of
CE or WE, whichever occurs last. The data is latched by
the first rising edge of CE or WE. Maximum of 128 bytes
of data may be loaded into each page by the same
procedure as outlined in the page program section
below.
READ/RESET COMMAND
The read or reset operation is initiated by writing the
read/reset command sequence into the command
register. Microprocessor read cycles retrieve array data
from the memory. The device remains enabled for reads
until the CIR contents are altered by a valid command
sequence.
The device will automatically power-up in the read/reset
state. In this case, a command sequence is not required
for "read operation". Standard microprocessor read
cycles will retrieve array data. This default value ensures
that no spurious alteration of the memory content occurs
during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing
parameters.
BYTE-WIDE LOAD/WORD-WIDE LOAD
Byte(word) loads are used to enter the 128 bytes(64
words) of a page to be programmed or the software
codes for data protection. A byte load(word load) is
performed by applying a low pulse on the WE or CE input
with CE or WE low (respectively) and OE high. The
address is latched on the falling edge of CE or WE,
whichever occurs last. The data is latched by the first
rising edge of CE or WE.
The MX29L1611 is accessed like an EPROM. When CE
and OE are low and WE is high the data stored at the
memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual
line control gives designers flexibility in preventing bus
contention.
Either byte-wide load or word-wide load is
determined(Byte = VIL or VIH is latched) on the falling
edge of the WE (or CE) during the 3rd command write
cycle.
Note that the read/reset command is not valid when
program or erase is in progress.
PROGRAM
PAGE READ
Any page to be programmed should have the page in the
erased state first, i.e. performing sector erase is
suggested before page programming can be performed.
The MX29L1611 offers "fast page mode read" function.
The users can take the access time advantage if keeping
CE, OE at low and the same page address (A3~A19
unchanged). Please refer to Figure 5-2 for detailed
timing waveform. The system performance could be
enhanced by initiating 1 normal read and 7 fast page
reads(for word mode A0~A2) or 15 fast page reads(for
byte mode altering A-1~A2).
The device is programmed on a page basis. If a
byte(word) of data within a page is to be changed, data
for the entire page can be loaded into the device. Any
byte(word) that is not loaded during the programming of
its page will be still in the erased state (i.e. FFH). Once
the bytes of a page are loaded into the device, they are
simultaneously programmed during the internal
programming period. After the first data byte(word) has
been loaded into the device, successive bytes(words)
are entered in the same manner. Each new byte(word)
to be programmed must have its high to low transition on
WE (or CE) within 30us of the low to high transition of WE
(or CE) of the preceding byte(word). A6 to A19 specify
the page address, i.e., the device is page-aligned on 128
bytes(64 words)boundary. The page address must be
valid during each high to low transition of WE or CE. A1 to A5 specify the byte address within the page, A0 to
A5 specify the word address withih the page. The
PAGE PROGRAM
To initiate Page program mode, a three-cycle command
sequence is required. There are two "unlock" write
cycles. These are followed by writing the page program
command-A0H.
Any attempt to write to the device without the three-cycle
command sequence will not start the internal Write State
Machine(WSM), no data will be written to the device.
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MX29L1611
byte(word) may be loaded in any order; sequential
loading is not required. If a high to low transition of CE or
WE is not detected whithin 100us of the last low to high
transition, the load period will end and the internal
programming period will start. The Auto page program
terminates when status on DQ7 is '1' at which time the
device stays at read status register mode until the CIR
contents are altered by a valid command sequence.(Refer
to table 3,6 and Figure 1,7,8)
SECTOR ERASE
CHIP ERASE
Sector erase does not require the user to program the
device prior to erase. The system is not required to
provide any controls or timings during these operations.
Sector erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
set-up command-80H. Two more "unlock" write cycles
are then followed by the sector erase command-30H.
The sector address is latched on the falling edge of WE,
while the command (data) is latched on the rising edge
of WE.
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command-80H. Two more "unlock" write cycles
are then followed by the chip erase command-10H.
The automatic sector erase begins on the rising edge of
the last WE pulse in the command sequence and
terminates when the status on DQ7 is "1" at which time
the device stays at read status register mode. The
device remains enabled for read status register mode
until the CIR contents are altered by a valid command
sequence.(Refer to table 3,6 and Figure 3,4,7,9)
Chip erase does not require the user to program the
device prior to erase.
The automatic erase begins on the rising edge of the last
WE pulse in the command sequence and terminates
when the status on DQ7 is "1" at which time the device
stays at read status register mode. The device remains
enabled for read status register mode until the CIR
contents are altered by a valid command sequence.(Refer
to table 3,6 and Figure 2,7,9)
ERASE SUSPEND
This command only has meaning while the the WSM is
executing SECTOR or CHIP erase operation, and
therefore will only be responded to during SECTOR or
CHIP erase operation. After this command has been
executed, the CIR will initiate the WSM to suspend erase
operations, and then return to Read Status Register
mode. The WSM will set the DQ6 bit to a "1". Once the
WSM has reached the Suspend state,the WSM will set
the DQ7 bit to a "1", At this time, WSM allows the CIR to
respond to the Read Array, Read Status Register, Abort
and Erase Resume commands only. In this mode, the
CIR will not resopnd to any other comands. The WSM
will continue to run, idling in the SUSPEND state,
regardless of the state of all input control pins.
Table 5. MX29L1611 Sector Address Table
(Byte-Wide Mode)
A19
A18
A17
A16
A15
Address Range[A19, -1]
SA0
0
0
0
0
0
000000H--00FFFFH
SA1
0
0
0
0
1
010000H--01FFFFH
SA2
0
0
0
1
0
020000H--02FFFFH
SA3
0
0
0
1
1
030000H--03FFFFH
SA4
0
0
1
0
0
040000H--04FFFFH
...
...
...
...
1
1
1
1
SA31
...
1
................................
ERASE RESUME
1F0000H--1FFFFFH
This command will cause the CIR to clear the suspend
state and set the DQ6 to a '0', but only if an Erase
Suspend command was previously issued. Erase
Resume will not have any effect in all other conditions.
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MX29L1611
READ STATUS REGISTER
CLEAR STATUS REGISTER
The MXIC's 16 Mbit flash family contains a status
register which may be read to determine when a program
or erase operation is complete, and whether that
operation completed successfully. The status register
may be read at any time by writing the Read Status
command to the CIR. After writing this command, all
subsequent read operations output data from the status
register until another valid command sequence is
written to the CIR. A Read Array command must be
written to the CIR to return to the Read Array mode.
The Eraes fail status bit (DQ5) and Program fail status
bit (DQ4) are set by the write state machine, and can only
be reset by the system software. These bits can indicate
various failure conditions(see Table 6). By allowing the
system software to control the resetting of these bits,
several operations may be performed (such as
cumulatively programming several pages or erasing
multiple blocks in squence). The status register may
then be read to determine if an error occurred during that
programming or erasure series. This adds flexibility to
the way the device may be programmed or erased.
Additionally, once the program(erase) fail bit happens,
the program (erase) operation can not be performed
further. The program(erase) fail bit must be reset by
system software before further page program or sector
(chip) erase are attempted. To clear the status register,
the Clear Status Register command is written to the CIR.
Then, any other command may be issued to the CIR.
Note again that before a read cycle can be initiated, a
Read command must be written to the CIR to specify
whether the read data is to come from the Array, Status
Register or Silicon ID.
The status register bits are output on DQ3 - DQ7(table
6) whether the device is in the byte-wide (x8) or wordwide (x16) mode for the MX29L1611. In the word-wide
mode the upper byte, DQ(8:15) is set to 00H during a
Read Status command. In the byte-wide mode, DQ(8:14)
are tri-stated and DQ15/A-1 retains the low order address
function.
It should be noted that the contents of the status register
are latched on the falling edge of OE or CE whichever
occurs last in the read cycle. This prevents possible bus
errors which might occur if the contents of the status
register change while reading the status register. CE or
OE must be toggled with each subsequent status read,
or the completion of a program or erase operation will not
be evident.
The Status Register is the interface between the
microprocessor and the Write State Machine (WSM).
When the WSM is active, this register will indicate the
status of the WSM, and will also hold the bits indicating
whether or not the WSM was successful in performing
the desired operation. The WSM sets status bits four
through seven and clears bits six and seven, but cannot
clear status bits four and five. If Erase fail or Program fail
status bit is detected, the Status Register is not cleared
until the Clear Status Register command is written. The
MX29L1611 automatically outputs Status Register data
when read after Chip Erase, Sector Erase, Page Program
or Read Status Command write cycle. The default state
of the Status Register after powerup and return from
deep power-down mode is (DQ7, DQ6, DQ5, DQ4) =
1000B. DQ3 = 0 or 1 depends on sector-protect status,
can not be changed by Clear Status Register Command
or Write State Machine.
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11
MX29L1611
TABLE 6. MX29L1611 STATUS REGISTER
IN PROGRESS
STATUS
NOTES
DQ7
DQ6
DQ5
DQ4
DQ3
PROGRAM
1,2, 6
0
0
0
0
0/1
ERASE
1,3, 6
0
0
0
0
0/1
SUSPEND (NOT COMPLETE)
1,4, 6
(COMPLETE)
COMPLETE
FAIL
0
1
0
0
0/1
1
1
0
0
0/1
PROGRAM
1,2, 6
1
0
0
0
0/1
ERASE
1,3, 6
1
0
0
0
0/1
PROGRAM
1,5, 6
1
0
0
1
0/1
ERASE
1,5, 6
1
0
1
0
0/1
6
1
0
0
0
0/1
AFTER CLEARING STATUS REGISTER
NOTES:
1. DQ7 : WRITE STATE MACHINE STATUS
1 = READY, 0 = BUSY
DQ6 : ERASE SUSPEND STATUS
1 = SUSPEND, 0 = NO SUSPEND
DQ5 : ERASE FAIL STATUS
1 = FAIL IN ERASE, 0 = SUCCESSFUL ERASE
DQ4 : PROGRAM FAIL STATUS
1 = FAIL IN PROGRAM, 0 = SUCCESSFUL PROGRAM
DQ3 : SECTOR-PROTECT STATUS
1 = SECTOR 0 OR/AND 15 PROTECTED
0 = NONE OF SECTOR PROTECTED
DQ2 - 0 = RESERVED FOR FUTURE ENHANCEMENTS.
These bits are reserved for future use ; mask them out when polling the Status Register.
2. PROGRAM STATUS is for the status during Page Programming or Sector Unprotect mode.
3. ERASE STATUS is for the status during Sector/Chip Erase or Sector Protection mode.
4. SUSPEND STATUS is for both Sector and Chip Erase mode .
5. FAIL STATUS bit(DQ4 or DQ5) is provided during Page Program or Sector/Chip Erase modes respectively.
6. DQ3 = 0 or1 depends on Sector-Protect Status.
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12
MX29L1611
HARDWARE SECTOR PROTECTION
SECTOR UNPROTECT
The MX29L1611 features sector protection. This feature
will disable both program and erase operations in either
the top or the bottom sector (0 or 31). The sector
protection feature is enabled using system software by
the user(Refer to table 3). The device is shipped with
both sectors unprotected. Alternatively, MXIC may
protect sectors in the factory prior to shipping the device.
It is also possible to unprotect the sector , same as the
first five write command cycles in activating sector
protection mode followed by the Unprotect Sector
command -40H, the automatic Unprotect operation
begins on the rising edge of the last WE pulse in the
command sequence and terminates when the Status on
DQ7 is '1' at which time the device stays at the read
status register mode. (Refer to table 3,6 and Figure
11,12)
SECTOR PROTECTION
The device remains enabled for read status register
mode until the CIR contents are altered by a valid
command sequence.
To activate this mode, a six-bus cycle operation is
required. There are two 'unlock' write cycles. These are
followed by writing the 'set-up' command. Two more
'unlock' write cycles are then followed by the Lock Sector
command - 20H. Sector address is latched on the falling
edge of CE or WE of the sixth cycle of the command
sequence. The automatic Lock operation begins on the
rising edge of the last WE pulse in the command sequence
and terminates when the Status on DQ7 is '1' at which
time the device stays at the read status register mode.
Either Protect or Unprotect sector mode is accomplished
by keeping WP high, i.e. protect-bit status can only be
changed with a valid command sequence and WP at
high. When WP is high, all sectors can be programmed
or erased regardless of the state of the protect-bits.
Protect-bit status will not be changed during chip/sector
erase operations. With WP at VIL, only unprotected
sectors can be programmed or erased.
The device remains enabled for read status register
mode until the CIR contents are altered by a valid
command sequence (Refer to table 3,6 and Figure
10,12 ).
ABORT MODE
To activate Abort mode, a three-bus cycle operation is
required. The E0H command (Refer to table 3) only
stops Page program or Sector /Chip erase operation
currently in progress and puts the device in Abort mode.
So the program or erase operation will not be completed.
Since the data in some page/sectors is no longer valid
due to an incomplete program or erase operation, the
program fail (DQ4) or erase fail (DQ5)bit will be set.
VERIFY SECTOR PROTECT
To verify the Protect status of the Top and the Bottom
sector, operation is initiated by writing Silicon ID read
command into the command register. Following the
command write, a read cycle from address XXX0H
retrieves the Manufacturer code of C2H. A read cycle
from XXX1H returns the Device code F8H. A read cycle
from appropriate address returns information as to which
sectors are protected. To terminate the operation, it is
necessary to write the read/reset command sequence
into the CIR.
A read array command MUST be written to bring the
device out of the abort state without incurring any wake
up latency. Note that once device is brought out, Clear
status register mode is required before a program or
erase operation can be executed.
(Refer to table 3,4 and Figure 12)
A few retries are required if Protect status can not be
verified successfully after each operation.
P/N:PM0511
REV. 2.4, NOV. 06, 2001
13
MX29L1611
DATA PROTECTION
The MX29L1611 is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power
transitions. During power up the device automatically
resets the internal state machine in the Read Array
mode. Also, with its control register architecture, alteration
of the memory contents only occurs after successful
completion of specific multi-bus cycle command
sequences.
The device also incorporates several features to prevent
inadvertent write cycles resulting from VCC power-up
and power-down transitions or system noise.
LOW VCC WRITE INHIBIT
To avoid initiation of a write cycle during VCC power-up
and power-down, a write cycle is locked out for VCC less
than VLKO(typically 1.8V). If VCC < VLKO, the command
register is disabled and all internal program/erase circuits
are disabled. Under this condition the device will reset
to the read mode. Subsequent writes will be ignored until
the VCC level is greater than VLKO. It is the user's
responsibility to ensure that the control pins are logically
correct to prevent unintentional write when VCC is
above VLKO.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 10ns (typical) on CE or WE will
not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL,CE =
VIH or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
P/N:PM0511
REV. 2.4, NOV. 06, 2001
14
MX29L1611
Figure 1. AUTOMATIC PAGE PROGRAM FLOW CHART
START
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data A0H Address 5555H
Write Program Data/Address
NO
Loading End?
YES
Wait 100us
Read Status Register
NO
SR7 = 1
?
YES
SR4 = 0
?
NO
YES
Page Program Completed
YES
Program Error
To Continue Other Operations,
Do Clear S.R. Mode First
Program
another page?
NO
Operation Done, Device Stays At Read S.R. Mode
Note : S.R. Stands for Status Register
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REV. 2.4, NOV. 06, 2001
15
MX29L1611
Figure 2. AUTOMATIC CHIP ERASE FLOW CHART
START
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data 80H Address 5555H
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data 10H Address 5555H
Read Status Register
NO
NO
SR7 = 1
?
To Execute
Suspend Mode ?
YES
Erase Suspend Flow (Figure 4.)
YES
SR5 = 0
?
NO
YES
Chip Erase Completed
Operation Done,
Device Stays at
Read S.R. Mode
Erase Error
To Continue Other
Operations, Do Clear
S.R. Mode First
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REV. 2.4, NOV. 06, 2001
16
MX29L1611
Figure 3. AUTOMATIC SECTOR ERASE FLOW CHART
START
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data 80H Address 5555H
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data 30H Sector Address
Read Status Register
NO
NO
SR7 = 1
?
To Execute
Suspend Erase ?
YES
Erase Suspend Flow (Figure 4.)
YES
SR5 = 0
?
NO
YES
Sector Erase Completed
Operation Done,
Device Stays at
Read S.R. Mode
Erase Error
To Continue Other
Operations, Do Clear
S.R. Mode First
P/N:PM0511
REV. 2.4, NOV. 06, 2001
17
MX29L1611
Figure 4. ERASE SUSPEND/ERASE RESUME FLOW CHART
START
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data B0H Address 5555H
Read Status Register
NO
SR7 = 1
?
YES
SR6 = 1
?
NO
NO
SR5 = 0
?
YES
YES
Erase has completed
Erase Suspend
Operation Done,
Device Stays at
Read S,R, Mode
Write Data AAH Address 5555H
Erase Error
To Continue Other
Operations, Do Clear
S.R. Mode First
Write Data 55H Address 2AAAH
Write Data F0H Address 5555H
Read Array
NO
Reading End ?
YES
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data D0H Address 5555H
Continue Erase
P/N:PM0511
REV. 2.4, NOV. 06, 2001
18
MX29L1611
ELECTRICAL SPECIFICATIONS
NOTICE:
Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is stress rating only and functional operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended period may
affect reliability.
ABSOLUTE MAXIMUM RATINGS
RATING
VALUE
Ambient Operating Temperature
0°C to 70°C
Storage Temperature
-65°C to 125°C
Applied Input Voltage
-0.5V to Vcc+0.5V
Applied Output Voltage
NOTICE:
Specifications contained within the following tables are subject
to change.
-0.5V to Vcc+0.6V
VCC to Ground Potential
-0.5V to 4.0V
A9
-0.5V to 12.5V
°C, f = 1.0 MHz
CAPACITANCE TA = 25°
SYMBOL
CIN
COUT
PARAMETER
Input Capacitance
Output Capacitance
MIN.
TYP.
MAX.
14
16
UNIT
pF
pF
CONDITIONS
VIN = 0V
VOUT = 0V
SWITCHING TEST CIRCUITS
2.7K ohm
DEVICE
UNDER
TEST
3.3V
CL
6.2K ohm
DIODES = IN3064
OR EQUIVALENT
CL = 30 pF Including jig capacitance(29L1611-75/10/12)@Vcc=3.0V~3.6V
CL=100pF Including jig capacitance (29L1611-90) @Vcc=2.7V~3.6V
SWITCHING TEST WAVEFORMS
2.4V
2.0V
1.5V
TEST POINTS
0.8V
0.45V
OUTPUT
INPUT
AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".
Input pulse rise and fall times are < 5ns.
P/N:PM0511
REV. 2.4, NOV. 06, 2001
19
MX29L1611
5.1 DC CHARACTERISTICS Vcc = 3.0V ~ 3.6V
SYMBOL
PARAMETER
IIL
Input Load
NOTES
MIN.
TYP.
1
MAX.
±1
UNITS
TEST CONDITIONS
uA
VCC = VCC Max
Current
ILO
Output Leakage
VIN = VCC or GND
1
±10
uA
Current
ISB1
VCC Standby
VIN = VCC or GND
1
20
50
uA
Current(CMOS)
ISB2
VCC Standby
VCC Read
1
2
mA
VCC Erase
1
50
80
mA
VCC Program
VCC = VCC Max
f = 10MHz, IOUT = 0 mA
1,2
5
mA
Suspend Current
ICC3
VCC = VCC Max
CE = VIH
Current
ICC2
VCC = VCC Max
CE = VCC ± 0.2V
Current(TTL)
ICC1
VCC = VCC Max
CE = VIH
Sector Erase Suspended
1
15
30
mA
Program in Progress
15
30
mA
Erase in Progress
Current
ICC4
VCC Erase Current
1
VIL
Input Low Voltage
3
-0.3
0.6
V
VIH
Input High Voltage
4
0.7xVCC
VCC+0.3
V
VOL
Output Low Voltage
0.45
V
IOL = 2.1mA, Vcc = Vcc Min
VOH
Output High Voltage
V
IOH = -100uA, Vcc = Vcc Min
2.4
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product
versions (package and speeds).
2. ICC2 is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of
ICC2 and ICC1.
3. VIL min. = -1.0V for pulse width < 50ns.
VIL min. = -2.0V for pulse width < 20ns.
4. VIH max. = VCC + 1.5V for pulse width < 20ns. If VIH is over the specified maximum value, read operation cannot be
guaranteed.
P/N:PM0511
REV. 2.4, NOV. 06, 2001
20
MX29L1611
AC CHARACTERISTICS -- READ OPERATIONS
SYMBOL DESCRIPTIONS
29L1611-75
29L1611-90
MIN. MAX.
MIN.
MAX.
UNIT CONDITIONS
tACC
Address to Output Delay
75
90
ns
CE=OE=VIL
tPA
Page Mode Access Time
30
35
ns
CE= OE = VIL
tCE
CE to Output Delay
75
90
ns
OE=VIL
tOE
OE to Output Delay
30
35
ns
CE=VIL
tDF
OE High to Output Delay
0
20
ns
CE=VIL
tOH
Address to Output hold
0
ns
CE=OE=VIL
tBACC
BYTE to Output Delay
75
90
ns
CE= OE=VIL
tBHZ
BYTE Low to Output in High Z
20
20
ns
CE=VIL
SYMBOL DESCRIPTIONS
20
0
0
29L1611-10
29L1611-12
MIN. MAX.
MIN.
MAX.
UNIT CONDITIONS
tACC
Address to Output Delay
100
120
ns
CE=OE=VIL
tPA
Page Mode Access Time
30
40
ns
CE= OE = VIL
tCE
CE to Output Delay
100
120
ns
OE=VIL
tOE
OE to Output Delay
30
30
ns
CE=VIL
tDF
OE High to Output Delay
0
20
ns
CE=VIL
tOH
Address to Output hold
0
ns
CE=OE=VIL
tBACC
BYTE to Output Delay
100
120
ns
CE= OE=VIL
tBHZ
BYTE Low to Output in High Z
20
20
ns
CE=VIL
20
0
0
NOTE: In the voltage range 3.0~3.6V, 29L1611-90 achieves tPA=30ns or better.
TEST CONDITIONS:
• Input pulse levels: 0.45V/2.4V
• Input rise and fall times: 5ns
• Output load:
Speed options
output load (Including scope and jig)
29L1611-75
1TTL gate + 30pF
29L1611-90/10/12
1TTL gate + 100pF
• Reference levels for measuring timing: 1.5V
NOTE:
1. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven.
P/N:PM0511
REV. 2.4, NOV. 06, 2001
21
MX29L1611
Figure 5-1. NORMAL READ TIMING WAVEFORMS
Vcc Power-up
Standby
Device and
Outputs Enabled
address selection
Standby
Vcc Power-down
Data valid
VIH
ADDRESSES STABLE
ADDRESSES
VIL
VIH
CE
VIL
VIH
OE
VIL
tDF
VIH
WE
tOE
VIL
tCE
tOH
VOH
DATA OUT
HIGH Z
HIGH Z
Data out valid
VOL
tACC
5.0V
VCC
GND
NOTE:
1. For real world application, BYTE pin should be either static high(word mode) or static low(byte mode);
dynamic switching of BYTE pin is not recommended.
P/N:PM0511
REV. 2.4, NOV. 06, 2001
22
MX29L1611
Figure 5-2. PAGE READ TIMING WAVEFORMS
VALID ADDRESS
A3-A19
(A-1), A0~A2
tACC
CE
OE
tPA
tPA
tPA
tOE
tOH
tDF
DATA OUT
Figure 6. BYTE TIMING WAVEFORMS
VIH
ADDRESSES STABLE
ADDRESSES
VIL
VIH
CE
VIL
VIH
OE
VIL
tDF
tBACC
VIH
tOE
BYTE
VIL
tCE
tOH
VOH
DATA(DQ0-DQ7)
HIGH Z
Data Output
HIGH Z
Data Output
VOL
tACC
tBHZ
VOH
DATA(DQ8-DQ15)
HIGH Z
HIGH Z
Data Output
VOL
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REV. 2.4, NOV. 06, 2001
23
MX29L1611
AC CHARACTERISTICS -- WRITE/ERASE/PROGRAM OPERATIONS
29L1611-75
29L1611-90
MIN.
SYMBOL
DESCRIPTION
MIN.
MAX.
tWC
Write Cycle Time
75
90
ns
tAS
Address Setup Time
0
0
ns
tAH
Address Hold Time
45
45
ns
tDS
Data Setup Time
35
45
ns
tDH
Data Hold Time
10
10
ns
tOES
Output Enable Setup Time
0
0
ns
tCES
CE Setup Time
0
0
ns
tGHWL
Read Recover TimeBefore Write
0
0
tCS
CE Setup Time
0
0
ns
tCH
CE Hold Time
0
0
ns
tWP
Write Pulse Width
35
35
ns
tWPH
Write Pulse Width High
30
30
ns
tBALC
Byte(Word) Address Load Cycle
0.3
tBAL
Byte(Word) Address Load Time
100
tSRA
Status Register Access Time
tCESR
CE Setup before S.R. Read
100
100
ns
tVCS
VCC Setup Time
2
2
us
30
0.3
30
100
75
P/N:PM0511
MAX.
UNIT
us
us
90
ns
REV. 2.4, NOV. 06, 2001
24
MX29L1611
AC CHARACTERISTICS -- WRITE/ERASE/PROGRAM OPERATIONS
29L1611-10
29L1611-12
MIN.
SYMBOL
DESCRIPTION
MIN.
MAX.
tWC
Write Cycle Time
100
120
ns
tAS
Address Setup Time
0
0
ns
tAH
Address Hold Time
60
60
ns
tDS
Data Setup Time
50
50
ns
tDH
Data Hold Time
10
10
ns
tOES
Output Enable Setup Time
0
0
ns
tCES
CE Setup Time
0
0
ns
tGHWL
Read Recover TimeBefore Write
0
0
tCS
CE Setup Time
0
0
ns
tCH
CE Hold Time
0
0
ns
tWP
Write Pulse Width
60
60
ns
tWPH
Write Pulse Width High
40
40
ns
tBALC
Byte(Word) Address Load Cycle
0.3
tBAL
Byte(Word) Address Load Time
100
tSRA
Status Register Access Time
tCESR
CE Setup before S.R. Read
100
100
ns
tVCS
VCC Setup Time
2
2
us
30
0.3
30
100
100
P/N:PM0511
MAX.
UNIT
us
us
120
ns
REV. 2.4, NOV. 06, 2001
25
MX29L1611
Figure 7. COMMAND WRITE TIMING WAVEFORMS
tCH
CE
tOES
tCS
OE
tWC
WE
tGHWL
tWPH
tWP
tAS
ADDRESSES
tAH
VALID
tDH
tDS
HIGH Z
DATA
(D/Q)
VCC
DIN
tVCS
NOTE:
1. BYTE pin is treated as address pin All timing specifications for BYTE pin are the same as those for address pin.
2. BYTE pin is sampled on the falling edge of WE or CE during the 3rd command write bus cycle; for real world application,
BYTE pin should be either static high(word mode) or static low(byte mode).
P/N:PM0511
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26
MX29L1611
Figure 8. AUTOMATIC PAGE PROGRAM TIMING WAVEFORMS
A0~A5
AAH
55H
55H
A-1
(byte mode only)
55H
A6~A14
tAS
2AH
55H
Word offset
Address
Last Word
offset Address
Low/High
Byte Select
Last Low/High
Byte Select
Page Address
tAH
Page Address
A15~A19
tWC
tBAL
tBALC
CE
tWP
tWPH
WE
tCES
OE
tDS
tDH
tSRA
DATA
AAH
55H
A0H
Write
Last Write
Data
Data
SRD
NOTE:
1.Please refer to page 9 for detail page program operation.
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27
MX29L1611
Figure 9. AUTOMATIC SECTOR/CHIP ERASE TIMING WAVEFORMS
A0~A14
5555H
tAS
2AAAH
5555H
5555H
2AAAH
*/5555H
tAH
SA/*
A15~A19
tCESR
CE
tWP
tWPH
WE
tWC
tCES
OE
tDS
tDH
tSRA
AAH
DATA
55H
AAH
80H
55H
30H
SRD
NOTES:
1."*" means "don't care" in this diagram.
2."SA" means "Sector Adddress".
P/N:PM0511
REV. 2.4, NOV. 06, 2001
28
MX29L1611
Figure 10. SECTOR PROTECTION ALGORITHM
START,
PLSCNT=0
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data 60H Address 5555H
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Increment PLSCNT,
To Protect Sector Again
Write Data 20H, Sector Address*
Read Status Register
NO
SR7 = 1
?
NO
YES
Protect Sector
Operation Terminated
PLSCNT
YES
= 25 ?
NO
Device Failed
To
Verify Protect
Status ?
YES
Verify Protect Status Flow
(Figure 12)
NO
Data
= C2H ?
YES
Device Stays at
Read S.R. Mode
Write Data AAH Address 5555H
NOTE :
*Only the Top or the Bottom Sector Address is vaild in this feature.
i.e. Sector Address = (A19,A18,A17,A16,A15) = 00000B or 11111B
Write Data 55H Address 2AAAH
Write Data 60H Address 5555H
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data 20H, Sector Address*
Read Status Register
SR7 = 1
?
NO
YES
Sector Protected,Operation
Done, Device Stays at
Verify Sector Protect Mode
P/N:PM0511
REV. 2.4, NOV. 06, 2001
29
MX29L1611
Figure 11. SECTOR UNPROTECT ALGORITHM
START,
PLSCNT=0
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data 60H Address 5555H
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Increment PLSCNT,
To Unprotect Sector Again
Write Data 40H, Sector Address*
Read Status Register
NO
SR7 = 1
?
NO
YES
Unprotect Sector
Operation Terminated
PLSCNT
= 25 ?
YES
NO
Device Failed
To
Verify Protect
Status ?
YES
Verify Protect Status Flow
(Figure 12)
NO
Data
= 00H ?
YES
Device Stays at
Read S.R. Mode
Write Data AAH Address 5555H
NOTE :
*Only the Top or the Bottom Sector Address is vaild in this feature.
i.e. Sector Address = (A19,A18,A17,A16,A15) = 00000B or 11111B
Write Data 55H Address 2AAAH
Write Data 60H Address 5555H
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data 40H, Sector Address*
Read Status Register
SR7 = 1
?
NO
YES
Sector Unprotected,Operation
Done, Device Stays at
Verify Sector Protect Mode
P/N:PM0511
REV. 2.4, NOV. 06, 2001
30
MX29L1611
Figure 12. VERIFY SECTOR PROTECT FLOW CHART
START
Write Data AAH, Address 5555H
Write Data 55H, Address 2AAAH
Write Data 90H, Address 5555H
Ptoect Status Read*
* 1. Protect Status:
Data Outputs C2H as Protected Sector Verified Code.
Data Outputs 00H as Unprotected Sector Verified Code.
2. Sepecified address will be either
(A19,A18,A17,A16,A15,A1,A0) = (0000010) or (1111110),
the rest of the address pins are don't care.
3. Silicon ID can be read via this Flow Chart.
Refer to Table 4.
P/N:PM0511
REV. 2.4, NOV. 06, 2001
31
MX29L1611
Figure 13. COMMAND WRITE TIMING WAVEFORMS(Alternate CE Controlled)
tWH
WE
tOES
tWS
OE
tWC
CE
tGHWL
tCPH
tCP
tAS
ADDRESSES
tAH
VALID
tDH
tDS
HIGH Z
DATA
(D/Q)
VCC
DIN
tVCS
NOTE:
1. BYTE pin is treated as Address pin. All timing specifications for BYTE pin are the same as those for address pin.
2. BYTE pin is sampled on the falling edge of WE or CE during the 3rd command write bus cycle; for real world applicaton,
BYTE oin should be either static high(word mode) or static low(byte mode).
P/N:PM0511
REV. 2.4, NOV. 06, 2001
32
MX29L1611
Figure 14. AUTOMATIC PAGE PROGRAM TIMING WAVEFORM(Alternate CE Controlled)
A0~A5
AAH
55H
55H
A-1
((Byte Mode Only)
55H
A6~A14
tAS
2AH
Word offset
Address
Last Word
Offset Address
Low/High
Byte Select
Last Low/High
Byte Select
Page Address
55H
tAH
Page Address
A15~A19
tWC
tBALC
WE
tCP
tCPH
tBAL
CE(1)
tCES
OE
tDS
tDH
tSRA
AAH
DATA
55H
A0H
Write
Last Write
Data
Data
SRD
NOTE:
1.Please refer to page 9 for detail page program operation.
P/N:PM0511
REV. 2.4, NOV. 06, 2001
33
MX29L1611
ERASE AND PROGRAMMING PERFORMANCE
PARAMETER
Chip/Sector Erase Time
Page Programming Time
Chip Programming Time
Byte Program Time
Erase/Program Cycles
MIN.
LIMITS
TYP.
200
5
80
40
MAX.
2000
500
800
4000
10,000
UNITS
ms
ms
sec
us
Cycles
1.All number are sampled, not 100% tested.
2.Typing values are measured at 25°C, VCC=3.3V
LATCHUP CHARACTERISTICS
Input Voltage with respect to GND on all pins except I/O pins
Input Voltage with respect to GND on all I/O pins
Current
Includes all pins except Vcc. Test conditions: Vcc = 3.3V, one pin at a time.
P/N:PM0511
MIN.
-1.0V
-1.0V
-100mA
MAX.
6.6V
Vcc + 1.0V
+100mA
REV. 2.4, NOV. 06, 2001
34
MX29L1611
ORDERING INFORMATION
PLASTIC PACKAGE
PART NO.
Access Time
Operating Current
Standby Current
PACKAGE
(ns)
MAX.(mA)
MAX.(uA)
MX29L1611MC-75
75
50
20
44 Pin SOP
MX29L1611MC-90
90
50
20
44 Pin SOP
MX29L1611MC-10
100
50
20
44 Pin SOP
MX29L1611MC-12
120
50
20
44 Pin SOP
MX29L1611TC-75
75
50
20
48 Pin TSOP
(Normal Type)
MX29L1611TC-90
90
50
20
48 Pin TSOP
(Normal Type)
MX29L1611TC-10
100
50
20
48 Pin TSOP
(Normal Type)
MX29L1611TC-12
120
50
20
48 Pin TSOP
(Normal Type)
P/N:PM0511
REV. 2.4, NOV. 06, 2001
35
MX29L1611
PACKAGE INFORMATION
44-PIN PLASTIC SOP
P/N:PM0511
REV. 2.4, NOV. 06, 2001
36
MX29L1611
48-PIN PLASTIC TSOP(NORMAL TYPE)
P/N:PM0511
REV. 2.4, NOV. 06, 2001
37
MX29L1611
HISTORY STORY
Revision Description
Page
1.1
Correct Page Programming waveform and delete RY/BY,PWD wafewaves
on Page 26 & Page 32 respetively
1.2
Revise page read speed to 30ns @CL=35pF on Page 1 & Page 19
Correct statement of ABORT MODE on Page 13.
1.3
Add 48 TSOP(I) package, and new read speed grade random access
P1,2,21,24
120ns, page mode access 40ns
1.4
Modify the data for erase and programming performance
P33
1.5
Add in ordering information
P34
1.6
Revised Package Information
P35,36
1.7
Revised random access time 100/120-->75/90
P1
Revised page mode access time 30/40-->25/30
P1
Revised device power supply VCC
P4
Revised switching test circuits
P19
Revised DC Characteristic Vcc=3.3V ±10%-->2.7V~3.6V
P20
Revised AC Characteristic
P21
Revised access time in package information
P34
1.8
Revised Fast Pagemode Access Time : 25/30 -->30/35
P1
Add 48 TSOP(Reverse Type)
1.9
Modify AC Characteristics--tSRA MIN:75/90-->MAX:75/90
P24
2.0
Add in note in the AC Characteristics
P21
2.1
Add 120ns in for fast random access time
P1
Add MX29L1611-12 in AC Characteristics
P21,24
Add MX29L1611MC-12 and MX29L1611TC-12
P34
2.2
Add 100ns in for fast random access time
P1
Add MX29L1611-10 in AC Characteristics
P21,25
Add MX29L1611MC-10 and MX29L1611TC-10
P34
2.3
Modify Switching Test Waveform Vcc/ 0 ---> 2.4V/0.45V
P19
Modify Test Conditions : Input pulse levels: 0/Vcc ---> 0.45V/2.4V
P21
Reference level for measuring timing Vcc/2 -->1.5V
P21
2.4
Remove 48-pin Reverse TSOP in Package Information
P37
P/N:PM0511
Date
APR/10/1998
SEP/09/1998
NOV/26/1998
JUN/28/1999
JUL/15/1999
JUL/22/1999
DEC/03/1999
JAN/18/2000
FEB/10/2000
FEB/21/2000
FEB/29/2000
JUN/09/2000
JUN/22/2000
NOV/06/2001
REV. 2.4, NOV. 06, 2001
38
MX29L1611
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
EUROPE OFFICE:
TEL:+32-2-456-8020
FAX:+32-2-456-8021
JAPAN OFFICE:
TEL:+81-44-246-9100
FAX:+81-44-246-9105
SINGAPORE OFFICE:
TEL:+65-348-8385
FAX:+65-348-8096
TAIPEI OFFICE:
TEL:+886-2-2509-3300
FAX:+886-2-2509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-453-8088
FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900
FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
39
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