IDT IDT72821 Dual cmos syncfifo Datasheet

IDT72801
IDT72811
IDT72821
IDT72831
IDT72841
IDT72851
DUAL CMOS SyncFIFO™
DUAL 256 x 9, DUAL 512 x 9,
DUAL 1,024 x 9, DUAL 2,048 x 9,
DUAL 4,096 x 9, DUAL 8,192 x 9
FEATURES:
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The IDT72801 is equivalent to two IDT72201 256 x 9 FIFOs
The IDT72811 is equivalent to two IDT72211 512 x 9 FIFOs
The IDT72821 is equivalent to two IDT72221 1,024 x 9 FIFOs
The IDT72831 is equivalent to two IDT72231 2,048 x 9 FIFOs
The IDT72841 is equivalent to two IDT72241 4,096 x 9 FIFOs
The IDT72851 is equivalent to two IDT72251 8,192 x 9 FIFOs
Offers optimal combination of large capacity, high speed,
design flexibility and small footprint
Ideal for prioritization, bidirectional, and width expansion
applications
10 ns read/write cycle time for the IDT72801/72811/72821/72831/
72841 (excluding the IDT72851)
15 ns read/write cycle time for the IDT72851
Separate control lines and data lines for each FIFO
Separate Empty, Full, Programmable Almost-Empty and AlmostFull flags for each FIFO
Enable puts output data lines in high-impedance state
Space-saving 64-pin Thin Quad Flat Pack (TQFP) and Slim Thin
Quad Flatpack (STQFP)
Industrial temperature range (–40°°C to +85°°C) is available
DESCRIPTION:
The IDT72801/72811/72821/72831/72841/72851 are dual synchronous
(clocked) FIFOs. The device is functionally equivalent to two IDT72201/72211/
72221/72231/72241/72251 FIFOs in a single package with all associated
control, data, and flag lines assigned to separate pins.
Each of the two FIFOs (designated FIFO A and FIFO B) contained in the
IDT72801/72811/72821/72831/72841/72851 has a 9-bit input data port (DA0
- DA8, DB0 - DB8) and a 9-bit output data port (QA0 - QA8, QB0 - QB8). Each
input port is controlled by a free-running clock (WCLKA, WCLKB), and two Write
Enable pins (WENA1, WENA2, WENB1, WENB2). Data is written into each of
the two arrays on every rising clock edge of the Write Clock (WCLKA, WCLKB)
when the appropriate write enable pins are asserted.
The output port of each FIFO bank is controlled by its associated clock pin
(RCLKA, RCLKB) and two Read Enable pins (RENA1, RENA2, RENB1,
RENB2). The Read Clock can be tied to the Write Clock for single clock operation
or the two clocks can run asynchronous of one another for dual clock operation.
An Output Enable pin (OEA, OEB) is provided on the read port of each FIFO
for three-state output control.
Each of the two FIFOs has two fixed flags, Empty (EFA, EFB) and Full (FFA,
FFB). Two programmable flags, Almost-Empty (PAEA, PAEB) and Almost-Full
(PAFA, PAFB), are provided for each FIFO bank to improve memory utilization.
If not programmed, the programmable flags default to empty+7 for PAEA and
PAEB, and full-7 for PAFA and PAFB.
The IDT72801/72811/72821/72831/72841/72851 architecture lends itself
to many flexible configurations such as:
• 2-level priority data buffering
• Bidirectional operation
• Width expansion
• Depth expansion
These FIFOs is fabricated using IDT's high-performance submicron
CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
WCLKA
WENA1
WENA2
EFA
PAEA
PAFA
LDA
FFA
DA0 - DA8
INPUT REGISTER
WRITE CONTROL
LOGIC
RAM ARRAY
256 x 9, 512 x 9,
1024 x 9, 2048 x 9,
4096 x 9, 8192 x 9
WRITE POINTER
WCLKB
WENB1
DB0 - DB8
OFFSET REGISTER
INPUT REGISTER
FLAG
LOGIC
WRITE CONTROL
LOGIC
READ POINTER
WRITE POINTER
OFFSET REGISTER
FLAG
LOGIC
RAM ARRAY
256 x 9, 512 x 9,
1024 x 9, 2048 x 9,
4096 x 9, 8192 x 9
READ CONTROL
LOGIC
EFB
PAEB
PAFB
FFB
READ POINTER
READ CONTROL
LOGIC
OUTPUT REGISTER
OUTPUT REGISTER
RESET LOGIC
RSA
LDB
WENB2
RESET LOGIC
OEA
QA0 - QA8
RCLKA
RENA1
RENA2
RSB
OEB
QB0 - QB8
RCLKB
RENB1
RENB2
3034 drw 01
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
 2001
Integrated Device Technology, Inc.
APRIL 2001
DSC-3034/1
Commercial And Industrial Temperature Range
IDT72801/728211/72821/72831/72841/72851
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
QA0
FFA
EFA
OEA
RENA2
RCLKA
RENA1
GND
QB8
QB7
QB6
QB5
QB4
QB3
QB2
QB1
PIN CONFIGURATION
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
QB0
FFB
EFB
OEB
RENB2
RCLKB
RENB1
GND
VCC
PAEB
PAFB
DB0
DB1
DB2
DB3
DB4
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DA5
DA4
DA3
DA2
DA1
DA0
PAFA
PAEA
WENB2/LDB
WCLKB
WENB1
RSB
DB8
DB7
DB6
DB5
QA1
QA2
QA3
QA4
QA5
QA6
QA7
QA8
VCC
WENA2/LDA
WCLKA
WENA1
RSA
DA8
DA7
DA6
TQFP (PN64-1, order code: PF)
STQFP (PP64-1, order code: TF)
TOP VIEW
2
3034 drw 02
Commercial And Industrial Temperature Range
IDT72801/728211/72821/72831/72841/72851
PIN DESCRIPTIONS
The IDT72801/72811/72821/72831/72841/72851s two FIFOs, referred
to as FIFO A and FIFO B, are identical in every respect. The following
description defines the input and output signals for FIFO A. The corresponding signal names for FIFO B are provided in parentheses.
Symbol
DA0-DA8
Name
A Data Inputs
I/O
I
DB0-DB8
RSA, RSB
B Data Inputs
Reset
I
I
9-bit data inputs to RAM array B.
When RSA (RSB) is set LOW, the associated internal read and write pointers of array A (B) are set to
the first location; FFA (FFB) and PAFA (PAFB) go HIGH, and PAEA (PAEB) and EFA (EFB) go
LOW. After power-up, a reset of both FIFOs A and B is required before an initial Write.
WCLKA
WCLKB
Write Clock
I
WENA1
WENB1
Write Enable 1
I
Data is written into the FIFO A (B) on a LOW-to-HIGH transition of WCLKA (WCLKB) when the write
enable(s) are asserted.
If FIFO A (B) is configured to have programmable flags, WENA1 (WENB1) is the only Write
Enable pin that can be used. When WENA1 (WENB1) is LOW, data A (B) is written into the FIFO
on every LOW-to-HIGH transition WCLKA (WCLKB). If the FIFO is configured to have two write enables,
WENA1 (WENB1) must be LOW and WENA2 (WENB2) must be HIGH to write data into the FIFO. Data
will not be written into the FIFO if FFA (FFB) is LOW.
WENA2/LDA
WENB2/LDB
Write Enable 2/
Load
I
QA0-QA8
A Data Outputs
O
QB0-QB8
RCLKA
RCLKB
B Data Outputs
Read Clock
O
I
9-bit data outputs from RAM array B.
Data is read from FIFO A (B) on a LOW-to-HIGH transition of RCLKA (RCLKB) when RENA1
(RENB1) and RENA2 (RENB2) are asserted.
RENA1
RENB1
Read Enable 1
I
RENA2
RENB2
Read Enable 2
I
When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from FIFO A (B) on every
LOW-to-HIGH transition of RCLKA (RCLKB). Data will not be read from Array A (B) if EFA (EFB) is LOW.
When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from the FIFO A (B) on every
LOW-to-HIGH transition of RCLKA (RCLKB). Data will not be read from array A (B) if the EFA (EFB) is LOW.
OEA
OEB
Output Enable
I
EFA
EFB
Empty Flag
O
PAEA
PAEB
Programmable
Almost-Empty
Flag
Programmable
Almost-Full Flag
O
FFA
FFB
Full Flag
O
VCC
GND
Power
Ground
PAFA
PAFB
O
Description
9-bit data inputs to RAM array A.
FIFO A (B) is configured at reset to have either two write enables or programmable flags. If LDA (LDB)
is HIGH at reset, this pin operates as a second write enable. If WENA2/LDA (WENB2/LDB) is LOW
at reset this pin operates as a control to load and read the programmable flag offsets for its respective array.
If the FIFO is configured to have two write enables, WENA1 ( WENB1) must be LOW
and WENA2 (WENB2) must be HIGH to write data into FIFO A (B). Data will not be written into FIFO A (B)
if FFA (FFB) is LOW. If the FIFO is configured to have programmable flags, LDA
(LDB) is held
LOW to write or read the programmable flag offsets.
9-bit data outputs from RAM array A.
When OEA (OEB) is LOW, outputs DA0-DA8 (DB0-DB8) are active. If OEA (OEB) is HIGH, the
outputs DA0-DA8 (DB0-DB8) will be in a high-impedance state.
When EFA (EFB) is LOW, FIFO A (B) is empty and further data reads from the output are inhibited.
When EFA (EFB) is HIGH, FIFO A (B) is not empty. EFA (EFB) is synchronized to RCLKA (RCLKB).
When PAEA (PAEB) is LOW, FIFO A (B) is almost-empty based on the offset programmed into the
appropriate offset register. The default offset at reset is Empty+7. PAEA (PAEB) is synchronized to
RCLKA (RCLKB).
When PAFA (PAFB) is LOW, FIFO A (B) is almost-full based on the offset programmed into the appropriate
offset register. The default offset at reset is Full-7. PAFA (PAFB) is synchronized to WCLKA (WCLKB).
When FFA (FFB) is LOW, FIFO A (B) is full and further data writes into the input are inhibited.
When FFA (FFB) is HIGH, FIFO A (B) is not full. FFA (FFB) is synchronized to WCLKA (WCLKB).
+5V power supply pin.
0V ground pin.
3
Commercial And Industrial Temperature Range
IDT72801/728211/72821/72831/72841/72851
ABSOLUTE MAXIMUM RATINGS
Symbol
VTERM
TSTG
IOUT
Rating
Com'l & Ind'l
Terminal Voltage with
Respect to GND
StorageTemperature
DC Output Current
–0.5 to +7.0
–55 to +125
–50 to +50
RECOMMENDEDOPERATINGCONDITIONS
Unit
Symbol
V
VCC
°C
mA
GND
VIH
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Parameter
Supply Voltage
(Com'l & Ind'l)
Supply Voltage
(Com'l & Ind'l)
Input High Voltage
(Com'l & Ind'l)
Input Low Voltage
(Com'l & Ind'l)
Operating Temperature
Commercial
Operating Temperature
Industrial
VIL
TA
TA
Min.
Typ.
Max. Unit
4.5
5.0
5.5
V
0
0
0
V
2.0
—
—
V
—
0
—
—
0.8 V
70 °C
–40
—
85
°C
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C)
IDT72801
IDT72811
IDT72821
IDT72831
IDT72841
Commercial and Industrial(1)
tCLK = 10, 15, 25 ns
Symbol
Parameter
Min.
Typ.
Max.
Input Leakage Current (Any Input)
–1
—
ILO(3)
Output Leakage Current
–10
VOH
Output Logic “1” Voltage, IOH = –2 mA
VOL
IDT72851
Commercial and Industrial(1)
tCLK = 10, 15, 25 ns
Min.
Typ.
Max.
Unit
1
–1
—
1
µA
—
10
–10
—
10
µA
2.4
—
—
2.4
—
—
V
Output Logic “0” Voltage, IOL = 8 mA
—
—
0.4
—
—
0.4
V
ICC1(4,5,6,8)
Active Power Supply Current (both FIFOs)
—
—
60
—
—
80
mA
ICC2(4,7,8)
Standby Current
—
—
10
—
—
10
mA
ILI
(2)
NOTES:
1. Industrial temperature range product for 15ns and 25ns speed grade are available as a standard device.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs open (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. Typical ICC1 = 2*[1.7 + 0.7*fS + 0.02*CL*fS] (in mA).
These equations are valid under the following conditions:
VCC = 5V, TA = 25°°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
8. ICC1 and ICC2 parameters are improved as compared to previous data sheets.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
(2)
CIN
COUT
(1,2)
Parameter
Conditions
Max.
Unit
Input Capacitance
VIN = 0V
10
pF
Output Capacitance
VOUT = 0V
10
pF
NOTE:
1. With output deselected (OEA, OEB ≥ VIH).
2. Characterized values, not currently tested.
4
Commercial And Industrial Temperature Range
IDT72801/728211/72821/72831/72841/72851
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C)
Com'l &
Ind'l (1)
Commercial
IDT72801L10
IDT72811L10
IDT72821L10
IDT72831L10
IDT72841L10
IDT72851L10
IDT72801L15
IDT72811L15
IDT72821L15
IDT72831L15
IDT72841L15
IDT72851L15
IDT72801L25
IDT72811L25
IDT72821L25
IDT72831L25
IDT72841L25
IDT72851L25
Symbol
Parameter
Min
Max.
Min
Max.
Min
Max.
Unit
fS
Clock Cycle Frequency
—
100
—
66.7
—
40
MHz
tA
Data Access Time
2
6.5
2
10
2
15
ns
tCLK
Clock Cycle Time
10
—
15
—
25
—
ns
tCLKH
Clock High Time
4.5
—
6
—
10
—
ns
tCLKL
Clock Low Time
4.5
—
6
—
10
—
ns
tDS
Data Setup Time
3
—
4
—
6
—
ns
tDH
Data Hold Time
0.5
—
1
—
1
—
ns
tENS
Enable Setup Time
3
—
4
—
6
—
ns
tENH
Enable Hold Time
0.5
—
1
—
1
—
ns
(2)
tRS
Reset Pulse Width
10
—
15
—
15
—
ns
tRSS
Reset Setup Time
8
—
10
—
15
—
ns
tRSR
Reset Recovery Time
8
—
10
—
15
—
ns
tRSF
Reset to Flag Time and Output Time
—
10
—
15
—
25
ns
0
—
0
—
0
—
ns
3
6
3
8
3
13
ns
ns
tOLZ
Output Enable to Output in
Low-Z(3)
tOE
Output Enable to Output Valid
tOHZ
Output Enable to Output in High-Z(3)
3
6
3
8
3
13
tWFF
Write Clock to Full Flag
—
6.5
—
10
—
15
ns
tREF
Read Clock to Empty Flag
—
6.5
—
10
—
15
ns
tPAF
Write Clock to Programmable
Almost-Full Flag
—
6.5
—
10
—
15
ns
tPAE
Read Clock to Programmable
Almost-Empty Flag
—
6.5
—
10
—
15
ns
tSKEW1
Skew Time Between Read Clock and
Write Clock for Empty Flag and Full Flag
5
—
6
—
10
—
ns
tSKEW2
Skew Time Between Read Clock and Write
Clock for Programmable Almost-Empty Flag
and Programmable Almost-Full Flag
14
—
15
—
18
—
ns
NOTES:
1. Industrial temperature range product for 15ns and 25ns speed grade are available as a standard device.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
5V
1.1K
D.U.T.
AC TEST CONDITIONS
In Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
680Ω
30pF*
3034 drw 03
or equivalent circuit
See Figure 1
Figure 1. Output Load
*Includes jig and scope capacitances.
5
Commercial And Industrial Temperature Range
IDT72801/728211/72821/72831/72841/72851
SIGNAL DESCRIPTIONS
When either of the two Read Enable RENA1, RENA2 (RENB1, RENB2)
associated with FIFO A (B) is HIGH, the output register holds the previous data
and no new data is allowed to be loaded into the register.
When all the data has been read from FIFO A (B), the Empty Flag EFA (EFB)
will go LOW, inhibiting further read operations. Once a valid write operation has
been accomplished, EFA (EFB) will go HIGH after tREF and a valid read can
begin. The Read Enables RENA1, RENA2(RENB1, RENB2) are ignored when
FIFO A (B) is empty.
FIFO A and FIFO B are identical in every respect. The following description
explains the interaction of input and output signals for FIFO A. The corresponding signal names for FIFO B are provided in parentheses.
INPUTS:
Data In (DA0 – DA8, DB0 – DB8) —DA0 - DA8 are the nine data inputs
for memory array A. DB0 - DB8 are the nine data inputs for memory array B.
Output Enable (OEA, OEB) — When Output Enable OEA (OEB) is enabled
(LOW), the parallel output buffers of FIFO A (B) receive data from their respective
output register. When Output Enable OEA (OEB) is disabled (HIGH), the QA
(QB) output data bus is in a high-impedance state.
CONTROLS:
Reset (RSA, RSB) — Reset of FIFO A (B) is accomplished whenever RSA
(RSB) input is taken to a LOW state. During Reset, the internal read and write
pointers associated with the FIFO are set to the first location. A Reset is required
after power-up before a write operation can take place. The Full Flag FFA (FFB)
and Programmable Almost-Full flag PAFA (PAFB) will be reset to HIGH after
tRSF. The Empty Flag EFA (EFB) and Programmable Almost-Empty flag PAEA
(PAEB) will be reset to LOW after tRSF. During Reset, the output register is
initialized to all zeros and the offset registers are initialized to their default values.
Write Enable 2/Load (WENA2/LDA, WENB2/LDB) — This is a dualpurpose pin. FIFO A (B) is configured at Reset to have programmable flags
or to have two write enables, which allows depth expansion. If WENA2/LDA
(WENB2/LDB) is set HIGH at Reset RSA = LOW (RSB = LOW), this pin operates
as a second write enable pin.
If FIFO A (B) is configured to have two write enables, when Write Enable
1 WENA1 (WENB1) is LOW and WENA2/LDA (WENB2/LDB) is HIGH, data can be
loaded into the input register and RAM array on the LOW-to-HIGH transition
of every Write Clock WCLKA (WCLKB). Data is stored in the array sequentially
and independently of any ongoing read operation.
In this configuration, when WENA1 (WENB1) is HIGH and/or WENA2/LDA
(WENB2/LDB) is LOW, the input register of Array A holds the previous data and
no new data is allowed to be loaded into the register.
To prevent data overflow, the Full Flag FFA (FFB) will go LOW, inhibiting
further write operations. Upon the completion of a valid read cycle, FFA (FFB)
will go HIGH after tWFF, allowing a valid write to begin. WENA1, (WENB1) and
WENA2/LDA (WENB2/LDB) are ignored when the FIFO is full.
FIFO A (B) is configured to have programmable flags when the WENA2/
LDA (WENB2/LDB) is set LOW at Reset RSA = LOW (RSB = LOW). Each FIFO
contains four 8-bit offset registers which can be loaded with data on the inputs,
or read on the outputs. See Figure 3 for details of the size of the registers and
the default values.
If FIFO A (B) is configured to have programmable flags, when the WENA1
(WENB1) and WENA2/LDA (WENB2/LDB) are set LOW, data on the DA (DB)
inputs are written into the Empty (Least Significant Bit) Offset register on the first
LOW-to-HIGH transition of the WCLKA (WCLKB). Data are written into the
Empty (Most Significant Bit) Offset register on the second LOW-to-HIGH
transition of WCLKA (WCLKB), into the Full (Least Significant Bit) Offset register
on the third transition, and into the Full (Most Significant Bit) Offset register on
the fourth transition. The fifth transition of WCLKA (WCLKB) again writes to the
Empty (Least Significant Bit) Offset register.
However, writing all offset registers does not have to occur at one time. One
or two offset registers can be written and then by bringing LDA (LDB) HIGH, FIFO
A (B) is returned to normal read/write operation. When LDA (LDB) is set LOW,
and WENA1 (WENB1) is LOW, the next offset register in sequence is written.
The contents of the offset registers can be read on the QA (QB) outputs when
WENA2/LDA (WENB2/LDB) is set LOW and both Read Enables RENA1, RENA2
(RENB1, RENB2) are set LOW. Data can be read on the LOW-to-HIGH transition
of the Read Clock RCLKA (RCLKB).
Write Clock (WCLKA, WCLKB) — A write cycle to Array A (B) is
initiated on the LOW-to-HIGH transition of WCLKA (WCLKB). Data setup
and hold times must be met with respect to the LOW-to-HIGH transition of
WCLKA (WCLKB). The Full Flag FFA (FFB) and Programmable Almost-Full
flag PAFA (PAFB) are synchronized with respect to the LOW-to-HIGH transition
of the Write Clock WCLKA (WCLKB).
The Write and Read Clocks can be asynchronous or coincident.
Write Enable 1 (WENA1, WENB1) — If FIFO A (B) is configured for
programmable flags, WENA1 (WENB1) is the only enable control pin. In this
configuration, when WENA1 (WENB1) is LOW, data can be loaded into the input
register of RAM Array A (B) on the LOW-to-HIGH transition of every Write Clock
WCLKA (WCLKB). Data is stored in Array A (B) sequentially and independently
of any ongoing read operation.
In this configuration, when WENA1 (WENB1) is HIGH, the input register holds
the previous data and no new data is allowed to be loaded into the register.
If the FIFO is configured to have two write enables, which allows for depth
expansion. See Write Enable 2 paragraph below for operation in this
configuration.
To prevent data overflow, FFA (FFB) will go LOW, inhibiting further write
operations. Upon the completion of a valid read cycle, the FFA (FFB) will go HIGH
after tWFF, allowing a valid write to begin. WENA1 (WENB1) is ignored when FIFO
A (B) is full.
Read Clock (RCLKA, RCLKB) — Data can be read from Array A (B) on
the LOW-to-HIGH transition of RCLKA (RCLKB). The Empty Flag EFA (EFB)
and Programmable Almost-Empty Flag PAEA (PAEB) are synchronized with
respect to the LOW-to-HIGH transition of RCLKA (RCLKB).
The Write and Read Clocks can be asynchronous or coincident.
Read Enables (RENA1, RENA2, RENB1, RENB2) — When both Read
Enables RENA1, RENA2 (RENB1, RENB2) are LOW, data is read from Array
A (B) to the output register on the LOW-to-HIGH transition of the Read Clock
RCLKA (RCLKB).
6
Commercial And Industrial Temperature Range
IDT72801/728211/72821/72831/72841/72851
LDA
WENA1
WCLKA
OPERATION ON FIFO A
LDB
WENB1
WCLKB
OPERATION ON FIFO B
0
0
A read and write should not be performed simultaneously to the offset
registers.
Empty Offset (LSB)
OUTPUTS:
Empty Offset (MSB)
Full Flag (FFA, FFB) — FFA (FFB) will go LOW, inhibiting further write
operations, when Array A (B) is full. If no reads are performed after reset, FFA
(FFB) will go LOW after 256 writes to the IDT72801's FIFO A (B); 512 writes
to the IDT72811's FIFO A (B); 1,024 writes to the IDT72821's FIFO A (B); 2,048
writes to the IDT72831's FIFO A (B); 4,096 writes to the IDT72841's FIFO A
(B); or 8,192 writes to the IDT72851's FIFO A (B).
FFA (FFB) is synchronized with respect to the LOW-to-HIGH transition of the
Write Clock WCLKA (WCLKB).
Full Offset (LSB)
Full Offset (MSB)
0
1
No Operation
1
0
Write Into FIFO
1
1
No Operation
Empty Flag (EFA, EFB) — EFA (EFB) will go LOW, inhibiting further read
operations, when the read pointer is equal to the write pointer, indicating that
Array A (B) is empty.
EFA (EFB) is synchronized with respect to the LOW-to-HIGH transition of
the Read Clock RCLKA (RCLKB).
NOTE:
1. For the purposes of this table, WENA1 and WENB1 = VIH.
2. The same selection sequence applies to reading from the registers. RENA1 and
RENA2 (RENB1 and RENB2) are enabled and read is performed on the LOW-toHIGH transition of RCLKA (RCLKB).
Figure 2. Writing to Offset Registers for FIFOs A and B
72801 - DUAL 256 x 9
8
0
8
0
7
Empty Offset (LSB)
Default Value 007H
Default Value 007H
Default Value 007H
0
7
0
8
0
1
8
8
8
8
(MSB)
0
0
0
8
8
0
7
Full Offset (LSB) Reg.
Default Value 007H
Default Value 007H
1
0
8
0
1
(MSB)
(MSB)
0
0
72841 - DUAL 4,096 x 9
0
0
1
Full Offset (LSB)
8
72851 - DUAL 8,192 x 9
0
7
8
0
7
Empty Offset (LSB) Reg.
Empty Offset (LSB)
Empty Offset (LSB)
Default Value 007H
Default Value 007H
Default Value 007H
0
2
3
8
0
8
4
0
(MSB)
(MSB)
(MSB)
0
0
0
7
0
8
Full Offset (LSB) Reg.
Default Value 007H
8
0
(MSB)
7
72831 - DUAL 2,048 x 9
7
8
0
7
Empty Offset (LSB)
Full Offset (LSB) Reg.
Default Value 007H
8
8
Empty Offset (LSB) Reg.
8
8
72821 - DUAL 1,024 x 9
72811 - DUAL 512 x 9
7
0
2
0
7
8
0
7
Full Offset (LSB)
Full Offset (LSB)
Default Value 007H
Default Value 007H
3
8
0
8
4
0
(MSB)
(MSB)
(MSB)
0
0
0
3034 drw 04
Figure 3. Offset Register Formats and Default Values for the A and B FIFOs
7
Commercial And Industrial Temperature Range
IDT72801/728211/72821/72831/72841/72851
Programmable Almost–Full Flag (PAFA, PAFB) — PAFA (PAFB) will go
LOW when the amount of data in Array A (B) reaches the almost-full condition.
If no reads are performed after Reset, PAFA (PAFB) will go LOW after (256-m)
writes to the IDT72801's FIFO A (B); (512-m) writes to the IDT72811's FIFO
A (B); (1,024-m) writes to the IDT72821's FIFO A (B); (2,048-m) writes to the
IDT72831's FIFO A (B); (4,096-m) writes to the IDT72841's FIFO A (B); or
(8,192-m) writes to the IDT72851's FIFO A (B).
FFA (FFB) is synchronized with respect to the LOW-to-HIGH transition of the
Write Clock WCLKA (WCLKB). The offset “m” is defined in the Full Offset
registers.
If there is no Full offset specified, PAFA (PAFB) will go LOW at Full-7 words.
PAFA (PAFB) is synchronized with respect to the LOW-to-HIGH transition
of WCLKA (WCLKB).
Programmable Almost–Empty Flag (PAEA, PAEB) — PAEA (PAEB) will
go LOW when the read pointer is "n+1" locations less than the write pointer. The
offset "n" is defined in the Empty Offset registers. If no reads are performed after
Reset, PAEA (PAEB) will go HIGH after "n+1" writes to FIFO A (B).
If there is no Empty offset specified, PAEA (PAEB) will go LOW at Empty+7
words.
PAEA (PAEB) is synchronized with respect to the LOW-to-HIGH transition
of the Read Clock RCLKA (RCLKB).
Data Outputs (QA0 – QA8, QB0 – QB8 ) — QA0 - QA8 are the nine data
outputs for memory array A, QB0 - QB8 are the nine data outputs for memory
array B.
TABLE 1: STATUS FLAGS FOR A AND B FIFOS
NUMBER OF WORDS IN ARRAY A
NUMBER OF WORDS IN ARRAY B
72801
0
1 to n(1)
(n+1) to (256-(m+1))
(256-m)(2) to 255
256
72811
0
1 to n(1)
(n+1) to (512-(m+1))
(512-m)(2) to 511
512
72821
0
1 to n(1)
(n+1) to (1,024-(m+1))
(1,024-m)(2) to 1,023
1,024
NUMBER OF WORDS IN ARRAY A
NUMBER OF WORDS IN ARRAY B
72831
0
1 to n(1)
(n+1) to (2,048-(m+1))
(2,048-m)(2) to 2,047
2,048
72841
0
1 to n(1)
(n+1) to (4,096-(m+1))
(4,096-m)(2) to 4,095
4,096
72851
0
1 to n(1)
(n+1) to (8,192-(m+1))
(8,192-m)(2) to 8,191
8,192
NOTES:
1. n = Empty Offset (n = 7 default value)
2. m = Full Offset (m = 7 default value)
8
FFA
PAFA
PAEA
EFA
FFB
PAFB
PAEB
EFB
H
H
H
L
L
L
L
H
H
H
FFA
PAFA
PAEA
EFA
FFB
PAFB
PAEB
EFB
H
H
H
L
L
L
L
H
H
H
H
H
H
H
L
H
H
H
H
L
L
H
H
H
H
L
H
H
H
H
Commercial And Industrial Temperature Range
IDT72801/728211/72821/72831/72841/72851
tRS
RSA (RSB)
tRSS
tRSR
tRSS
tRSR
tRSS
tRSR
RENA1, RENA2
(RENB1, RENB2)
WENA1
(WENB1)
WENA2/LDA(1)
(WENB2/LDB)
tRSF
EFA, PAEA
(EFB, PAEB)
tRSF
FFA, PAFA
(FFB, PAFB)
tRSF
(2)
OEA (OEB) = 1
QA0 - QA8
(QB0 - QB8)
OEA (OEB) = 0
3034 drw 05
NOTES:
1. Holding WENA2/LDA (WENB2/LDB) HIGH during reset will make the pin act as a second write enable pin. Holding WENA2/LDA (WENB2/LDB) LOW
during reset will make the pin act as a load enable for the programmable flag offset registers.
2. After reset, QA0 - QA8 (QB0 - QB8) will be LOW if OEA (OEB) = 0 and tri-state if OEA (OEB) = 1.
3. The clocks RCLKA, WCLKA (RCLKB, WCLKB) can be free-running during reset.
Figure 4. Reset Timing
tCLK
tCLKH
tCLKL
WCLKA (WCLKB)
tDS
tDH
DA0 - DA8
(DB0 - DB8)
DATA IN VALID
tENS
WENA1
(WENB1)
tENH
NO OPERATION
tENS
tENH
WENA2 (WENB2)
(If Applicable)
NO OPERATION
tWFF
tWFF
FFA
(FFB)
tSKEW1(1)
RCLKA (RCLKB)
RENA1, RENA2
(RENB1, RENB2)
3034 drw 06
NOTE:
1. tSKEW1 is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for FFA (FFB) to change during the current clock cycle. If the time between
the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then FFA (FFB) may not change state until the next WCLKA (WCLKB) edge.
Figure 5. Write Cycle Timing
9
Commercial And Industrial Temperature Range
IDT72801/728211/72821/72831/72841/72851
tCLK
tCLKH
tCLKL
RCLKA (RCLKB)
tENS
tENH
RENA1, RENA2
(RENB1, RENB2)
NO OPERATION
tREF
tREF
EFA (EFB)
tA
QA0 - QA8
(QB0 - QB8)
VALID DATA
tOLZ
tOHZ
tOE
OEA (OEB)
tSKEW1(1)
WCLKA (WCLKB)
WENA1 (WENB1)
WENA2 (WENB2)
3034 drw 07
NOTE:
1. tSKEW1 is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for EFA (EFB) to change during the current clock cycle. If the time
between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then EFA (EFB) may not change state until the next RCLKA (RCLKB)
Figure 6. Read Cycle Timing
WCLKA (WCLKB)
tDS
DA0 - DA8
(DB0 - DB8)
D1
D2
D3
D0 (First Valid Write)
tENS
WENA1 (WENB1)
tENS
WENA2 (WENB2)
(If Applicable)
tSKEW1
tFRL (1)
RCLKA (RCLKB)
tREF
EFA (EFB)
tENS
RENA1, RENA2
(RENB1, RENB2)
tA
tA
QA0 - QA8
(QB0 - QB8)
D0
D1
tOLZ
tOE
OEA (OEB)
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1V or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EFA, EFB = LOW).
3034 drw 08
Figure 7. First Data Word Latency Timing
10
Commercial And Industrial Temperature Range
IDT72801/728211/72821/72831/72841/72851
NO WRITE
NO WRITE
WCLKA
(WCLKB)
tSKEW1
tDS
NO WRITE
tSKEW1
tDH
DA0 - DA8
(DB0 - DB8)
tWFF
tWFF
tWFF
FFA (FFB)
(1)
tENS
tENH
tENS
tENS
tENH
tENS
WENA1
(WENB1)
(1)
WENA2
(WENB2)
(If Applicable)
RCLKA
(RCLKB)
tENH
tENH
tENS
tENS
RENA1
(RENB2)
tA
OEA LOW
(OEB)
tA
QA0 - QA8
(QB0 - QB8)
DATA READ
DATA IN OUTPUT REGISTER
NEXT DATA READ
3034 drw 09
NOTE:
1. Only one of the two write enable inputs, WEN1 or WEN2, needs to go inactive to inhibit writes to the FIFO.
Figure 8. Full Flag Timing
WCLKA (WCLKB)
tDS
tDS
DA0 - DA8
(DB0 - DB8)
DATA WRITE 1
DATA WRITE 2
tENS
tENH
tENS
tENS
tENH
tENS
tENH
WENA1, (WENB1)
WENA2 (WENB2)
(If Applicable)
tENH
(1)
(1)
tFRL
tSKEW1
tSKEW1
tFRL
RCLKA (RLCKB)
tREF
tREF
tREF
EFA (EFB)
RENA1, RENA2
(RENB1, RENB2)
OEA (OEB)
LOW
tA
QA0-QA8
(QB0-QB8)
DATA IN OUTPUT REGISTER
DATA READ
3034 drw 10
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EFA, EFB = LOW).
Figure 9. Empty Flag Timing
11
Commercial And Industrial Temperature Range
IDT72801/728211/72821/72831/72841/72851
tCLKH
tCLKL
(4)
WCLKA
(WCLKB)
tENS
tENH
tENS
tENH
WENA1
(WENB1)
WENA2 (WENB2)
(If Applicable)
tPAF
PAFA
(PAFB)
Full - (m+1) words in FIFO
(2)
(1)
Full - m words in FIFO
(3)
tSKEW2
tPAF
RCLKA (RCLKB)
tENS
tENH
RENA1, RENA2
(RENB1, RENB2)
3034 drw 11
NOTES:
1. m = PAF offset.
2. (256-m) words for the IDT72801; (512-m) words the IDT72811; (1,024-m) words for the IDT72821; (2,048-m) words for the IDT72831; (4,096-m) words for the IDT72841; or (8,192-m)
words for the IDT72851.
3. tSKEW2 is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for PAFA (PAFB) to change during that clock cycle. If the time between the
rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW2, then PAFA (PAFB) may not change state until the next WCLKA (WCLKB) rising edge.
4. If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words in FIFO A (B) when PAFA (PAFB) goes LOW.
Figure 10. Programmable Full Flag Timing
tCLKH
tCLKL
WCLKA (WCLKB)
tENS
tENH
tENS
tENH
WENA1
(WENB1)
WENA2 (WENB2)
(If Applicable)
PAEA,
PAEB
n words in FIFO
(1)
tSKEW2
n+1 words in FIFO
(2)
tPAE
(3)
tPAE
RCLKA (RCLKB)
tENS
RENA1, RENA2
(RENB1, RENB2)
tENH
3034 drw 12
NOTES:
1. n = PAE offset.
2. tSKEW2 is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for PAEA (PAEB) to change during that clock cycle. If the time between the
rising edge of WCLKA (WCLKB) and the rising edge of RCLKA (RCLKB) is less than tSKEW2, then PAEA (PAEB) may not change state until the next RCLKA (RCLKB) rising edge.
3. If a read is performed on this rising edge of the read clock, there will be Empty + (n-1) words in FIFO A (B) when PAEA (PAEB) goes LOW.
Figure 11. Programmable Empty Flag Timing
12
Commercial And Industrial Temperature Range
IDT72801/728211/72821/72831/72841/72851
tCLK
tCLKL
WCLKA (WCLKB)
tENH
tENS
LDA (LDB)
tENS
WENA1 (WENB1)
tDH
tDS
DA0 - DA7
(DB0 - DB7)
PAE OFFSET
(LSB)
PAE OFFSET
(MSB)
PAF OFFSET
(LSB)
PAF OFFSET
(MSB)
3034 drw 13
Figure 12. Write Offset Register Timing
tCLK
tCLKH
tCLKL
RCLKA (RCLKB)
tENS
tENH
LDA (LDB)
tENS
RENA1, RENA2
(RENB1, RENB2)
tA
QA0 - QA7
(QB0 - QB7)
DATA IN OUTPUT REGISTER
EMPTY OFFSET
(LSB)
EMPTY OFFSET
(MSB)
FULL OFFSET
(LSB)
FULL OFFSET
(MSB)
3034 drw 14
Figure 13. Read Offset Register Timing
13
Commercial And Industrial Temperature Range
IDT72801/728211/72821/72831/72841/72851
OPERATING CONFIGURATIONS
can be grounded (see Figure 14). In this configuration, the Write Enable 2/
Load WENA2/LDA (WENB2/LDB) pin is set LOW at Reset so that the pin
operates as a control to load and read the programmable flag offsets.
SINGLE DEVICE CONFIGURATION — When FIFO A (B) is in a Single
Device Configuration, the Read Enable 2 RENA2 (RENB2) control input
RSA (RSB)
WCLKA (WCLKB)
RCLKA (RCLKB)
WENA1 (WENB1)
RENA1 (RENB1)
IDT
72801
72811
72821
72831
72841
72851
WENA2/LDA (WENB2/LDB)
DA0 - DA8 (DB0 - DB8)
FFA (FFB)
PAFA (PAFB)
OEA (OEB)
QA0 - QA8 (QB0 - QB8)
EFA (EFB)
PAEA (PAEB)
FIFO
A (B)
RENA2 (RENB2)
3034 drw 15
Figure 14. Block Diagram of One of the IDT72801/72811/72821/72831/72841/72851's two FIFOs
configured as a single device
WIDTH EXPANSION CONFIGURATION — Word width may be increased simply by connecting the corresponding input control signals of
FIFOs A and B. A composite flag should be created for each of the endpoint
status flags EFA and EFB, also FFA and FFB). The partial status flags
PAEA, PAFB, PAEA and PAFB can be detected from any one device.
Figure 15 demonstrates an 18-bit word width using the two FIFOs contained
in one IDT72801/72811/72821/72831/72841/72851. Any word width can
be attained by adding additional IDT72801/72811/72821/72831/72841/
72851s.
When these devices are in a Width Expansion Configuration, the Read
Enable 2 (RENA2 and RENB2) control inputs can be grounded (see
Figure 15). In this configuration, the Write Enable 2/Load (WENA2/LDA,
WENB2/LDB) pins are set LOW at Reset so that the pin operates as a
control to load and read the programmable flag offsets.
9
RESET
RSA
DATA IN
18
9
DA0 - DA8
WRITE CLOCK
WCLKA
WRITE ENABLE
WENA1
WRITE ENABLE/LOAD
WENA2/LDA
FULL FLAG
FFA
FFB
DB0 - DB8
RAM
ARRAY
A
256x9
512x9
1,024x9
2,048x9
4,096x9
8,192x9
RSB
EFA
EFB
RAM
RCLKA
ARRAY RCLKB
B
WCLKB
256x9 RENB1
RENA1
WENB1 512x9
1,024x9 OEB
OEA1
2WENB2/LDB 2,048x9
4,096x9
8,192x9 QB0 - QB8
RENA2
EMPTY FLAG
READ CLOCK
READ ENABLE
OUTPUT ENABLE
9
18
DATA OUT
QA0 - QA8 RENB2
9
Figure 15. Block diagram of the two FIFOs contained in one IDT72801/72811/
72821/72831/72841/72851 configured for an 18-bit width-expansion
14
3034 drw 16
Commercial And Industrial Temperature Range
IDT72801/728211/72821/72831/72841/72851
TWO PRIORITY DATA BUFFER
CONFIGURATION
data according to type, sending one kind to FIFO A and the other kind to FIFO
B. Then, at the outputs, each data type is transferred to its appropriate
destination. Additional IDT72801/72811/72821/72831/72841/72851s permit
more than two priority levels. Priority buffering is particularly useful in network
applications.
The two FIFOs contained in the IDT72801/72811/72821/72831/72841/
72851 can be used to prioritize two different types of data shared on a system
bus. When writing from the bus to the FIFO, control logic sorts the intermixed
Clock
Control
Logic
9
Image Processing
Card
RAM ARRAY A
RCLKA
WCLKA
OEA
WENA1
RENA
VCC
Data
9
QA0-QA8
WENA2 RENA2
IDT
72801
72811
72821
72831
72841
72851
Data
Voice Processing
Card
RAM ARRAY B
WCLKB RCLKB
WENB1
RAM
Clock
OEB2
RENB1
9
Address
Control
I/O Data
DB0-DB8
Data
QB0-QB8
WENB2 RENB2
9
I/O Data
Control
Logic
Control
9-bit bus
Control
Logic
Address
Control
9
DA0-DA8
Processor
Clock
Address
9
3034 drw 17
VCC
Figure 16. Block Diagram of Two Priority Configuration
BIDIRECTIONAL CONFIGURATION
processor can write data to a peripheral controller via FIFO A, and, in turn,
the peripheral controller can write the processor via FIFO B.
The two FIFOs of the IDT72801/72811/72821/72831/72841/72851 can
be used to buffer data flow in two directions. In the example that follows, a
RAM ARRAY A
WENA2 RENA2
WENA1
9
Data
9
9-bit bus
Control
Logic
Control
OEA
RENA1
DA0-DA8
QA0-QA8
IDT
72801
72811
72821
72831
72841
72851
Processor
Clock
Address
RCLKA
Peripheral
Controller
DMA Clock
9
Control
Logic
WCLKA
9-bit bus
VCC
RAM ARRAY B
RCLKB
Address
Control
I/O Data
Data
9
WENB1
RENB1
RAM
9
9
WCLKB
OEB
QB0-QB8
DB0-DB8
RENB2 WENB2
9
Figure 17. Block Diagram of Bidirectional Configuration
15
3034 drw 18
DEPTH EXPANSION — IDT72801/72811/72821/72831/72841/72851
can be adapted to applications that require greater than 256/512/1,024/
2,048/4,096/8,192 words. The existence of double enable pins on the read
and write ports allow depth expansion. The Write Enable 2/Load (WENA2,
WENB2) pins are used as a second write enables in a depth expansion
configuration, thus the Programmable flags are set to the default values.
Depth expansion is possible by using one enable input for system control
while the other enable input is controlled by expansion logic to direct the flow
of data. A typical application would have the expansion logic alternate data
access from one device to the next in a sequential manner. These FIFOs
operate in the Depth Expansion configuration when the following conditions
are met:
1. WENA2/LDA and WENB2/LDB pins are held HIGH during Reset so
that these pins operate as second Write Enables.
2. External logic is used to control the flow of data.
Please see the Application Note" DEPTH EXPANSION OF IDT'S SYNCHRONOUS FIFOs USING THE RING COUNTER APPROACH" for details
of this configuration.
ORDERING INFORMATION
IDT
XXXXX
Device Type
X
Power
XX
Speed
XX
Package
X
Process/
Temperature
Range
BLANK
I(1)
Commercial (0 C to +70 C)
Industrial (-40 C to +85 C)
PF
TF
Thin Quad Flatpack (TQFP, PN64-1)
Slim Thin Quad Flatpack(STQFP, PP64-1)
10
15
25
Commercial Only
Commercial and Industrial
Commercial and Industrial
L
Low Power
72801
72811
72821
72831
72841
72851
256 x 9 Dual SyncFIFO
512 x 9 Dual SyncFIFO
1,024 x 9 Dual SyncFIFO
2,048 x 9 Dual SyncFIFO
4,096 x 9 Dual SyncFIFO
8,192 x 9 Dual SyncFIFO
Clock Cycle Time
(tCLK), Speed in
Nanoseconds
3034 drw 19
NOTES:
1. Industrial temperature range product for 15ns and 25ns speed grade are available as a standard device.
DATASHEET DOCUMENT HISTORY
04/24/2001
pgs. 4, 5 and 16
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
for TECH SUPPORT:
(408) 330-1753
e-mail: [email protected]
PF Pkg: www.idt.com/docs/PSC4036.pdf
TF Pkg: www.idt.com/docs/PSC4046.pdf
The SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
16
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