ON NIF62514 Self−protected fet with temperature and current limit Datasheet

NIF62514
Preferred Device
Self−protected FET
with Temperature and
Current Limit
HDPlus devices are an advanced series of power MOSFETs which
utilize ON Semiconductor’s latest MOSFET technology process to
achieve the lowest possible on−resistance per silicon area while
incorporating smart features. Integrated thermal and current limits
work together to provide short circuit protection. The devices feature
an integrated Drain−to−Gate Clamp that enables them to withstand
high energy in the avalanche mode. The Clamp also provides
additional safety margin against unexpected voltage transients.
Electrostatic Discharge (ESD) protection is provided by an integrated
Gate−to−Source Clamp.
Features
•
•
•
•
•
•
•
•
•
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6.0 AMPERES*
40 VOLTS CLAMPED
RDS(on) = 90 mW
Drain
Gate
Input
Current Limitation
Thermal Shutdown with Automatic Restart
Short Circuit Protection
Low RDS(on)
IDSS Specified at Elevated Temperature
Avalanche Energy Specified
Slew Rate Control for Low Noise Switching
Overvoltage Clamped Protection
Pb−Free Packages are Available
RG
Temperature
Limit
4
Value
Unit
Drain−to−Source Voltage Internally Clamped
VDSS
40
Vdc
Drain−to−Gate Voltage Internally Clamped
(RGS = 1.0 MW)
VDGR
40
Vdc
VGS
"16
Vdc
Total Power Dissipation @ TA = 25°C (Note 1)
@ TA = 25°C (Note 2)
@ TA = 25°C (Note 3)
ID
ID
IDM
Internally
Limited
PD
1.1
1.73
8.93
W
3
1
GATE
4
DRAIN
3
DRAIN
SOURCE
14
114
72.3
°C/W
Single Pulse Drain−to−Source Avalanche Energy
(VDD = 25 Vdc, VGS = 5.0 Vdc,
VDS = 40 Vdc, IL = 2.8 Apk, L = 80 mH,
RG = 25 W)
EAS
300
mJ
TJ, Tstg
−55 to
150
°C
A
= Assembly Location
Y
= Year
W
= Work Week
62514 = Specific Device Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Mounted onto min pad board.
2. Mounted onto 1″ pad board.
3. Mounted onto large heatsink.
April, 2006 − Rev. 5
2
SOT−223
CASE 318E
STYLE 3
2
RqJT
RqJA
RqJA
© Semiconductor Components Industries, LLC, 2006
Current
Sense
MARKING DIAGRAM
Thermal Resistance, Junction−to−Tab
Junction−to−Ambient (Note 1)
Junction−to−Ambient (Note 2)
Operating and Storage Temperature Range
1
AYW
62514 G
G
Drain Current
− Continuous @ TA = 25°C
− Continuous @ TA = 100°C
− Pulsed (tp ≤ 10 ms)
Current
Limit
Source
Symbol
Gate−to−Source Voltage
MPWR
ESD Protection
MOSFET MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Overvoltage
Protection
1
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Preferred devices are recommended choices for future use
and best overall value.
*Limited by the current limit circuit.
Publication Order Number:
NIF62514/D
NIF62514
MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
42
42
46
45
50
50
Vdc
−
−
0.5
2.0
2.0
10
−
−
50
550
100
1000
1.0
−
1.7
4.0
2.0
6.0
−
−
90
165
100
190
−
−
105
185
120
210
VSD
−
1.05
−
V
OFF CHARACTERISTICS
Drain−to−Source Clamped Breakdown Voltage
(VGS = 0 Vdc, ID = 250 mAdc)
(VGS = 0 Vdc, ID = 250 mAdc, TJ = 150°C)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 32 Vdc, VGS = 0 Vdc)
(VDS = 32 Vdc, VGS = 0 Vdc, TJ = 150°C)
IDSS
Gate Input Current
(VGS = 5.0 Vdc, VDS = 0 Vdc)
(VGS = −5.0 Vdc, VDS = 0 Vdc)
IGSS
mAdc
mAdc
ON CHARACTERISTICS
Gate Threshold Voltage
(VDS = VGS, ID = 150 mAdc)
Threshold Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−Resistance (Note 4)
(VGS = 10 Vdc, ID = 1.4 Adc, TJ @ 25°C)
(VGS = 10 Vdc, ID = 1.4 Adc, TJ @ 150°C)
RDS(on)
Static Drain−to−Source On−Resistance (Note 4)
(VGS = 5.0 Vdc, ID = 1.4 Adc, TJ @ 25°C)
(VGS = 5.0 Vdc, ID = 1.4 Adc, TJ @ 150°C)
RDS(on)
Source−Drain Forward On Voltage
(IS = 7 A, VGS = 0 V)
Vdc
mV/°C
mW
mW
SWITCHING CHARACTERISTICS
Turn−on Delay Time
10% Vin to 10% ID
RL = 4.7 W, Vin = 0 to 10 V, VDD = 12 V
td(on)
−
4.0
8.0
ms
Turn−on Rise Time
10% ID to 90% ID
RL = 4.7 W, Vin = 0 to 10 V, VDD = 12 V
trise
−
11
20
ms
Turn−off Delay Time
90% Vin to 90% ID
RL = 4.7 W, Vin = 10 to 0 V, VDD = 12 V
td(off)
−
32
50
ms
Turn−off Fall Time
90% ID to 10% ID
RL = 4.7 W, Vin = 10 to 0 V, VDD = 12 V
tfall
−
27
50
ms
Slew−Rate On
RL = 4.7 W,
Vin = 0 to 10 V, VDD = 12 V
−dVDS/dton
−
1.5
2.5
ms
Slew−Rate Off
RL = 4.7 W,
Vin = 10 to 0 V, VDD = 12 V
dVDS/dtoff
−
0.6
1.0
ms
SELF PROTECTION CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Current Limit
(VGS = 5.0 Vdc)
(VGS = 5.0 Vdc, TJ = 150°C)
ILIM
6.0
3.0
9.0
5.0
11
8.0
Adc
Current Limit
(VGS = 10 Vdc)
(VGS = 10 Vdc, TJ = 150°C)
ILIM
7.0
4.0
10.5
7.5
13
10
Adc
Temperature Limit (Turn−off)
VGS = 5.0 Vdc
TLIM(off)
150
175
200
°C
Temperature Limit (Circuit Reset)
VGS = 5.0 Vdc
TLIM(on)
135
160
185
°C
Temperature Limit (Turn−off)
VGS = 10 Vdc
TLIM(off)
150
155
185
°C
Temperature Limit (Circuit Reset)
VGS = 10 Vdc
TLIM(on)
130
140
170
°C
ESD ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Electro−Static Discharge Capability
Human Body Model (HBM)
ESD
4000
−
−
V
Electro−Static Discharge Capability
Machine Model (MM)
ESD
400
−
−
V
4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.
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2
NIF62514
TYPICAL ELECTRICAL CHARACTERISTICS
12
8
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
TJ = 150°C
VGS = 10 V
10
7V
6V
8
5V
4V
6
4
3V
2
7
VGS = 10 V
6
1
0
3
2
4
3V
2
1
0
6
4
3
6
5
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. Output Characteristics
Figure 2. Output Characteristics
12
VGS = 10 V
ID, DRAIN CURRENT (AMPS)
12
7V
6V
10
5V
8
4V
6
TJ = −40°C
4
2
3V
VDS = 5 V
TJ = −40°C
10
8
6
TJ = 25°C
4
TJ = 150°C
2
0
0
0
2
1
4
3
0
6
5
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
VGS = 10 V
ID = 1.4 A
200
175
150
Maximum
125
100
75
Typical
50
25
0
−50
−25
0
25
50
75
100
1
1.5
2
2.5
3
3.5
4
4.5
5
Figure 4. Transfer Characteristics
250
225
0.5
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 3. Output Characteristics
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
2
1
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
14
ID, DRAIN CURRENT (AMPS)
4V
3
0
5
4
6V
5V
TJ = 25°C
0
7V
5
125
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. Drain−to−Source Resistance versus
Junction Temperature
250
225
VGS = 5 V
ID = 1.4 A
200
175
Maximum
150
125
100
Typical
75
50
25
0
−50
−25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 6. Drain−to−Source Resistance versus
Junction Temperature
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3
2.50
4
GATE THRESHOLD VOLTAGE (V)
IDSS, DRAIN−TO−SOURCE LEAKAGE
CURRENT (mA)
NIF62514
VDS = 32 V
3
2
1
Typical
0
−50
−25
0
25
50
75
125
100
ID = 150 mA
2.25
2.00
VTH + 4 Sigma
VTH
1.75
1.50
VTH − 4 Sigma
1.25
1.00
0.75
0.50
0.25
0
−50 −30 −10
150
30
10
50
70
90
110 130 150
TJ, JUNCTION TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. Drain−to−Source Resistance versus
Junction Temperature
Figure 8. Gate Threshold Voltage versus
Temperature
12
DRAIN CURRENT (AMPS)
Current Limit
10
VGS = 10 V
Temperature Limit
8
6
VGS = 5 V
4
2
0
0
1
2
3
4
5
TIME (ms)
R(t), TRANSIENT THERMAL RESISTANCE (°C/W)
Figure 9. Short−circuit Response
100
Duty Cycle = 0.5
0.2
10
0.1
0.05
P(pk)
0.02
1
0.01
t1
t2
DUTY CYCLE, D = t1/t2
Single Pulse
0.1
0.00001
0.0001
0.001
0.01
t,TIME (S)
0.1
D CURVES APPLY
FOR POWER
PULSE TRAIN SHOWN
READ TIME AT T1
TJ(pk) − TA = P(pk) RqJA(t)
RqJC @ R(t) for t ≤ 0.02
s
1
10
Figure 10. Transient Thermal Resistance
(Non−normalized Junction−to−Ambient mounted on minimum pad area)
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4
NIF62514
ORDERING INFORMATION
Device
Package
Shipping†
NIF62514T1
SOT−223
NIF62514T1G
SOT−223
(Pb−Free)
1000 / Tape & Reel
NIF62514T3G
SOT−223
(Pb−Free)
4000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
NIF62514
PACKAGE DIMENSIONS
SOT−223 (TO−261)
CASE 318E−04
ISSUE L
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
D
b1
4
HE
1
2
3
E
b
e1
e
0.08 (0003)
C
q
A
A1
L1
DIM
A
A1
b
b1
c
D
E
e
e1
L1
HE
MILLIMETERS
NOM
MAX
1.63
1.75
0.06
0.10
0.75
0.89
3.06
3.20
0.29
0.35
6.50
6.70
3.50
3.70
2.30
2.40
0.94
1.05
1.75
2.00
7.00
7.30
10°
−
q
MIN
1.50
0.02
0.60
2.90
0.24
6.30
3.30
2.20
0.85
1.50
6.70
0°
STYLE 3:
PIN 1.
2.
3.
4.
GATE
DRAIN
SOURCE
DRAIN
MIN
0.060
0.001
0.024
0.115
0.009
0.249
0.130
0.087
0.033
0.060
0.264
0°
INCHES
NOM
0.064
0.002
0.030
0.121
0.012
0.256
0.138
0.091
0.037
0.069
0.276
−
MAX
0.068
0.004
0.035
0.126
0.014
0.263
0.145
0.094
0.041
0.078
0.287
10°
SOLDERING FOOTPRINT*
3.8
0.15
2.0
0.079
2.3
0.091
2.3
0.091
6.3
0.248
2.0
0.079
1.5
0.059
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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For additional information, please contact your
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NIF62514/D
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