Catalyst CAT5419YI-50 Dual digitally programmable potentiometers (dppâ ¢) with 64 taps and 2-wire interface Datasheet

CAT5419
Dual Digitally Programmable Potentiometers (DPP™)
with 64 Taps and 2-wire Interface
FEATURES
DESCRIPTION
„ Two linear-taper digital potentiometers
The CAT5419 is two Digitally Programmable
Potentiometers (DPP™) integrated with control logic
and 16 bytes of NVRAM memory.
„ 64 resistor taps per potentiometer
„ End to end resistance 2.5kΩ, 10kΩ, 50kΩ or
100kΩ
A separate 6-bit control register (WCR) independently
controls the wiper tap position for each DPP.
Associated with each wiper control register are four 6bit non-volatile memory data registers (DR) used for
storing up to four wiper settings. Writing to the wiper
control register or any of the non-volatile data registers is via a 2-wire serial bus (I2C-like). On power-up,
the contents of the first data register (DR0) for each of
the two potentiometers is automatically loaded into its
respective wiper control registers (WCR).
„ Potentiometer control and memory access via
2-wire Interface (I2C like)
„ Low wiper resistance, typically 80
„ Four non-volatile wiper settings for each
potentiometer
„ Recall of wiper settings at power up
„ 2.5 to 6.0 volt operation
„ Standby current less than 1µA
¯¯¯) pin protects against
The Write Protection (WP
inadvertent programming of the data register.
„ 1,000,000 nonvolatile WRITE cycles
„ 100 year nonvolatile memory data retention
„ 24-lead SOIC and 24-lead TSSOP
The CAT5419 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
„ Write protection for data register
PIN CONFIGURATION
For Ordering Information details, see page 15.
TSSOP (Y)
(top view)
SOIC (W)
(top view)
VCC
1
24
NC
SDA
1
24
¯¯¯
WP
RL0
2
23
NC
A1
2
23
A2
RH0
3
22
NC
RL1
3
22
RW0
RW0
4
21
NC
RH1
4
21
RH0
A2
5
20
A0
RW1
5
20
RL0
¯¯¯
WP
6
NC
GND
6
7
A3
NC
7
CAT 19
5419 18
VCC
SDA
CAT 19
5419 18
RH0
SCL
SDA
NC
A1
8
17
SCL
NC
8
17
NC
RL1
9
16
NC
NC
9
16
NC
RH1
10
15
NC
NC
10
15
NC
RW1
11
14
NC
SCL
11
14
A0
GND
12
13
NC
A3
12
13
NC
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
FUNCTIONAL DIAGRAM
2-WIRE BUS
INTERFACE
RH1
WIPER
CONTROL
REGISTERS
RW0
RW1
WP
A0
A1
A2
A3
CONTROL
LOGIC
NONVOLATILE
DATA
REGISTERS
RL0
1
RL1
Doc. No. MD-2115 Rev. H
CAT5419
PIN DESCRIPTIONS
SCL: Serial Clock
The CAT5419 serial clock input pin is used to
clock all data transfers into or out of the device.
SDA: Serial Data
The CAT5419 bidirectional serial data pin is used
to transfer data into and out of the device. The
SDA pin is an open drain output and can be wireOR'd with the other open drain or open collector
outputs.
A0, A1, A2, A3: Device Address Inputs
These inputs set the device address when
addressing multiple devices. A total of sixteen
devices can be addressed on a single bus. A
match in the slave address must be made with the
address input in order to initiate communication
with the CAT5419.
Pin
SOIC
Pin
TSSOP
Name
1
19
VCC
2
20
RL0
3
21
RH0
4
22
RW0
Function
Supply Voltage
Low Reference Terminal for
Potentiometer 0
High Reference Terminal for
Potentiometer 0
Wiper Terminal for
Potentiometer 0
5
23
A2
Device Address
6
24
¯¯¯
WP
Write Protection
7
1
SDA
Serial Data Input/Output
8
2
A1
Device Address
Low Reference Terminal for
Potentiometer 1
High Reference Terminal for
Potentiometer 1
9
3
RL1
RH, RL: Resistor End Points
The RH and RL pins are equivalent to the terminal
connections on a mechanical potentiometer.
10
4
RH1
11
5
RW1
Wiper Terminal for
Potentiometer 1
RW: Wiper
The RW pins are equivalent to the wiper terminal of
a mechanical potentiometer.
12
6
GND
Ground
13
7
NC
No Connect
14
8
NC
No Connect
15
9
NC
No Connect
16
10
NC
No Connect
17
11
SCL
Bus Serial Clock
18
12
A3
Device Address
19
13
NC
No Connect
20
14
A0
Device Address, LSB
21
15
NC
No Connect
22
16
NC
No Connect
23
17
NC
No Connect
24
18
NC
No Connect
¯¯¯
WP: Write Protect Input
The ¯¯¯
WP pin when tied low prevents non-volatile
writes to the data registers (change of wiper
control register is allowed) and when tied high or
left floating normal read/write operations are
allowed. See page 7, Write Protection for more
details.
DEVICE OPERATION
The CAT5419 is two resistor arrays integrated with 2wire serial interface logic, four 6-bit wiper control registers
and sixteen 6-bit, non-volatile memory data registers. Each resistor array contains 63 separate resistive elements
connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL). RH and RL are symmetrical and may be interchanged. The tap positions between and
at the ends of the series resistors are connected to the output wiper terminals (RW) by a CMOS transistor switch.
Only one tap point for each potentiometer is connected to its wiper terminal at a time and is determined by the
value of the wiper control register. Data can be read or written to the wiper control registers or the non-volatile
memory data registers via the 2-wire bus. Additional instructions allow data to be transferred between the wiper
control registers and each respective potentiometer's non-volatile data registers. Also, the device can be
instructed to operate in an "increment/decrement" mode.
Doc. No. MD-2115 Rev. H
2
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5419
ABSOLUTE MAXIMUM RATINGS(1)
Parameters
Temperature Under Bias
Storage Temperature Range
Voltage to any Pins with Respect to VSS (2) (3)
VCC with Respect to GND
Package Power Dissipation Capability (TA = 25°C)
Lead Soldering Temperature (10 secs)
Wiper Current
Ratings
-55 to +125
-65 to +150
-2.0 to VCC +2.0
-2.0 to +7.0
1.0
300
±12
Units
ºC
ºC
V
V
W
ºC
mA
RECOMMENDED OPERATING CONDITIONS
Parameters
VCC
Industrial Temperature
Ratings
+2.5 to 6.0
-40 to +85
Units
V
ºC
POTENTIOMETER CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
RPOT
Potentiometer Resistance (-00)
100
kΩ
RPOT
Potentiometer Resistance (-50)
50
kΩ
RPOT
Potentiometer Resistance (-10)
10
kΩ
RPOT
Potentiometer Resistance (-2.5)
2.5
kΩ
Potentiometer Resistance Tolerance
RPOT Matching
Power Rating
25°C, each pot
IW
Wiper Current
RW
Wiper Resistance
IW = ±3mA @ VCC = 3V
RW
Wiper Resistance
IW = ±3mA @ VCC = 5V
Voltage on any RH or RL Pin
VSS
(4)
VTERM
VN
Noise
= 0V
GND
Resolution
Absolute Linearity
TCRPOT
TCRATIO
CH/CL/CW
fc
(5)
RW(n)(actual)-R(n)(expected)
Relative Linearity (6)
RW(n+1)-[RW(n)+LSB](8)
Temperature Coefficient of RPOT
(4)
Ratiometric Temp. Coefficient
(4)
Potentiometer Capacitances
(4)
Frequency Response
80
±20
%
1
%
50
mW
±6
mA
300
Ω
150
Ω
VCC
V
TBD
nV/√Hz
1.6
%
(8)
±1
LSB (7)
±0.2
LSB (7)
±300
ppm/°C
20
(4)
RPOT = 50kΩ
ppm/°C
10/10/25
pF
0.4
MHz
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(3) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(4) This parameter is tested initially and after a design or process change that affects the parameter.
(5) Absolute linearity is utilitzed to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer.
(6) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(7) LSB = RTOT / 63 or (RH - RL) / 63, single pot
(8) n = 0, 1, 2, ..., 63
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. MD-2115 Rev. H
CAT5419
D.C. OPERATING CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
Test Conditions
ICC
Power Supply Current
ISB
Min
Max
Units
fSCL = 400kHz
1
mA
Standby Current (VCC = 5.0V)
VIN = GND or VCC; SDA Open
1
µA
ILI
Input Leakage Current
VIN = GND to VCC
10
µA
ILO
Output Leakage Current
VOUT = GND to VCC
10
µA
VIL
Input Low Voltage
-1
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 1.0
V
VOL1
Output Low Voltage (VCC = 3.0V)
0.4
V
IOL = 3 mA
PIN CAPACITANCE (1)
Applicable over recommended operating range from TA = 25˚C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
Symbol
Test Conditions
Min
Typ
Max
Units
Conditions
CI/O
Output Capacitance (SDA)
8
pF
VI/O = 0V
CIN
Input Capacitance (A0, A1, A2, A3, SCL, ¯¯¯
WP)
6
pF
VIN = 0V
Min
Typ
A.C. CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
fSCL
(1)
TI
tAA
tBUF
(1)
Parameter
Max
Units
Clock Frequency
400
kHz
Noise Suppression Time Constant at SCL, SDA Inputs
50
ns
SLC Low to SDA Data Out and ACK Out
0.9
µs
Time the bus must be free before a new transmission can start
1.2
µs
Start Condition Hold Time
0.6
µs
tLOW
Clock Low Period
1.2
µs
tHIGH
Clock High Period
0.6
µs
tSU:STA
Start Condition Setup Time (for a Repeated Start Condition)
0.6
µs
tHD:DAT
Data in Hold Time
0
ns
tSU:DAT
Data in Setup Time
100
ns
tHD:STA
(1)
SDA and SCL Rise Time
0.3
µs
(1)
SDA and SCL Fall Time
300
ns
tR
tF
tSU:STO
tDH
Stop Condition Setup Time
0.6
µs
Data Out Hold Time
50
ns
POWER UP TIMING (1)
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
Min
Typ
Max
Units
tPUR
Power-up to Read Operation
1
ms
tPUW
Power-up to Write Operation
1
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. MD-2115 Rev. H
4
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5419
WRITE CYCLES LIMITS
Symbol
Parameter
tWR
Write Cycle Time
Max
Units
5
ms
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
RELIABILITY CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
Reference Test Method
NEND
(1)
TDR(1)
VZAP(1)
ILTH(1)(2)
Min
Typ
Max
Units
Endurance
MIL-STD-883, Test Method 1033
1,000,000
Cycles/Byte
Data Retention
MIL-STD-883, Test Method 1008
100
Years
ESD Susceptibility
MIL-STD-883, Test Method 3015
2000
Volts
Latch-Up
JEDEC Standard 17
100
mA
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Figure 1. Bus Timing
tF
tHIGH
tLOW
tR
tLOW
SCL
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
tSU:STO
SDA IN
tAA
tBUF
tDH
SDA OUT
Figure 2. Write Cycle Timing
SCL
8TH BIT
BYTE n
SDA
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
STOP BIT
5
Doc. No. MD-2115 Rev. H
CAT5419
of the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are
fixed as 0101 for the CAT5419 (see Figure 5). The
next four significant bits (A3, A2, A1, A0) are the
device address bits and define which device the
Master is accessing. Up to sixteen devices may be
individually addressed by the system. Typically, +5V
and ground are hard-wired to these pins to establish
the device's address.
SERIAL BUS PROTOCOL
The following defines the features of the 2-wire bus
protocol:
(1) Data transfer may be initiated only when the bus
is not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock is high will
be interpreted as a START or STOP condition.
After the Master sends a START condition and the
slave address byte, the CAT5419 monitors the bus
and responds with an acknowledge (on the SDA line)
when its address matches the transmitted slave
address.
The device controlling the transfer is a master,
typically a processor or controller, and the device
being controlled is the slave. The master will always
initiate data transfers and provide the clock for both
transmit and receive operations. Therefore, the
CAT5419 will be considered a slave device in all
applications.
Acknowledge
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8
bits of data.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT5419 monitors the
SDA and SCL lines and will not respond until this
condition is met.
The CAT5419 responds with an acknowledge after
receiving a START condition and its slave address. If
the device has been selected along with a write
operation, it responds with an acknowledge after
receiving each 8-bit byte.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must
end with a STOP condition.
When the CAT5419 is in a READ mode it transmits 8
bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT5419 will continue to transmit
data. If no acknowledge is sent by the Master, the
device terminates data transmission and waits for a
STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACKNOWLEDGE
START
Doc. No. MD-2115 Rev. H
6
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5419
WRITE OPERATIONS
internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition
followed by the slave address. If the CAT5419 is still
busy with the write operation, no ACK will be returned.
If the CAT5419 has completed the write operation, an
ACK will be returned and the host can then proceed
with the next instruction operation.
In the Write mode, the Master device sends the
START condition and the slave address information to
the Slave device. After the Slave generates an
acknowledge, the Master sends the instruction byte
that defines the requested operation of CAT5419. The
instruction byte consist of a four-bit opcode followed
by two register selection bits and two pot selection
bits. After receiving another acknowledge from the
Slave, the Master device transmits the data to be
written into the selected register. The CAT5419
acknowledges once more and the Master generates
the STOP condition, at which time if a nonvolatile data
register is being selected, the device begins an
internal programming cycle to non-volatile memory.
While this internal cycle is in progress, the device will
not respond to any request from the Master device.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the non-volatile
data registers. If the ¯¯¯
WP pin is tied to LOW, the data
registers are protected and become read only.
Similarly, ¯¯¯
WP pin going LOW after Start will interrupt
non-volatile write to data registers, while ¯¯¯
WP pin going
LOW after internal write cycle has started will have no
effect on any write operation. The CAT5419 will
accept both slave addresses and instructions, but the
data registers are protected from programming by the
device’s failure to send an acknowledge after data is
received.
Acknowledge Polling
The disabling of the inputs can be used to take
advantage of the typical write cycle time. Once the
stop condition is issued to indicate the end of the
host's write operation, the CAT5419 initiates the
Figure 5. Slave Address Bits
CAT5419
0
1
0
1
A3
A2
A1
A0
* A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.
** A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.
Figure 6. Write Timing
BUS ACTIVITY :
MASTER
SDA LINE
S
T
A
R
T
INSTRUCTION
BYTE
SLAVE/DPP
ADDRESS
Fixed
Variable
op code
DR1 WCR DATA
S
P
A
C
K
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Data Register Pot/WCR
Address
Address
S
T
O
P
A
C
K
7
A
C
K
Doc. No. MD-2115 Rev. H
CAT5419
Instruction Byte
The next byte sent to the CAT5419 contains the
instruction and register pointer information. The four
most significant bits used provide the instruction
opcode I [3:0]. The R1 and R0 bits point to one of the
four data registers of each associated potentiometer.
The least two significant bits point to one of two Wiper
Control Registers. The format is shown in Table 2.
INSTRUCTIONS AND REGISTER
DESCRIPTION
INSTRUCTIONS
Slave Address Byte
The first byte sent to the CAT5419 from the master/
processor is called the Slave/DPP Address Byte. The
most significant four bits of the slave address are a
device type identifier. These bits for the CAT5419 are
fixed at 0101[B] (refer to Table 1).
Data Register Selection
Data Register Selected
R1
R0
DR0
0
0
DR1
0
1
DR2
1
0
DR3
1
1
The next four bits, A3 - A0, are the internal slave
address and must match the physical device address
which is defined by the state of the A3 - A0 input pins
for the CAT5419 to successfully continue the
command sequence. Only the device which slave
address matches the incoming device address sent by
the master executes the instruction. The A3 - A0
inputs can be actively driven by CMOS input signals
or tied to VCC or VSS.
Table 1. Identification Byte Format
Device Type
Identifier
ID3
0
ID2
1
ID1
0
Slave Address
ID0
1
A3
A2
A1
(MSB)
A0
(LSB)
Table 2. Instruction Byte Format
Instruction
Opcode
I3
(MSB)
Doc. No. MD-2115 Rev. H
I2
Data Register
Selection
I1
I0
R1
8
R0
WCR/Pot Selection
0
P0
(LSB)
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5419
four Data Registers and the associated Wiper Control
Register. Any data changes in one of the Data
Registers is a non-volatile operation and will take a
maximum of 5ms.
WIPER CONTROL AND DATA REGISTERS
Wiper Control Register (WCR)
The CAT5419 contains two 6-bit Wiper Control
Registers, one for each potentiometer. The Wiper
Control Register output is decoded to select one of 64
switches along its resistor array. The contents of the
WCR can be altered in four ways: it may be written by
the host via Write Wiper Control Register instruction; it
may be written by transferring the contents of one of
four associated Data Registers via the XFR Data
Register instruction, it can be modified one step at a
time by the Increment/decrement instruction (see
Instruction section for more details). Finally, it is
loaded with the content of its data register zero (DR0)
upon power-up.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as standard memory locations for system
parameters or user preference data.
INSTRUCTIONS
Four of the nine instructions are three bytes in length.
These instructions are:
— Read Wiper Control Register – read the current
wiper position of the selected potentiometer in
the WCR
The Wiper Control Register is a volatile register that
loses its contents when the CAT5419 is powereddown. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
— Write Wiper Control Register – change current
wiper position in the WCR of the selected
potentiometer
— Read Data Register – read the contents of the
selected Data Register
Data Registers (DR)
Each potentiometer has four 6-bit non-volatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
— Write Data Register – write a new value to the
selected Data Register.
Table 3. Instruction Set
Note: 1/0 = data is one or zero
Instruction Set
Instruction
I3
I2
I1
I0
R1
R0
0
WCR0/ P0
Operation
Read Wiper Control
Register
1
0
0
1
0
0
0
1/0
Read the contents of the Wiper Control
Register pointed to by P0
Write Wiper Control
Register
1
0
1
0
0
0
0
1/0
Write new value to the Wiper Control
Register pointed to by P0
Read Data Register
1
0
1
1
1/0
1/0
0
1/0
Read the contents of the Data Register
pointed to by P0 and R1-R0
Write Data Register
1
1
0
0
1/0
1/0
0
1/0
Write new value to the Data Register
pointed to by P0 and R1-R0
XFR Data Register to
Wiper Control Register
1
1
0
1
1/0
1/0
0
1/0
Transfer the contents of the Data
Register pointed to by P0 and R1-R0 to
its associated Wiper Control Register
XFR Wiper Control
Register to Data
Register
1
1
1
0
1/0
1/0
0
1/0
Transfer the contents of the Wiper
Control Register pointed to by P0 to the
Data Register pointed to by R1-R0
Gang XFR Data
Registers to Wiper
Control Registers
0
0
0
1
1/0
1/0
0
0
Transfer the contents of the Data
Registers pointed to by R1-R0 of both
pots to their respective Wiper Control
Registers
Gang XFR Wiper
Control Registers to
Data Register
1
0
0
0
1/0
1/0
0
0
Transfer the contents of both Wiper
Control Registers to their respective data
Registers pointed to by R1-R0 of both
four pots
Increment/Decrement
Wiper Control Register
0
0
1
0
0
0
0
1/0
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
Enable Increment/decrement of the
Control Latch pointed to by P0
Doc. No. MD-2115 Rev. H
CAT5419
The basic sequence of the three byte instructions is
illustrated in Figure 8. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. The WCR controls the position of the wiper.
The response of the wiper to this action will be
delayed by tWRL. A transfer from the WCR (current
wiper position), to a Data Register is a write to nonvolatile memory and takes a maximum of tWR to
complete. The transfer can occur between one of the
potentiometers and one of its associated registers; or
the transfer can occur between all potentiometers and
one associated register.
— Global XFR Data Register to Wiper Control
Register
This transfers the contents of all specified Data
Registers to the associated Wiper Control Registers.
— Global XFR Wiper Counter Register to Data
Register
This transfers the contents of all Wiper Control
Registers to the specified associated Data
Registers.
INCREMENT/DECREMENT COMMAND
The final command is Increment/Decrement (Figure 5
and 9). The Increment/Decrement command is
different from the other commands. Once the
command is issued and the CAT5419 has responded
with an acknowledge, the master can clock the
selected wiper up and/or down in one segment steps;
thereby providing a fine tuning capability to the host.
For each SCL clock pulse (tHIGH) while SDA is HIGH,
the selected wiper will move one resistor segment
towards the RH terminal. Similarly, for each SCL clock
pulse while SDA is LOW, the selected wiper will move
one resistor segment towards the RL terminal.
Four instructions require a two-byte sequence to
complete, as illustrated in Figure 7. These instructions
transfer data between the host/processor and the
CAT5419; either between the host and one of the data
registers or directly between the host and the Wiper
Control Register. These instructions are:
— XFR Data Register to Wiper Control Register
This transfers the contents of one specified Data
Register to the associated Wiper Control Register.
— XFR Wiper Control Register to Data Register
This transfers the contents of the specified Wiper
Control Register to the specified associated Data
Register.
See Instructions format for more detail.
Figure 7. Two-Byte Instruction Sequence
SDA
0
1
0
1
S ID3 ID2 ID1 ID0 A3
T
A
R
Device ID
T
A2 A1 A0
A I3
C
K
Internal
Address
I2
I1
I0
Instruction
Opcode
0
R1 R0
Register
Address
S
T
O
P
P0
A
C
K
Pot/WCR
Address
Figure 8. Three-Byte Instruction Sequence
SDA
0
1
0
1
S ID3 ID2 ID1 ID0 A3
T
A
Device ID
R
T
A2
A0 A I3
C
K
Internal
Address
I2
A1
I1 I0
Instruction
Opcode
P0 A
C
K
Data
Pot/WCR
Register Address
Address
R1 R0
0
D7 D6 D5 D4 D3 D2 D1 D0
WCR[7:0]
or
Data Register D[7:0]
A
C
K
S
T
O
P
Figure 9. Increment/Decrement Instruction Sequence
0
SDA
S
T
A
R
T
1
0
1
ID3 ID2 ID1 ID0
Doc. No. MD-2115 Rev. H
Device ID
A3
A2 A1 A0
Internal
Address
A
C
K
I3
I2
I1
Instruction
Opcode
10
I0
R1 R0
0
P0
A
C
Pot/WCR K
Data
Register Address
Address
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
S
T
O
P
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5419
Figure 10. Increment/Decrement Timing Limits
INC/DEC
Command
Issued
tWRID
SCL
SDA
Voltage Out
RW
INSTRUCTION FORMAT
Read Wiper Control Register (WCR)
S
T
A
R
T
DEVICE ADDRESSES
0
1
0
1
A3
A2
A1
A0
A
C
K
INSTRUCTION
1
0
0
1
0
0
0
P0
A
C
K
DATA
7
0
6
0
5
4
3
2
1
0
A
C
K
S
T
O
P
A
C
K
S
T
O
P
A
C
K
S
T
O
P
A
C
K
S
T
O
P
Write Wiper Control Register (WCR)
S
T
A
R
T
DEVICE ADDRESSES
0
1
0
1
A3
A2
A1
A0
A
C
K
INSTRUCTION
1
0
1
0
0
0
0
P0
A
C
K
DATA
7
0
6
0
5
4
3
2
1
0
Read Data Register (DR)
S
T
A
R
T
DEVICE ADDRESSES
0
1
0
1
A3
A2
A1
A0
A
C
K
INSTRUCTION
1
0
1
1
R1
R0
0
P0
A
C
K
DATA
7
0
6
0
5
4
3
2
1
0
Write Data Register (DR)
S
T
A
R
T
DEVICE ADDRESSES
0
1
0
1
A3
A2
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
A1
A0
A
C
K
INSTRUCTION
1
1
0
0
R1
11
R0
0
P0
A
C
K
DATA
7
0
6
0
5
4
3
2
1
0
Doc. No. MD-2115 Rev. H
CAT5419
INSTRUCTION FORMAT (continued)
Global Transfer Data Register (DR) to Wiper Control Register (WCR)
S
T
A
R
T
DEVICE ADDRESSES
0
1
0
1
A3
A2
A1
A0
A
C
K
INSTRUCTION
0
0
0
1
R1
R0
0
0
A
C
K
S
T
O
P
A
C
K
S
T
O
P
A
C
K
S
T
O
P
A
C
K
S
T
O
P
Global Transfer Wiper Control Register (WCR) to Data Register (DR)
S
T
A
R
T
DEVICE ADDRESSES
0
1
0
1
A3
A2
A1
A0
A
C
K
INSTRUCTION
1
0
0
0
R1
R0
0
0
Transfer Wiper Control Register (WCR) to Data Register (DR)
S
T
A
R
T
DEVICE ADDRESSES
0
1
0
1
A3
A2
A1
A0
A
C
K
INSTRUCTION
1
1
1
0
R1
R0
0
P0
Transfer Data Register (DR) to Wiper Control Register (WCR)
S
T
A
R
T
DEVICE ADDRESSES
0
1
0
1
A3
A2
A1
A0
A
C
K
INSTRUCTION
1
1
0
1
R1
R0
0
P0
Increment (I)/Decrement (D) Wiper Control Register (WCR)
S
T
A
R
T
DEVICE ADDRESSES
0
1
0
1
A3
A2
A1
A0
A
C
K
INSTRUCTION
0
0
1
0
0
0
0
P0
A
C
K
DATA
I/D
I/D
...
I/D
I/D
A
C
K
S
T
O
P
Note:
(1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued.
Doc. No. MD-2115 Rev. H
12
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5419
PACKAGE OUTLINES
SOIC 24-Lead 300mils (W)
SYMBOL
E1
E
MIN
e
PIN#1 IDENTIFICATION
MAX
A
2.35
2.65
A1
0.10
0.30
A2
2.05
2.55
b
0.31
0.51
c
0.20
0.33
D
15.20
15.40
E
10.11
10.51
E1
7.34
e
b
NOM
7.60
1.27 BSC
h
0.25
0.75
L
0.40
1.27
θ
0°
8°
θ1
5°
15°
TOP VIEW
h
D
A2
A
A1
SIDE VIEW
h
θ1
θ
θ1
L
c
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1)
All dimensions in millimeters. Angles in degrees.
(2)
Complies with JEDEC MS-013.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
13
Doc. No. MD-2115 Rev. H
CAT5419
TSSOP 24-Lead 4.4mm (Y)
b
SYMBOL
MIN
NOM
A
A1
E1
E
MAX
1.20
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
D
7.70
7.80
7.90
E
6.25
6.40
6.55
E1
4.30
4.40
4.50
e
0.20
0.65 BSC
L
1.00 REF
L1
0.50
θ1
0°
0.60
0.70
8°
e
TOP VIEW
D
c
A2
A
θ1
L1
A1
L
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1)
All dimensions in millimeters. Angles in degrees.
(2)
Complies with JEDEC MO-153.
Doc. No. MD-2115 Rev. H
14
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5419
EXAMPLE OF ORDERING INFORMATION
Prefix
Device # Suffix
CAT
5419
Company ID
W
Package
W: SOIC
Y: TSSOP
I
Temperature Range
I = Industrial (-40ºC to 85ºC)
-00
- T1
Resistance
25: 2.5kΩ
10: 10kΩ
50: 50kΩ
00: 100kΩ
Tape & Reel
T: Tape & Reel
1: 1000/Reel - SOIC
2: 2000/Reel - TSSOP
Product Number
5419
Notes:
(1)
All packages are RoHS-compliant (Lead-free, Halogen-free).
(2)
The device used in the above example is a CAT5419WI-00-T1 (SOIC, Industrial Temperature, 100kΩ, Tape & Reel).
(3)
The lead finish is Matte-Tin.
Ordering Part Number
CAT5419WI-25
CAT5419WI-10
CAT5419WI-50
CAT5419WI-00
CAT5419YI-25
CAT5419YI-10
CAT5419YI-50
CAT5419YI-00
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
15
Doc. No. MD-2115 Rev. H
REVISION HISTORY
Date
Rev.
10/08/2003
E
04/01/2004
F
04/29/2007
10/10/2007
G
H
Reason
Update Features
Update Description
Eliminate data sheet designation
Update Features
Update Description
Update Pin Description
Update Absolute Maximum Ratings
Update Recommended Operating Conditions
Update Potentiometer Characteristics
Update Write Protection
Update Instructions
Update Ordering Information
Updated Example of Ordering Information
Updated Package Outline
Updated Example of Ordering Information
Added MD- to document number
Copyrights, Trademarks and Patents
© Catalyst Semiconductor, Inc.
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
Adaptive Analog™, Beyond Memory™, DPP™, EZDim™, LDD™, MiniPot™, Quad-Mode™ and Quantum Charge Programmable™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
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OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal
injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled
"Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical
semiconductor applications and may not be complete.
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Corporate Headquarters
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Santa Clara, CA 95054
Phone: 408.542.1000
Fax:
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Document No: MD-2115
Revision:
H
Issue date:
10/10/07
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