TI ADS5545IRGZ 14-bits, 170 msps adc with lvds/cmos output Datasheet

ADS5545
www.ti.com
SLWS180 – SEPTEMBER 2005
14-BITS, 170 MSPS ADC WITH LVDS/CMOS OUTPUTS
FEATURES
APPLICATIONS
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Wireless Communication
Software Defined Radio
Power Amplifier Linearization
802.16d/e
Test and Measurement Instrumentation
High Definition Video
Medical Imaging
Radar Systems
DESCRIPTION
The ADS5545 is a high performance 14-bit 170-MSPS ADC. Using an internal sample and hold and low jitter
clock buffer this ADC supports high SNR and high SFDR at high IF. With programmable options for parallel
CMOS and LVDS outputs, this device is available in a compact 48-pin QFN package. The device provides
internal references or can optionally be driven with an external reference. The device is specified over a –40°C to
85°C operating range.
CLKP
PLL
CLKM
14-Bit ADC
DIGITAL
ENCODER
REFERENCE
CONTROL I/F
IREF
SCLK
SEN
SDATA
RESET
OE
INP
CLKOUT
SH
D13−D0
INM
OVR
VCMOUT/
REFIN
IN CMOS MODE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2005, Texas Instruments Incorporated
PRODUCT PREVIEW
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Maximum Sample Rate: 170 MSPS
14-Bit Resolution
No Missing Codes
Power Dissipation
– Core Power: 1 W
– Total Power: 1.22 W
Internal Sample and Hold
73.5-dBFS SNR at 70-MHz IF
85-dBc SFDR at 70-MHz IF
Parallel CMOS and LVDS Output Options
Internal Reference, External Reference
Support
3.3-V Analog and Digital Supply
48-Pin QFN Package (7 mm × 7 mm)
ADS5545
www.ti.com
SLWS180 – SEPTEMBER 2005
PACKAG/ORDERING INFORMATION (1)
PRODUCT
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ADS5545
48-QFN
RGZ
–40°C to 85°C
ADS5545IRGZ
(1)
ORDERING
NUMBER
TRANSPORT
MEDIA,
QUANTITY
θJA = TBD, θJC = TBD
ABSOLUTE MAXIMUM RATINGS (1)
VALUE
UNIT
Supply voltage range
–0.3 V to 3.9
V
DRVDD Supply voltage range
–0.3 V to 3.9
V
Voltage between AGND and DRGND
–0.3 to 0.3
V
Voltage between AVDD to DRVDD
–0.3 to 3.3
V
–0.3 to 2
V
AVDD
CM
Voltage applied to external pin
PRODUCT PREVIEW
Voltage applied to analog input pins
–0.3 V to minimum (3.6, AVDD + 0.3 V )
V
TA
Operating free-air temperature range
–40 to 85
°C
TJ
Operating junction temperature range
125
°C
Tstg
Storage temperature range
–65 to 150
°C
220
°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
SUPPLIES AND REFERENCES
AVDD
Analog supply voltage
3
3.3
3.6
V
DRVDD
Digital supply voltage
3
3.3
3.6
V
170
MSPS
CLOCK INPUT
Input clock sample rate
1
Input clock amplitude, differential
Vpp
Input clock duty cycle
50%
Operating free-air temperature
–40
85
°C
ELECTRICAL CHARACTERISTICS
Typical values at 25°C, min, max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = DRVDD
= 3.3 V, sampling rate = 170 MSPS, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, LVDS
data output (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC ACCURACY
Resolution
14
No missing codes
DNL
Differential non-linearity
INL
Integral non-linearity
Offset error
Offset temperature coefficient
Gain error
Gain temperature coefficient
2
bits
Assured
–0.9
0.5
±3
TBD
LSB
LSB
±10
mV
TBD
ppm/°C
±1
%FS
TBD
∆/°C
ADS5545
www.ti.com
SLWS180 – SEPTEMBER 2005
ELECTRICAL CHARACTERISTICS (continued)
Typical values at 25°C, min, max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = DRVDD
= 3.3 V, sampling rate = 170 MSPS, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, LVDS
data output (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
ICC
Total supply current
FIN = TBD
369
mA
IAVDD
Analog supply current
FIN = TBD
315
mA
54
mA
70
mA
IDRVDD
Digital supply current
LVDS mode, FIN = TBD, CL = 5 pF
CMOS mode, FIN = TBD, CL = 5 pF
Total power dissipation
LVDS mode, FIN = TBD
1.22
W
Power down dissipation
Clock running
TBD
mW
REFERENCE VOLTAGES
VREFB
Reference bottom
0.5
V
VREFT
Reference top
2.5
V
VCM
Common mode voltage (internal)
1.5
V
VCM output current
±4
mA
7
pF
Differential input capacitance
VCM ± 0.1
Analog input common mode range
Differential input voltage range
Analog input bandwidth
–3 dB, source impedance 50 Ω
PRODUCT PREVIEW
ANALOG INPUT
V
2
Vpp
400
MHz
DYNAMIC AC CHARACTERISTICS
SFDR
SNR
Spurious free dynamic range
Signal-to-noise ratio
FIN = 10 MHz
90
FIN = 70 MHz
85
FIN = 150 MHz
84
FIN = 10 MHz
74
FIN = 70 MHz
73.5
FIN = 150 MHz
dBc
dBFS
72
3
ADS5545
www.ti.com
SLWS180 – SEPTEMBER 2005
DIGITAL CHARACTERISTICS
The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1 AVDD = DRVDD = 3.3 V, IO = 3.5 mA, RL = 100 Ω. (1)
All LVDS and CMOS specifications are characterized, but not tested at production.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS
High-level input voltage
2.4
V
Low-level input voltage
0.8
V
High-level input current
10
µA
Low-level input current
10
µA
4
pF
High-level output voltage
3.3
V
Low-level output voltage
0
V
4
pF
High-level output voltage
1375
mV
Low-level output voltage
1025
mV
Input capacitance
DIGITAL OUTPUTS – CMOS MODE
Output capacitance
Output capacitance inside the device, from either
output to ground
DIGITAL OUTPUTS – LVDS MODE
PRODUCT PREVIEW
Output differential voltage, |VOD|
350
mV
1200
mV
4
pF
Change in |VOD|, |∆VOD|
25
mV
Change in |VOS|, |∆VOS|
25
mV
VOS Output offset voltage (1)
Common-mode voltage of OUTP and OUTM
Output capacitance
Output capacitance inside the device, from either
output to ground
(1)
IO refers to the LVDS buffer current setting, RL is the differential load resistance between the LVDS output pair.
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
FS = 170 MSPS
FIN = 10.1 MHz
SFDR = 91.5 dBc
SNR = 74.09
dBFS
0
10
20
30
40
50
60
70
Figure 1. ADS5545 FFT Plot at 170 MSPS and 10-MHz Input
4
80
ADS5545
www.ti.com
SLWS180 – SEPTEMBER 2005
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
FS = 170 MSPS
FIN = 70.1 MHz
SFDR = 87.8 dBc
SNR = 73.5 dBFS
10
20
30
40
50
60
70
80
Figure 2. ADS5545 FFT Plot at 170 MSPS and 70-MHz Input
PRODUCT PREVIEW
0
5
PACKAGE OPTION ADDENDUM
www.ti.com
21-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
ADS5545IRGZ
PREVIEW
QFN
RGZ
Pins Package Eco Plan (2)
Qty
48
250
TBD
Lead/Ball Finish
Call TI
MSL Peak Temp (3)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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