ALSC AS6UA51216-TC 1.65v to 3.6v 512kã 16 intelliwatt low power cmos sram with one chip enable Datasheet

Advance Information
June 2000
AS6UA51216
1.65V to 3.6V 512K×16 Intelliwatt™ low power CMOS SRAM with one chip enable
• Low power consumption: STANDBY
- 72 µW max at 3.6V
- 41 µW max at 2.7V
- 28 µW max at 2.3V
• 1.2V data retention
• Equal access and cycle times
• Easy memory expansion with CS, OE inputs
• Smallest footprint packages
- 48-ball FBGA
- 400-mil 44-pin TSOP II
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Features
•
•
•
•
•
•
•
•
AS6UA51216
Intelliwatt™ active power circuitry
Industrial and commercial temperature ranges available
Organization: 524,288 words × 16 bits
2.7V to 3.6V at 55 ns
2.3V to 2.7V at 70 ns
1.65V to 2.3V at 100 ns
Low power consumption: ACTIVE
- 144 mW at 3.6V and 55 ns
- 68 mW at 2.7V and 70 ns
- 28 mW at 2.3 V and 100 ns
Logic block diagram
44-pin 400-mil TSOP II
A4
1
A5
44
A3
2
43
A6
A2
3
42
A7
A1
4
41
OE
5
A0
UB
40
LB
6
39
CS
I/O16
I/O1
7
38
I/O15
I/O2
8
37
I/O14
I/O3
9
36
I/O13
I/O4
10
35
VCC
VSS
11
34
VSS
VCC
12
33
I/O5
13
32
I/O12
I/O6
I/O11
14
31
I/O7
I/O10
15
30
I/O8
I/O9
16
29
WE
A8
17
28
A18
18
A9
27
A17
A10
19
26
A16
20
25
A11
A15
21
A12
24
A14
22
A13
23
VDD
Row Decoder
A0
A1
A2
A3
A4
A6
A7
A8
A12
A13
I/O1–I/O8
I/O9–I/O16
Pin arrangement (top view)
512K × 16
Array
(8,388,608)
I/O
buffer
Control circuit
VSS
Column decoder
A5
A9
A10
A11
A14
A15
A16
A17
A18
WE
UB
OE
LB
CS
Note: A “MODE” pad is to be placed between pins 33 and 34 and 11 and 12,
shorted. The bonding of this pad to VCC or VSS configures the device. There should
only be 44+2+2 pads on the chip. Two extra VCC to separate out Array from
Peripheral and Two-Mode Pads.
48-CSP Ball-Grid-Array Package
A
B
C
D
E
F
G
H
1
LB
I/O9
I/O10
VSS
VCC
I/O15
I/O16
A18
2
3
OE
A0
A3
UB
I/O11 A5
I/O12 A17
I/O13 VSS
I/O14 A14
NC
A12
A8
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CS
I/O2
I/O4
I/O5
I/O6
WE
A11
6
NC
I/O1
I/O3
VCC
VSS
I/O7
I/O8
NC
Selection guide
VCC Range
Power Dissipation
Typ2
(V)
Max
(V)
Speed
(ns)
Operating (ICC1)
Standby (ISB2)
Product
Min
(V)
Max (mA)
Max (µA)
AS6UA51216
2.7
3.0
3.6
55
2
20
AS6UA51216
2.3
2.5
2.7
70
1
15
AS6UA51216
1.65
2.0
2.3
100
1
12
6/27/00
ALLIANCE SEMICONDUCTOR
1
Copyright ©2000 Alliance Semiconductor. All rights reserved.
AS6UA51216
Functional description
The AS6UA51216 is a low-power CMOS 8,388,608-bit Static Random Access Memory (SRAM) device organized as 524,288 words × 16
bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 55/70/100 ns are ideal for low-power applications. Active high and low chip enables
(CS) permit easy memory expansion with multiple-bank memory systems.
When CS is high, or UB and LB are high, the device enters standby mode: the AS6UA51216 is guaranteed not to exceed 72 µW power
consumption at 3.6V and 55ns; 41 µW at 2.7V and 70 ns; or 28 µW at 2.3V and 100 ns. The device also returns data when VCC is reduced
to 1.5V for even lower power consumption.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CS) low, and UB and/or LB low. Data on the input pins I/O1–
O16 is written on the rising edge of WE (write cycle 1) or CS (write cycle 2). To avoid bus contention, external devices should drive I/O
pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE), chip enable (CS), UB and LB low, with write enable (WE) high. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is
active, or (UB) and (LB), output drivers stay in high-impedance mode.
These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16.
All chip inputs and outputs are CMOS-compatible, and operation is from either a single 1.65V to 3.6V supply. Device is available in the JEDEC
standard 400-mL, TSOP II, and 48-ball FBGA packages.
Absolute maximum ratings
Parameter
Device
Symbol
Min
Max
Unit
Voltage on V CC relative to VSS
VtIN
–0.5
VCC + 0.5
V
Voltage on any I/O pin relative to GND
VtI/O
–0.5
Power dissipation
PD
–
1.0
W
Storage temperature (plastic)
Tstg
–65
+150
°C
Temperature with VCC applied
Tbias
–55
+125
°C
DC output current (low)
IOUT
–
20
mA
V
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specificati on is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CS
WE
OE
LB
UB
H
X
X
X
X
L
X
X
H
H
L
H
H
X
X
L
H
H
L
L
L
L
H
L
L
X
Supply
Current
I/O1–I/O8 I/O9–I/O16
Mode
ISB
High Z
High Z
Standby (ISB)
ICC
High Z
High Z
Output disable (ICC)
DOUT
High Z
High Z
DOUT
L
DOUT
DOUT
L
H
DIN
High Z
H
L
High Z
DIN
L
L
DIN
DIN
ICC
ICC
Read (ICC)
Write (ICC)
Key: X = Don’t care, L = Low, H = High.
2
ALLIANCE SEMICONDUCTOR
6/27/00
AS6UA51216
Recommended operating condition (over the operating range)
Parameter
VOH
VOL
VIH
Description
Test Conditions
Output HIGH Voltage
Output LOW Voltage
Max
IOH = –2.1mA
VCC = 2.7V
2.4
IOH = –0.5mA
VCC = 2.3V
2.0
IOH = –0.1mA
VCC = 1.65V
1.5
IOL = 2.1mA
VCC = 2.7V
0.4
IOL = 0.5mA
VCC = 2.3V
0.4
IOL = 0.1mA
VCC = 1.65V
0.2
Input HIGH Voltage
Input LOW Voltage
VIL
Min
Unit
V
VCC = 2.7V
2.2
VCC + 0.5
VCC = 2.3V
2.0
VCC + 0.3
VCC = 1.65V
1.4
VCC + 0.3
VCC = 2.7V
–0.5
0.8
VCC = 2.3V
–0.3
0.6
VCC = 1.65V
–0.3
0.4
V
V
V
IIX
Input Load Current
GND < VIN < VCC
–1
+1
µA
IOZ
Output Load Current
GND < VO < VCC; Outputs High Z
–1
+1
µA
ICC
VCC Operating Supply
Current
ICC1 @
1 MHz
ICC2
ISB
ISB1
Average VCC Operating
Supply Current at 1 MHz
Average VCC Operating
Supply Current
CS Power Down Current;
TTL Inputs
CS = VIL, VIN = VIL
or VIH, IOUT = 0mA,
f=0
VCC = 3.6V
2
VCC = 2.7V
1
VCC = 2.3V
1
CS < 0.2V, VIN < 0.2V
or VIN > VCC – 0.2V,
f = 1 mS
VCC = 3.6V
4
VCC = 2.7V
2
VCC = 2.3V
2
VCC = 3.6V (55/70/100 mS)
CS ≠ VIL, VIN = VIL or
VCC = 2.7V (55/70/100 mS)
VIH, f = fMax
VCC = 2.3V(55/70/100 mS)
CS > VIH or UB = LB
> VIH, other inputs =
VIL or VIH, f = 0
CS > VCC – 0.2V or
CS Power Down Current; UB = LB > VCC – 0.2V
CMOS Inputs
other inputs = 0V –
VCC, f = fMax
Data Retention
ISBDR
CS > VCC – 0.1V,
UB = LB = VCC – 0.1V
f=0
mA
mA
40/30/20
30/25/15
mA
25/10/12
VCC = 3.6V
100
VCC = 2.7V
100
VCC = 2.3V
100
VCC = 3.6V
20
VCC = 2.7V
15
VCC = 2.3V
12
VCC = 1.2V
2
µA
µA
µA
Capacitance (f = 1 MHz, T a = Room temperature, VCC = NOMINAL)
Parameter
Symbol
Signals
Test conditions
Max
Unit
Input capacitance
CIN
A, CS, WE, OE, LB, UB
VIN = 0V
5
pF
I/O capacitance
CI/O
I/O
VIN = VOUT = 0V
7
pF
6/27/00
ALLIANCE SEMICONDUCTOR
3
AS6UA51216
Read cycle (over the operating range)
–55
Parameter
–70
–100
Symbol
Min
Max
Min
Max
Min
Max
Unit
Read cycle time
tRC
55
–
70
–
100
–
ns
Address access time
tAA
–
55
–
70
–
100
ns
3
Chip enable (CS) access time
tACS
–
55
–
70
–
100
ns
3
Output enable (OE) access
time
tOE
–
25
–
35
–
50
ns
Output hold from address
change
tOH
10
–
10
–
15
–
ns
5
CS
tCLZ
10
–
10
–
10
–
ns
4, 5
CS high to output in high Z
tCHZ
0
20
0
20
0
20
ns
4, 5
OE low to output in low Z
tOLZ
5
–
5
–
5
–
ns
4, 5
UB/LB access time
tBA
–
55
–
70
–
100
ns
UB/LB low to low Z
tBLZ
10
–
10
–
10
–
ns
4, 5
UB/LB high to high Z
tBHZ
0
20
0
20
0
20
ns
4, 5
OE high to output in high Z
tOHZ
0
20
0
20
0
20
ns
4, 5
Power up time
tPU
0
–
0
–
0
–
ns
4, 5
Power down time
tPD
–
55
–
70
–
100
ns
4, 5
o output in low Z
Notes
Shaded areas indicate preliminary information.
Key to switching waveforms
Rising input
Falling input
Undefined/don’t care
Read waveform 1 (address controlled)
tRC
Address
tOH
D OUT
tAA
tOH
Previous data valid
Data valid
Read waveform 2 (CS, OE, UB, LB controlled)
tRC
Address
tAA
OE
tOE
tOLZ
tOH
CS
tLZ
tOHZ
tHZ
tACS
LB, UB
tBLZ
DOUT
4
tBA
tBHZ
Data valid
ALLIANCE SEMICONDUCTOR
6/27/00
AS6UA51216
Write cycle (over the operating range)
–55
Parameter
–70
–100
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Write cycle time
tWC
55
–
70
–
100
–
ns
Chip enable to write end
tCW
40
–
60
–
80
–
ns
Address setup to write end
tAW
40
–
60
–
80
–
ns
Address setup time
tAS
0
–
0
–
0
–
ns
Write pulse width
tWP
35
–
55
–
70
–
ns
Address hold from end of write
tAH
0
–
0
–
0
–
ns
Data valid to write end
tDW
25
–
30
–
40
–
ns
Data hold time
tDH
0
–
0
–
0
–
ns
4, 5
Write enable to output in high Z
tWZ
0
20
0
20
0
20
ns
4, 5
Output active from write end
tOW
5
–
5
–
5
–
ns
4, 5
UB/LB low to end of write
tBW
35
–
55
–
70
–
ns
12
12
Shaded areas indicate preliminary information.
Write waveform 1 (WE controlled)
tWC
Address
tAH
tCW
CS
tBW
LB, UB
tAW
tAS
tWP
WE
tDW
D IN
Data valid
tWZ
DOUT
tDH
tOW
Data undefined
High Z
Write waveform 2 (CS controlled)
tWC
Address
tAS
tAH
tCW
CS
tAW
tBW
LB, UB
tWP
WE
tDW
DIN
DOUT
6/27/00
tCLZ
High Z
tWZ
Data undefined
ALLIANCE SEMICONDUCTOR
tDH
Data valid
tOW
High Z
5
AS6UA51216
Data retention characteristics (over the operating range)
Parameter
Symbol
Test conditions
Min
Max
Unit
VCC for data retention
VDR
1.2V
3.6
V
Data retention current
ICCDR
–
2
mA
Chip deselect to data retention time
tCDR
VCC = 1.2V
CS ≥ VCC – 0.1V or
UB = LB = > VCC – 0.1V
VIN ≥ VCC – 0.1V or
VIN ≤ 0.1V
0
–
ns
tRC
–
ns
Operation recovery time
tR
Data retention waveform
Data retention mode
VCC
VDR ≥ 1.2V
VCC
VCC
tCDR
tR
VDR
VIH
CS
VIH
AC test loads and waveforms
VCC
OUTPUT
Thevenin equivalent:
R1
R1
VCC
OUTPUT
30 pF
5 pF
R2
INCLUDING
JIG AND
SCOPE
(a)
V
ALL INPUT PULSES
R2
INCLUDING
JIG AND
SCOPE
RTH
OUTPUT
VCC Typ
GND
90%
10%
(b)
90%
< 5 ns
10%
(c)
Parameters
VCC = 3.0V
VCC = 2.5V
VCC = 2.0V
Unit
R1
1105
16670
15294
Ohms
R2
1550
15380
11300
Ohms
RTH
645
8000
6500
Ohms
VTH
1.75V
1.2V
0.85V
Volts
Notes
1
2
3
4
5
6
7
8
9
10
11
12
13
14
6
During V CC power-up, a pull-up resistor to VCC on CS is required to meet ISB specification.
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions.
tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500 mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is HIGH for read cycle.
CS and OE are LOW for read cycle.
Address valid prior to or coincident with CS transition LOW.
All read cycle timings are referenced from the last valid address to the first transitioning address.
CS or WE must be HIGH during address transitions. Either CS or WE asserting high terminates a write cycle.
All write cycle timings are referenced from the last valid address to the first transitioning address.
N/A.
1.2V data retention applies to commercial and industrial temperature range operations.
C = 30pF, except at high Z and low Z parameters, where C = 5pF.
ALLIANCE SEMICONDUCTOR
6/27/00
AS6UA51216
Typical DC and AC characteristics
Normalized supply current
vs. supply voltage
Normalized access time
vs. supply voltage
1.4
1.0
Normalized TAA
VIN = V CC typ
TA = 25° C
1.0
3.0
2.5
0.8
0.6
0.4
0.75
Normalized ISB2
1.2
Normalized ICC
Normalized standby current
vs. ambient temperature
TA = 25° C
0.5
1.5
1.0
0.5
0.0
0.25
0.2
VCC = VCC typ
VIN = VCC typ
2.0
-0.5
0.0
1.7
2.2
2.7
3.2
3.7
0.0
1.7
Supply voltage (V)
2.2
2.7
3.2
3.7
-55
Supply Voltage (V)
25
105
Ambient temperature (°C)
Normalized standby current
vs. supply voltage
Normalized ICC
vs. cycle time
1.4
1.0
Normalized ICC
Normalized ISB
1.5
ISB2
1.2
0.8
0.6
0.4
VCC = 3.6V
TA = 25° C
1.0
0.50
VIN = VCC typ
TA = 25 ° C
0.2
0.10
0.0
2.8
1.9
Supply voltage (V)
1
1
3.7
5
10
Supply voltage (V)
15
Package diagrams and dimensions
44-pin TSOP II
c
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
Min
(mm)
A
e He
44-pin TSOP II
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
A2
A
A1
b
l
0–5°
0.05
A2
0.95
1.05
b
0.25
0.45
20.85
21.05
e
10.06
10.26
He
11.56
11.96
l
6/27/00
ALLIANCE SEMICONDUCTOR
0.15 (typical)
d
E
E
1.2
A1
c
d
Max
(mm)
0.80 (typical)
0.40
0.60
7
AS6UA51216
48-ball FBGA
Top View
Bottom View
6
5
4
3
2
1
Ball #A1 Index
Ball #A1
A
B
SRAM Die
C
D
C1
C
E
F
A
G
H
Elastomer
A
B
B1
Detail View
Side View
A
Ε
Ε2
D
E2
Y
E
Die
Die
Ε1
8
0.3/Typ
Minimum
Typical
Maximum
A
–
0.75
–
B
6.90
7.00
7.10
B1
–
3.75
–
C
8.4
8.5
8.6
C1
–
5.25
–
D
0.30
0.35
0.40
5. Typ: typical.
E
–
–
1.20
6. Y is coplanarity: 0.08 (max).
E1
–
0.68
–
E2
0.22
0.25
0.27
Y
–
–
0.08
Notes
1. Bump counts: 48 (8 row × 6 column).
2. Pitch: (x,y) = 0.75 mm × 0.75 mm (typ).
3. Units: millimeters.
4. All tolerance are ± 0.050 unless otherwise specified.
ALLIANCE SEMICONDUCTOR
6/27/00
AS6UA51216
Ordering codes
Speed (ns)
55/70/100
Ordering Code
Package Type
AS6UA51216-TC
44-pin TSOP II
AS6UA51216-BC
48-ball fine pitch BGA
AS6UA51216-TI
44-pin TSOP II
AS6UA51216-BI
48-ball fine pitch BGA
Operating Range
Commercial
Industrial
Part numbering system
AS6UA
SRAM Intelliwatt™ prefix
6/27/00
51216
B, T
C, I
Device number
Package:
T: TSOP II
B: CSP BGA
Temperature range:
C: Commercial: 0° C to 70° C
I: Industrial: –40° C to 85° C
ALLIANCE SEMICONDUCTOR
9
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