STMicroelectronics ESDA18-1F2 Transil, transient voltage suppressor Datasheet

ESDA18-1F2
Transil™, transient voltage suppressor
Features
■
Stand-off voltage 16V
■
Unidirectional device
■
Low clamping factor VCL/VBR
■
Fast response time
■
Very thin package: 0.65 mm
Flip Chip
(4 bumps)
Complies with the following standards
■
IEC 61000-4-2 Level 4
– 15 kV (air discharge)
– 8 kV (contact discharge)
Figure 1.
Pin configuration (bump side)
Description
The ESDA18-1F2 is a single line Transil diode
designed specifically for the protection of
integrated circuits into portable equipment and
miniaturized electronics devices subject to ESD
and EOS transient overvoltages.
A
B
K
A
K
A
1
2
K
A
TM: Transil is a trademark of STMicroelectronics.
April 2008
Rev 2
1/8
www.st.com
8
Characteristics
1
ESDA18-1F2
Characteristics
Table 1.
Absolute ratings (limiting value, per diode)
Symbol
Parameter and test conditions
Value
Peak pulse power dissipation
10 / 1000 µs pulse
PPP
100
W
Tj initial = Tamb
Peak pulse power dissipation
8 / 20 µs pulse
700
IFSM
Non repetitive surge peak forward current
Tj
Maximum operating junction temperature
Tstg
tp=10 ms
Tj initial = Tamb
Storage temperature range
Table 2.
Parameter
VBR
Breakdown voltage
IRM
Leakage current
VRM
Stand-off voltage
VCL
Clamping voltage
Rd
Dynamic impedance
IPP
Peak pulse current
ESDA18-1F2
A
125
°C
- 65 to + 175
°C
I
IF
VF
VCL VBR
VRM
V
IRM
Slope: 1/Rd
IPP
Capacitance
VBR
Order
number
8
Electrical characteristics (Tamb = 25 °C)
Symbol
C
Unit
IRM
VRM
VCL
IPP (1)
IR
min.
max.
max.
VF (2)
αT
C
max.
max.
typ.
max.
IF = 850 mA
VR=0 V
V
V
mA
µA
V
V
A
V
10-4/°C
pF
16
18
1
0.5
10
20
1
1.3
8.5
230
1. 8 / 20 µs pulse waveform.
2. A DC current is not recommended for more than 5 sec. Even if Transil failure mode is short circuit the
bumps could exceed melting temperature and the component disassembled from the board.
2/8
ESDA18-1F2
Figure 2.
Characteristics
Relative variation of peak pulse
power versus initial junction
temperature
Figure 3.
PPP[Tj initial] / PPP[Tj initial=25°C)
Peak pulse power versus
exponential pulse duration
PPP(W)
1.1
10000
1.0
Tj initial=25°C
0.9
0.8
1000
0.7
0.6
0.5
0.4
100
0.3
0.2
0.1
Tj(°C)
tp(µs)
0.0
10
0
25
Figure 4.
50
75
100
125
150
Clamping voltage versus peak
pulse current (typical values,
exponential waveform)
1
10
Figure 5.
IPP(A)
100
1000
Forward voltage drop versus peak
forward current (typical values)
IFM(A)
100.0
1.E+01
8/20µs
Tj initial=25°C
1.E+00
Tj=125°C
10.0
Tj=25°C
1.E-01
1.0
1.E-02
VCL(V)
VFM(V)
0.1
1.E-03
10
12
Figure 6.
14
16
18
20
22
24
26
28
30
Junction capacitance versus
reverse voltage applied (typical
values)
0.0
Figure 7.
C(pF)
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Relative variation of leakage
current versus junction
temperature (typical values)
IR[Tj] / IR[Tj=25°C]
300
100
VR=10V
F=1MHz
VOSC=30mVRMS
Tj=25°C
250
200
150
10
100
50
VR(V)
Tj(°C)
0
1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
25
50
75
100
125
3/8
Application information
2
ESDA18-1F2
Application information
One major point is that the ESDA18-1F2 has to ensure the safety during reverse battery
operation. Indeed, during this operation the device must clamp the DC reverse voltage
below 1.3 V @ 0.85 A (max current). Thus reverse battery operation has been simulated by
inverting the polatrity of the Transil (please see figures 8 and 9)
Figure 8.
Reverse battery operation setup
Equivalent
mobile phone
impedance
PTC
I
Vmains
V
4.7 kΩ
1 nF
ESDA18-1F2
Figure 9.
Reverse battery operation results
A short calculation based on Reverse battery operation results figures clearly show that in
such real phone application the ESDA18-1F2 clamp the DC voltage below 1.3 V.
Typically the ESDA18-1F2 can clamp the DC voltage @ 0.9 V @ 0.76 A DC current:
2 × V max 2 × 1.4
V DC = ----------------------- ≈ ----------------- ≈ 0.9V
Π
3.14
2 × I max 2 × 1.2
I DC = --------------------- ≈ ----------------- ≈ 0.76A
Π
3.14
4/8
ESDA18-1F2
3
Ordering information scheme
Ordering information scheme
Figure 10. Ordering information scheme
ESDA
18 - 1
Fx
ESD Array
Breakdown Voltage
18 = 18 Volts max.
Number of line
1 = signle line
Package
F = Flip Chip
x = 2: Lead-free, pitch = 500 µm, bump = 315 µm
Packing information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at
www.st.com.
Figure 11. Flip Chip package dimensions
650 µm ± 65
500 µm ± 50
0.92 mm ± 30 µm
315 µm ± 50
500 µm ± 50
225 µm
0.92 mm ± 30 µm
225 µm
4
5/8
Packing information
ESDA18-1F2
Figure 12. Footprint recommendations
Figure 13. Marking
Dot, ST logo
xx = marking
z = manufacturing location
yww = datecode
(y = year
ww = week)
Copper pad Diameter:
250 µm recommended, 300µm max
Solder stencil opening: 330 µm
Solder mask opening recommendation:
340 µm min for 315 µm copper pad diameter
E
x x z
y ww
Figure 14. Flip Chip tape and reel specification
Dot identifying Pin A1 location
3.5 ± 0.1
1.0
STE
xxx
yww
1.0
STE
xxx
yww
Note:
STE
All dimensions in mm
xxx
yww
8 ± 0.3
0.73 ± 0.05
4 ± 0.1
User direction of unreeling
More packing information is available in the application notes:
AN1235: “Flip Chip: Package description and recommendations for use”
AN1751: "EMI Filters: Recommendations and measurements"
6/8
1.75 ± 0.1
Ø 1.5 ± 0.1
4 ± 0.1
ESDA18-1F2
5
Ordering information
Ordering information
Table 3.
6
Ordering Information
Order code
Marking
Package
Weight
Base qty
Delivery mode
ESDA18-1F2
EE
Flip Chip
1.25 mg
5000
Tape and reel 7”
Revision history
Table 4.
Document revision history
Date
Revision
Changes
09-May-2005
1
First issue.
18-Apr-2008
2
Updated ECOPACK statement. Updated Figure 11, Figure 13, and
Figure 14. Reformatted to current standards.
7/8
ESDA18-1F2
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