DATASHEET ISL9001A FN6433 Rev 3.00 December 10, 2015 LDO with Low ISUPPLY, High PSRR ISL9001A is a high performance Low Dropout linear regulator capable of sourcing 300mA current. It has a low standby current and high-PSRR and is stable with output capacitance of 1µF to 10µF with ESR of up to 200m. Features The ISL9001A has a very high PSRR of 90dB and output noise less than 30µVRMS. A reference bypass pin allows connection of a noise-filtering capacitor for low-noise and high-PSRR applications. When coupled with a no load quiescent current of 25µA (typical), and 0.1µA shutdown current, the ISL9001A is an ideal choice for portable wireless equipment. • Excellent load regulation: <0.1% voltage change across full range of load current • 300mA high performance LDO • Excellent transient response to large current steps • High PSRR: 90dB @ 1kHz • Wide input voltage capability: 2.3V to 6.5V • Extremely low quiescent current: 25µA • Low dropout voltage: typically 200mV @ 300mA The ISL9001A provides a PGOOD signal with delay time programmable through an external capacitor. • Low output noise: typically 30µVRMS @ 100µA (1.5V) Several different fixed voltage outputs are standard. Output voltage options for each LDO range from 1.5V to 3.3V. Other output voltage options may be available upon request. • Soft-start to limit input current surge during enable • Stable with 1µF to 10µF ceramic capacitors • Current limit and overheat protection • Delayed POR, programmable with external capacitor Pinout • ±1.8% accuracy over all operating conditions ISL9001A (8 LD DFN) TOP VIEW • Tiny 2mmx3mm 8 Ld DFN package • -40°C to +85°C operating temperature range VIN 1 8 VO EN 2 7 POR CBYP 3 6 NC Applications CPOR 4 5 GND • PDAs, cell phones and smart phones • Pb-free (RoHS compliant) • Portable instruments, MP3 players • Handheld devices, including medical handhelds FN6433 Rev 3.00 December 10, 2015 Page 1 of 12 ISL9001A Ordering Information PART NUMBER (Notes 1, 2) PART MARKING VO VOLTAGE (V) (Note 3) TEMP RANGE (°C) PACKAGE Tape and Reel (Pb-free) PKG. DWG. # ISL9001AIRBZ-T EBB 1.5 -40 to +85 8 Ld 2x3 DFN L8.2x3 ISL9001AIRCZ-T EBC 1.8 -40 to +85 8 Ld 2x3 DFN L8.2x3 ISL9001AIRFZ-T EBD 2.5 -40 to +85 8 Ld 2x3 DFN L8.2x3 ISL9001AIRJZ-T EBE 2.8 -40 to +85 8 Ld 2x3 DFN L8.2x3 ISL9001AIRKZ-T EBF 2.85 -40 to +85 8 Ld 2x3 DFN L8.2x3 ISL9001AIRLZ-T (No longer available or supported, recommended part: ISL9005AIRKZ-T) EBG 2.9 -40 to +85 8 Ld 2x3 DFN L8.2x3 ISL9001AIRNZ-T EBJ 3.3 -40 to +85 8 Ld 2x3 DFN L8.2x3 NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Please refer to TB347 for details on reel specifications 3. For other output voltages, contact Intersil Marketing. FN6433 Rev 3.00 December 10, 2015 Page 2 of 12 ISL9001A Absolute Maximum Ratings Thermal Information Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1V VO Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.6V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN + 0.3)V Thermal Resistance (Notes 4, 5) JA (°C/W) JC (°C/W) 8 Ld 2x3 DFN Package . . . . . . . . . . . . 69 10 Junction Temperature Range . . . . . . . . . . . . . . . . .-40°C to +125°C Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Ambient Temperature Range (TA) . . . . . . . . . . . . . . .-40°C to +85°C Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 6.5V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications PARAMETER Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -40°C to +85°C; VIN = (VO + 0.5V) to 5.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF. SYMBOL TEST CONDITIONS MIN (Note 7) TYP MAX (Note 7) UNITS 6.5 V DC CHARACTERISTICS Supply Voltage 2.3 VIN Ground Current Quiescent condition: IO = 0µA IDD LDO active 25 32 µA LDO disabled @ +25°C 0.1 1.0 µA Shutdown Current IDDS UVLO Threshold VUV+ 1.9 2.1 2.3 V VUV- 1.6 1.8 2.0 V Regulation Voltage Accuracy Maximum Output Current IMAX Internal Current Limit ILIM Dropout Voltage (Note 6) Thermal Shutdown Temperature Initial accuracy at VIN = VO + 0.5V, IO = 10mA, TJ = +25°C -0.7 +0.7 % VIN = VO + 0.5V to 5.5V, IO = 10µA to 300mA, TJ = +25°C -0.8 +0.8 % VIN = VO + 0.5V to 5.5V, IO = 10µA to 300mA, TJ = -40°C to +125°C -1.8 +1.8 % Continuous 300 350 mA 475 600 mA VDO1 IO = 300mA; VO 2.5V 300 500 mV VDO2 IO = 300mA; 2.5V VO 2.8V 250 400 mV VDO3 IO = 300mA; VO > 2.8V 200 325 mV TSD+ 145 °C TSD- 110 °C @ 1kHz 90 dB @ 10kHz 70 dB @ 100kHz 50 dB IO = 100µA, VO = 1.5V, TA = +25°C, CBYP = 0.1µF BW = 10Hz to 100kHz 30 µVRMS AC CHARACTERISTICS Ripple Rejection Output Noise Voltage FN6433 Rev 3.00 December 10, 2015 IO = 10mA, VIN = 2.8V (min), VO = 1.8V, CBYP = 0.1µF Page 3 of 12 ISL9001A Electrical Specifications PARAMETER Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -40°C to +85°C; VIN = (VO + 0.5V) to 5.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF. (Continued) TYP MAX (Note 7) UNITS Time from assertion of the ENx pin to when the output voltage reaches 95% of the VO (nom) 250 500 µs Slope of linear portion of LDO output voltage ramp during start-up 30 60 µs/V SYMBOL MIN (Note 7) TEST CONDITIONS DEVICE START-UP CHARACTERISTICS Device Enable Time tEN LDO Soft-Start Ramp Rate tSSR EN PIN CHARACTERISTICS Input Low Voltage VIL -0.3 0.5 V Input High Voltage VIH 1.4 VIN + 0.3 V 0.1 µA Input Leakage Current IIL, IIH Pin Capacitance CPIN Informative 5 pF POR PIN CHARACTERISTICS POR Thresholds VPOR+ As a percentage of nominal output voltage VPORPOR Delay tPLH CPOR = 0.01µF 91 94 97 % 87 90 93 % 100 200 300 ms tPHL POR Pin Output Low Voltage VOL POR Pin Internal Pull-up Resistance 25 @ IOL = 1.0mA RPOR 78 100 µs 0.2 V 180 k NOTES: 6. VOx = 0.98*VOx(NOM); Valid for VOx greater than 1.85V. 7. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested. EN tEN VPOR+ VPOR- VPOR+ VPOR- <tPHL VO tPLH tPHL POR FIGURE 1. TIMING PARAMETER DEFINITION FN6433 Rev 3.00 December 10, 2015 Page 4 of 12 ISL9001A Typical Performance Curves 0.8 0.10 VO = 3.3V ILOAD = 0mA 0.4 0.2 -40°C 0.0 +25°C -0.2 +85°C -0.4 VIN = 3.8V VO = 3.3V 0.08 OUTPUT VOLTAGE CHANGE (%) OUTPUT VOLTAGE, VO (%) 0.6 -0.6 0.06 0.04 -40°C 0.02 +25°C 0.00 -0.02 +85°C -0.04 -0.06 -0.08 -0.8 3.4 3.8 4.6 4.2 5.0 5.4 5.8 6.2 6.6 -0.10 50 0 200 250 300 350 400 LOAD CURRENT - IO (mA) FIGURE 2. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V OUTPUT) FIGURE 3. OUTPUT VOLTAGE CHANGE vs LOAD CURRENT 3.4 0.10 VIN = 3.8V VO = 3.3V ILOAD = 0mA 0.08 0.06 0.04 0.02 0.00 -0.02 -0.04 -0.06 VO = 3.3V IO = 0mA 3.3 OUTPUT VOLTAGE, VO (V) OUTPUT VOLTAGE CHANGE (%) 150 100 INPUT VOLTAGE (V) 3.2 IO = 150mA 3.1 IO = 300mA 3.0 2.9 -0.08 -0.10 -40 -25 5 -10 20 35 50 65 TEMPERATURE (°C) 80 95 2.8 110 125 3.6 4.1 4.6 5.1 5.6 6.1 6.5 INPUT VOLTAGE (V) FIGURE 4. OUTPUT VOLTAGE CHANGE vs TEMPERATURE FIGURE 5. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V OUTPUT) 350 2.9 VO = 2.8V IO = 0mA 300 DROPOUT VOLTAGE, VDO (mV) 2.8 OUTPUT VOLTAGE, VO (V) 3.1 2.7 IO = 150mA 2.6 IO = 300mA 2.5 2.4 2.3 2.6 250 VO = 2.8V 200 VO = 3.3V 150 100 50 0 3.1 3.6 4.1 4.6 5.1 5.6 6.1 6.5 INPUT VOLTAGE (V) FIGURE 6. OUTPUT VOLTAGE vs INPUT VOLTAGE (2.8V OUTPUT) FN6433 Rev 3.00 December 10, 2015 0 50 100 150 200 250 OUTPUT LOAD (mA) 300 350 FIGURE 7. DROPOUT VOLTAGE vs LOAD CURRENT Page 5 of 12 400 ISL9001A Typical Performance Curves (Continued) 350 40 VO = 3.3V 35 GROUND CURRENT (µA) DROPOUT VOLTAGE, VDO (mV) 300 250 +25°C +85°C 200 -40°C 150 100 +25°C 25 -40°C 20 VO = 3.3V 15 50 0 +125°C 30 0 50 100 150 200 250 OUTPUT LOAD (mA) 300 350 10 400 3.0 3.5 4.0 4.58 5.0 5.5 6.5 6.0 INPUT VOLTAGE (V) FIGURE 8. DROPOUT VOLTAGE vs LOAD CURRENT FIGURE 9. GROUND CURRENT vs INPUT VOLTAGE 40 200 180 35 GROUND CURRENT (µA) GROUND CURRENT (µA) 160 +85°C 140 120 +25°C 100 -40°C 80 60 40 25 20 VIN = 3.8V VO = 3.3V 20 0 30 0 50 100 150 200 250 300 350 VIN = 3.8V VO = 3.3V ILOAD = 0µA 15 10 -40 -25 400 -10 5 LOAD CURRENT (mA) FIGURE 10. GROUND CURRENT vs LOAD 20 35 50 65 TEMPERATURE (°C) 80 FIGURE 11. GROUND CURRENT vs TEMPERATURE VIN = 5.0V VO = 2.85V IL = 150mA CL = 1µF CBYP = 0.01µF 5 3 4 2 VO (V) VOLTAGE (V) VO = 2.85V IL = 150mA VIN 3 2 1 0 POR 1 VEN (V) VO 0 0 110 125 95 0.5 1.0 1.5 2.0 2.5 TIME (s) 3.0 3.5 4.0 FIGURE 12. POWER-UP/POWER-DOWN FN6433 Rev 3.00 December 10, 2015 4.5 5.0 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 TIME (ms) 1.4 1.6 1.8 2.0 FIGURE 13. TURN-ON/TURN-OFF RESPONSE Page 6 of 12 ISL9001A Typical Performance Curves (Continued) VO = 3.3V ILOAD = 300mA CLOAD = 1µF CBYP = 0.01µF VO = 2.8V ILOAD = 300mA CLOAD = 1µF CBYP = 0.01µF 4.3V 4.2V 3.6V 3.5V 10mV/DIV 10mV/DIV 400µs/DIV 400µs/DIV FIGURE 14. LINE TRANSIENT RESPONSE, 3.3V OUTPUT FIGURE 15. LINE TRANSIENT RESPONSE, 2.8V OUTPUT VO (25mV/DIV) VO = 1.8V VIN = 2.8V 300mA ILOAD SPECTRAL NOISE DENSITY (nV/Hz) 1000 100 10 VIN = 3.6V VO = 1.8V ILOAD = 10mA 1 CBYP = 0.1µF CIN = 1µF CLOAD = 1µF 100µA 0.1 10 100 1k 10k FREQUENCY (Hz) 100µs/DIV FIGURE 16. LOAD TRANSIENT RESPONSE 100k FIGURE 17. SPECTRAL NOISE DENSITY vs FREQUENCY 100 VIN = 3.6V VO = 1.8V IO = 10mA CBYP = 0.1µF CLOAD = 1µF 90 80 PSRR (dB) 70 60 50 40 30 20 10 0 100 1k 10k FREQUENCY (Hz) 100k 1M FIGURE 18. PSRR vs FREQUENCY FN6433 Rev 3.00 December 10, 2015 1M Page 7 of 12 ISL9001A Pin Description PIN NUMBER PIN NAME 1 VIN Supply Voltage/LDO Input: Connect a 1µF capacitor to GND. 2 EN LDO Enable. 3 CBYP Reference Bypass Capacitor Pin: Optionally connect capacitor of value 0.01µF to 0.1µF between this pin and GND to achieve lowest noise and highest PSRR. 4 CPOR POR Delay Setting Capacitor Pin: Connect a capacitor between this pin and GND to delay the POR output release after the output reaches 94% of its specified voltage level. (200ms delay per 0.01µF). 5 GND 6 NC 7 POR 8 VO DESCRIPTION GND is the connection to system ground. Connect to PCB Ground plane. Do not connect. Open-drain POR Output (active-low): Internally connected to VO through 100k resistor. LDO Output: Connect capacitor of value 1µF to 10µF to GND (1µF recommended). Typical Application ISL9001A VIN (2.3V TO 5V) 1 ON 2 ENABLE OFF 3 C1 C2 4 C4 VIN EN VO POR VOUT OK 7 VOUT TOO LOW CBYP CPOR 8 GND 5 VOUT (200ms DELAY, C4 = 0.01µF) C3 C1, C3: 1µF X5R CERAMIC CAPACITOR C2: 0.1µF X7R CERAMIC CAPACITOR C4: 0.01µF X7R CERAMIC CAPACITOR FN6433 Rev 3.00 December 10, 2015 Page 8 of 12 ISL9001A Block Diagram VIN VO UVLO CONTROL LOGIC SHORT CIRCUIT, THERMAL PROTECTION, SOFT-START + EN + - VO 100k 1.0V GND BANDGAP AND TEMPERATURE SENSOR VOLTAGE AND REFERENCE GENERATOR CBYP Functional Description The ISL9001A contains all circuitry required to implement a high performance LDO. High performance is achieved through a circuit that delivers fast transient response to varying load conditions. In a quiescent condition, the ISL9001A adjusts its biasing to achieve the lowest standby current consumption. The device also integrates current limit protection, smart thermal shutdown protection, and soft-start. Smart thermal shutdown protects the device against overheating. Power Control The ISL9001A has an enable pin (EN) to control power to the LDO output. When EN is low, the device is in shutdown mode. During this condition, all on-chip circuits are off, and the device draws minimum current, typically less than 0.1µA. When the enable pin is asserted, the device first polls the output of the UVLO detector to ensure that VIN voltage is at least about 2.1V. Once verified, the device initiates a start-up sequence. During the start-up sequence, trim settings are first read and latched. Then, sequentially, the bandgap, reference voltage and current generation circuitry power up. Once the references are stable, a fast-start circuit quickly charges the external reference bypass capacitor (connected to the CBYP pin) to the proper operating voltage. Once the bypass capacitor has been charged, the LDO powers up. FN6433 Rev 3.00 December 10, 2015 POR POR DELAY 1.0V 0.94V 0.9V CPOR GND During operation, whenever the VIN voltage drops below about 1.84V, the ISL9001A immediately disables the LDO output. When VIN rises back above 2.1V, the device re-initiates its start-up sequence and LDO operation will resume automatically. Reference Generation The reference generation circuitry includes a trimmed bandgap, a trimmed voltage reference divider, a trimmed current reference generator, and an RC noise filter. The filter includes the external capacitor connected to the CBYP pin. A 0.01µF capacitor connected CBYP implements a 100Hz lowpass filter, and is recommended for most high performance applications. For the lowest noise application, a 0.1µF CBYP capacitor should be used. This filters the reference noise to below the 10Hz to 1kHz frequency band, which is crucial in many noise-sensitive applications. The bandgap generates a zero temperature coefficient (TC) voltage for the reference divider. The reference divider provides the regulation reference, POR detection thresholds, and other voltage references required for current generation and over-temperature detection. The current generator outputs references required for adaptive biasing as well as references for LDO output current limit and thermal shutdown determination. Page 9 of 12 ISL9001A LDO Regulation and Programmable Output Divider The LDO Regulator is implemented with a high-gain operational amplifier driving a PMOS pass transistor. The design of the ISL9001A provides a regulator that has low quiescent current, fast transient response, and overall stability across all operating and load current conditions. LDO stability is guaranteed for a 1µF to 10µF output capacitor that has a tolerance better than 20% and ESR less than 200m. The design is performance-optimized for a 1µF capacitor. Unless limited by the application, use of an output capacitor value above 4.7µF is not recommended as LDO performance improvement is minimal. Soft-start circuitry integrated into each LDO limits the initial ramp-up rate to about 30µs/V to minimize current surge. The ISL9001A provides short-circuit protection by limiting the output current to about 425mA. The LDO uses an independently trimmed 1V reference as its input. An internal resistor divider drops the LDO output voltage down to 1V. This is compared to the 1V reference for regulation. The resistor division ratio is programmed in the factory. Power-On Reset Generation The power-good state is exited when the LDO output falls below 90% of the expected output voltage for a period longer than the PGOOD exit delay time. While power-good is false, the ISL9001A pulls the POR pin low. The PGOOD entry and exit delays are determined by the value of an external capacitor connected to the CPOR pin. For a 0.01µF capacitor, the entry and exit delays are 200ms and 25µs respectively. Larger or smaller capacitor values will yield proportionately longer or shorter delay times. The POR exit delay should never be allowed to be less than 10µs to ensure sufficient immunity against transient induced false POR triggering. Overheat Detection The bandgap outputs a proportional-to-temperature current that is indicative of the temperature of the silicon. This current is compared with references to determine if the device is in danger of damage due to overheating. When the die temperature reaches about +140°C, if the LDO is sourcing more than 50mA, it shuts down until the die cools sufficiently. Once the die temperature falls back below about +110°C, the disabled LDO is re-enabled and soft-start automatically takes place. The ISL9001A has a Power-on Reset signal generation circuit, which indicates that output power is good. The POR signal is generated as follows. A POR comparator continuously monitors the output of the LDO. The LDO enters a power-good state when the output voltage is above 94% of the expected output voltage for a period exceeding the LDO PGOOD entry delay time (see the following). In the power-good state, the open-drain POR output is in a high-impedance state. An internal 100k pull-up resistor pulls the pin up to the LDO output voltage. An external resistor can be added between the POR output and the LDO output for a faster rise time, however, the POR output should not connect through an external resistor to a supply greater than the LDO voltage. FN6433 Rev 3.00 December 10, 2015 Page 10 of 12 ISL9001A Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION December 10, 2015 FN6433.3 CHANGE Added Rev History and About Intersil Verbiage. Updated Ordering Information on page 2 Updated POD L8.2x3 to most current version. Rev changes are as follows: Tiebar Note 5 updated From: Tiebar shown (if present) is a non-functional feature. To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends). Bottom View: Changed exposed pad height from 1.80 +/-0.10 to 1.80 +0.10/-0.15 Changed exposed pad width from 1.65 +/-0.10 to 1.65 +0.10/-0.15 Side View: Changed 0.05 to 0.05 MAX Converted to new POD standards by adding land pattern and moving dimensions from table onto drawing. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support © Copyright Intersil Americas LLC 2007-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6433 Rev 3.00 December 10, 2015 Page 11 of 12 ISL9001A Package Outline Drawing L8.2x3 8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 3/15 2.00 A 2X 1.50 PIN 1 INDEX AREA 6 PIN #1 INDEX AREA 6X 0.50 1 1.80 +0.10/-0.15 3.00 B (4X) 0.15 8 8X 0.40 ±0.10 TOP VIEW 1.65 +0.10/-0.15 8X 0.25 +0.07/-0.05 4 0.10 M C A B BOTTOM VIEW SEE DETAIL "X" 0.90 ±0.10 0.10 C (1.65) (1.50) (8X 0.60) C BASE PLANE SEATING PLANE 0.08 C 0.05 MAX SIDE VIEW (2.80)(1.80) 0.20 REF C (6X 0.50) 0.05 MAX (8X 0.25) DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: FN6433 Rev 3.00 December 10, 2015 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.25mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends). 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Compies to JEDEC MO-229 VCED-2. Page 12 of 12