LINER LT3070IUFDTR 5a, low noise, programmable output, 85mv dropout linear regulator Datasheet

Electrical Specifications Subject to Change
LT3070
5A, Low Noise,
Programmable Output,
85mV Dropout
Linear Regulator
FEATURES
DESCRIPTION
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The LT®3070 is a low voltage, UltraFast™ transient response linear regulator. The device supplies up to 5A of
output current with a typical dropout voltage of 85mV.
A 0.01μF reference bypass capacitor decreases output
voltage noise to 25μVRMS. The LT3070’s high bandwidth
permits the use of low ESR ceramic capacitors, saving
bulk capacitance and cost. The LT3070’s features make
it ideal for high performance FPGAs, microprocessors or
sensitive communication supply applications.
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Output Current: 5A
Dropout Voltage: 85mV Typical
Digitally Programmable VOUT : 0.8V to 1.8V
Digital Output Margining: ±1%, ±3% or ±5%
Low Output Noise: 25μVRMS (10Hz to 100kHz)
Parallelable: Use Two for a 10A Output
Precision Current Limit: ±10%
±1% Accuracy Over Line, Load and Temperature
Stable with Low ESR Ceramic Output Capacitors
(15μF Minimum)
High Frequency PSRR: 35dB at 1MHz
Enable Function Turns Output On/Off
VIOC Pin Controls Buck Converter to Maintain Low
Power Dissipation and Optimize Efficiency
PWRGD/UVLO Flag
Current Limit Foldback Protection
Thermal Shutdown
28-Lead (4mm × 5mm) QFN Package
Internal protection includes UVLO, reverse-current protection, precision current limiting with power foldback and
thermal shutdown. The LT3070 regulator is available in a
thermally enhanced 28-lead, 4mm × 5mm QFN package.
APPLICATIONS
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Output voltage is digitally selectable in 50mV increments
over a 0.8V to 1.8V range. A margining function allows the
user to tolerance system output voltage in increments of
±1%, ±3% or ±5%. The IC incorporates a unique tracking
function to control a buck regulator powering the LT3070’s
input. This tracking function drives the buck regulator to
maintain the LT3070’s input voltage to VOUT + 300mV,
minimizing power dissipation.
FPGA and DSP Supplies
ASIC and Microprocessor Supplies
Servers and Storage Devices
Post Buck Regulation and Supply Isolation
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. UltraFast is a trade mark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
0.9V, 5A Regulator
PWRGD
4
2.2μF
BIAS
330μF
IN
PWRGD
EN
SENSE
VO0
LT3070
3
OUT
2.2μF
VO1
4.7μF
10μF
VOUT
0.9V
5A
XXX
VIN
1.2V
Dropout Voltage
50k
VBIAS
2.2V TO 3.6V
PLACE HOLDER
2
VO2
MARGSEL
1
MARGTOL
VIOC
1nF
REF/BYP
GND
0.01μF
3070 TA01a
0
0
10
20
30
40
XXX
LTXXXX • TPCXX
3070p
1
LT3070
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
IN, OUT ......................................................... 3.3V, –0.3V
BIAS ................................................................. 4V, –0.3V
VO2, VO1, VO0 Inputs ........................................ 4V, –0.3V
MARGSEL, MARGTOL Input ............................ 4V, –0.3V
EN Input ........................................................... 4V, –0.3V
SENSE Input .................................................... 4V, –0.3V
VIOC, PWRGD Outputs .................................... 4V, –0.3V
REF/BYP Output ............................................... 4V, –0.3V
Output Short-Circuit Duration……...................Indefinite
Operating Junction Temperature (Note 2)
LT3070E/LT3070I .............................. –40°C to 125°C
LT3070MP......................................... –55°C to 125°C
Storage Temperature Range................... –65°C to 150°C
VO0
VO1
VO2
GND
BIAS
EN
TOP VIEW
28 27 26 25 24 23
VIOC 1
22 MARGTOL
PWRGD 2
21 MARGSEL
REF/BYP 3
20 GND
GND 4
19 SENSE
29
IN 5
18 OUT
IN 6
17 OUT
IN 7
16 OUT
IN 8
15 OUT
GND
GND
GND
GND
GND
GND
9 10 11 12 13 14
UFD PACKAGE
28-LEAD (4mm s 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 30°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3070EUFD#PBF
LT3070EUFD#TRPBF
3070
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LT3070IUFD#PBF
LT3070IUFD#TRPBF
3070
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LT3070MPUFD#PBF
LT3070MPUFD#TRPBF
070MP
28-Lead (4mm × 5mm) Plastic QFN
–55°C to 125°C
LEAD BASED FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3070EUFD
LT3070EUFD#TR
3070
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LT3070IUFD
LT3070IUFD#TR
3070
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LT3070MPUFD
LT3070MPUFD#TR
070MP
28-Lead (4mm × 5mm) Plastic QFN
–55°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3070p
2
LT3070
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. COUT = 15μF (Note 9), VIN = VOUT + 0.3V (Note 5), VBIAS = 2.5V unless
otherwise noted.
PARAMETER
CONDITIONS
Minimum IN Pin Voltage
VIN ≥ VOUT + 150mV, IOUT= 5A
MIN
l
TYP
0.95
l
2.2
MAX
3.0
UNITS
V
3.6
V
Regulated Output Voltage
VOUT = 0.8V, 10mA ≤ IOUT ≤ 5A, 1V ≤ VIN ≤ 1.25V
VOUT = 0.9V, 10mA ≤ IOUT ≤ 5A, 1.1V ≤ VIN ≤ 1.35V
VOUT = 1V, 10mA ≤ IOUT ≤ 5A, 1.2V ≤ VIN ≤ 1.45V
VOUT = 1.1V, 10mA ≤ IOUT ≤ 5A, 1.3V ≤ VIN ≤ 1.55V
VOUT = 1.2V, 10mA ≤ IOUT ≤ 5A, 1.4V ≤ VIN ≤ 1.65V
VOUT = 1.5V, 10mA ≤ IOUT ≤ 5A, 1.7V ≤ VIN ≤ 1.95V
VOUT = 1.8V, 10mA ≤ IOUT ≤ 5A, 2.0V ≤ VIN ≤ 2.25V
l
l
l
l
l
l
l
0.792
0.891
0.990
1.089
1.189
1.485
1.782
0.800
0.900
1.000
1.100
1.200
1.500
1.800
0.808
0.909
1.010
1.111
1.212
1.515
1.818
V
V
V
V
V
V
V
Regulated Output Voltage Margining
(Note 3)
MARGTOL = 0V, MARGSEL = VBIAS
MARGTOL = 0V, MARGSEL = 0V, IOUT = 10mA
l
l
0.7
–1.3
1
–1
1.3
–0.7
%
%
MARGTOL = FLOAT, MARGSEL = VBIAS
MARGTOL = FLOAT, MARGSEL = 0V, IOUT = 10mA
l
l
2.7
–3.3
3
–3
3.3
–2.7
%
%
MARGTOL = VBIAS, MARGSEL= VBIAS
MARGTOL = VBIAS, MARGSEL = 0V, IOUT = 10mA
l
l
4.7
–5.3
5
–5
5.3
–4.7
%
%
Line Regulation to VIN
VOUT = 0.8V, ΔVIN = 1.1V to 3.0V, VBIAS = 3.3V, IOUT = 10mA
VOUT = 1.8V, ΔVIN = 2.1V to 3.0V, VBIAS = 3.3V, IOUT = 10mA
l
l
1.0
1.0
mV
mV
Line Regulation to VBIAS
VOUT = 0.8V, ΔVBIAS = 2.2V to 3.6V, VIN = 1.1V, IOUT = 10mA
VOUT = 1.8V, ΔVBIAS = 3.1V to 3.6V, VIN = 2.1V, IOUT = 10mA
l
l
2.0
1.0
mV
mV
Load Regulation, ΔIOUT = 10mA to 5A
VBIAS = 3.3V, VIN = 1.1V, VOUT = 0.8V
–1.5
–3.0
–5.0
mV
mV
–1.5
–3.0
–5.0
mV
mV
–1.8
–3.6
–6.0
mV
mV
–2.3
–4.5
–7.5
mV
mV
–2.7
–5.4
–9.0
mV
mV
20
mV
45
55
63
mV
mV
85
105
150
mV
mV
Minimum BIAS Pin Voltage (Note 3)
VBIAS = 3.3V, VIN = 1.3V, VOUT = 1.0V
VBIAS = 3.3V, VIN = 1.5V, VOUT = 1.2V
VBIAS = 3.3V, VIN = 1.8V, VOUT = 1.5V
VBIAS = 3.3V, VIN = 2.1V, VOUT = 1.8V
Dropout Voltage, VIN = VOUT(NOMINAL)
(Note 6)
IOUT = 1A
IOUT = 2.5A
IOUT = 5A
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l
l
l
l
l
l
l
SENSE Pin Current
VBIAS = 3.3V, VIN = 1.1V, VOUT = 0.8
VBIAS = 3.3V, VIN = 2.1V, VOUT = 1.8V
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l
35
210
50
300
65
390
μA
μA
Ground Pin Current, VIN = 1.3V,
VOUT = 1V
IOUT = 10mA
IOUT = 5A
l
l
0.45
0.62
0.72
0.88
1.15
1.45
mA
mA
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LT3070
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. COUT = 15μF (Note 9), VIN = VOUT + 0.3V (Note 5), VBIAS = 2.5V unless
otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
BIAS Pin Current in Nap Mode
EN = Low (After POR Completed)
l
300
420
650
μA
BIAS Pin Current, VIN = 1.3V, VOUT = 1V
IOUT = 10mA
IOUT = 100mA
IOUT = 500mA
IOUT = 1A
IOUT = 2.5A
IOUT = 5A
l
l
l
l
l
l
1.20
2.05
2.75
3.40
4.85
5.20
1.80
2.60
3.70
4.60
6.40
7.25
2.40
3.70
5.45
6.80
9.40
11.45
mA
mA
mA
mA
mA
mA
Current Limit (Note 5)
VIN – VOUT < 0.5V
VIN – VOUT = 0.6V
VIN – VOUT = 1.0V
VIN – VOUT = 1.5V
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l
l
l
5.2
4.8
3.4
1.0
Reverse Output Current (Note 8)
VIN = 0V, VOUT = 3V
6
5.2
4.4
1.8
A
A
A
A
200
400
μA
87.5
83.5
90
86
92.5
88.5
%
%
PWRGD VOUT Threshold
Percentage of VOUT(NOMINAL), VOUT Rising
Percentage of VOUT(NOMINAL), VOUT Falling
l
l
PWRGD VOL
IPWRGD = 200μA (Fault Condition)
l
100
mV
VBIAS Undervoltage Lockout
EN = 3.3V, VBIAS Rising
EN = 3.3V, VBIAS Falling
l
l
1.11
0.96
1.50
1.30
2.03
1.62
V
V
l
250
300
350
mV
335
335
μA
μA
VIN-VOUT Servo Voltage by VIOC
VIOC Output Current
VIN = VOUT(NOMINAL) + 150mV, Sourcing
VIN = VOUT(NOMINAL) + 450mV, Sinking
l
l
175
175
256
256
VIL Input Threshold (Logic-0 State),
VO2, VO1, VO0, MARGSEL, MARGTOL
Input Falling
l
0.22
0.42
l
0.75
VIZ Input Range (Logic-Z State),
VO2, VO1, VO0, MARGSEL, MARGTOL
VIH Input Threshold (Logic-1 State),
VO2, VO1, VO0, MARGSEL, MARGTOL
Input Rising
l
l
Input Hysteresis (Both Thresholds),
VO2, VO1, VO0, MARGSEL, MARGTOL
40
V
1.76
V
2.00
2.25
V
52
70
mV
Input Current High,
VO2, VO1, VO0, MARGSEL, MARGTOL
VIH = VBIAS = 2.5V, Current Flows Into Pin
l
27
43
μA
Input Current Low,
VO2, VO1, VO0, MARGSEL, MARGTOL
VIL = 0V, VBIAS = 2.5V, Current Flows Out of Pin
l
26
38
μA
EN Pin Threshold
VOUT = Off to On
VOUT = On to Off
l
l
1.35
0.94
V
V
VEN = VBIAS = 2.5V
l
3.8
7.1
μA
VEN = 0V
l
0.1
μA
EN Pin Logic High Current
EN Pin Logic Low Current
5.0
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LT3070
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. COUT = 15μF (Note 9), VIN = VOUT + 0.3V (Note 5), VBIAS = 2.5V unless
otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
VBIAS Ripple Rejection
VBIAS = VOUT + 1.5VAVG, VRIPPLE =0.5VP-P , fRIPPLE = 120Hz,
VIN – VOUT = 300mV, IOUT = 2.5A
60
72
dB
VIN Ripple Rejection (Notes 3, 4, 5)
VBIAS = 2.5V, VIN – VOUT = 300mV, IOUT = 2.5A,
VRIPPLE = 50mVP-P , fRIPPLE = 120Hz
60
68
dB
Reference Voltage Noise (REF/BYP Pin)
CREF/BYP = 10nF, BW = 10Hz to 100kHz
10
μVRMS
Output Voltage Noise
VOUT = 1V, IOUT = 5A, CREF/BYP = 10nF, COUT = 15μF,
BW = 10Hz to 100kHz
25
μVRMS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3070 regulators are tested and specified under pulse load
conditions such that TJ ≅ TA. The LT3070E is 100% tested at TA = 25°C.
Performance at –40°C and 125°C is assured by design, characterization
and correlation with statistical process controls. The LT3070I is
guaranteed over the –40°C to 125°C operating junction temperature range.
The LT3070MP is 100% tested and guaranteed over the –55°C to 125°C
operating junction temperature range.
Note 3: To maintain proper performance and regulation, the BIAS supply
voltage must be higher than the IN supply voltage. For a given VOUT , the
BIAS voltage must be in the range: (1.2 • VOUT + 935mV) ≤ VBIAS ≤ 3.6V.
Note 4: Operating conditions are limited by maximum junction
temperature. The regulated output voltage specification does not apply
for all possible combinations of input voltage and output current. When
operating at maximum output current, limit the input voltage range to:
VIN < VOUT + 500mV.
Note 5: The LT3070 incorporates safe operating area protection circuitry.
Current limit decreases as the VIN-VOUT voltage increases. Current limit
foldback starts at VIN – VOUT > 500mV. See the Typical Performance
Characteristics for a graph of Current Limit vs VIN – VOUT voltage. The
current limit foldback feature is independent of the thermal shutdown
circuity.
MAX
UNITS
Note 6: Dropout voltage, VDO, is the minimum input to output voltage
differential at a specified output current. In dropout, the output voltage
equals VIN – VDO.
Note 7: GND pin current is tested with VIN = VOUT(NOMINAL) + 300mV and a
current source load. VIOC is a buffered output determined by the value of
VOUT as programmed by the VO2-VO0 pins. VIOC’s output is independent of
the margining function.
Note 8: Reverse output current is tested with the IN pins grounded and the
OUT + SENSE pins forced to the rated output voltage. This is measured as
current into the OUT + SENSE pins.
Note 9: Frequency Compensation: The LTC3070 must be frequency
compensated at its OUT pins with a minimum COUT of 15μF configured
as a cluster of (15×) 1μF ceramic capacitors or as a graduated cluster
of 10μF/4.7μF/2.2μF ceramic capacitors of the same case size. Linear
Technology only recommends X5R or X7R dielectric capacitors.
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LT3070
TYPICAL PERFORMANCE CHARACTERISTICS
VOUT Distribution
VOUT vs Temperature
Load Regulation
Dropout Voltage vs VIN
Dropout Voltage vs VBIAS
Load Transient Response
Current Limit vs VIN
Output Voltage Noise
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LT3070
TYPICAL PERFORMANCE CHARACTERISTICS
Ripple Rejection vs VIN
Ripple Rejection vs VBIAS
Minimum VIN vs Temperature
Line Transient Response vs VIN
Line Transient Response vs VBIAS
Noise vs Output Voltage
BIAS Pin Current vs Load
GND Pin Current vs Load
3070p
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LT3070
PIN FUNCTIONS
VIOC (Pin 1): Voltage for In-to-Out Control. The IC incorporates a unique tracking function to control a buck
regulator powering the LT3070’s input. The VIOC pin is
the output of this tracking function that drives the buck
regulator to maintain the LT3070’s input voltage at VOUT +
300mV. This function maximizes efficiency and minimizes
power dissipation. See the Applications Information section for more information on proper control of the buck
regulator.
PWRGD (Pin 2): Power Good. The PWRGD pin is an opendrain NMOS output that is active low if any one of these
fault modes is detected:
• VOUT is less than 90% of VOUT(NOMINAL) on the rising
edge of VOUT
• VOUT drops below 85% of VOUT(NOMINAL) for more than
25μs
• Junction temperature exceeds 145°C
See the Applications Information section for more information on PWRGD fault modes.
REF/BYP (Pin 3): Reference Filter. The pin is the output
of the bandgap reference and has an impedance of approximately 19kΩ. This pin must not be externally loaded.
Bypassing the REF/BYP pin to GND with a 10nF capacitor
decreases output voltage noise and provides a soft-start
function to the reference. See the Applications Information
section for more information on noise and output voltage
margining considerations.
GND (Pins 4, 9-14, 20, 26): Ground. All GND pins must
be tied together and to Pin 29, the exposed backside of
the package for proper thermal performance. These GND
pins are fused to the internal die attach paddle and exposed
package backside to optimize heat sinking and thermal
resistance performance.
IN (Pins 5, 6, 7, 8): Input Supply. These pins supply
power to the high current pass transistor. Tie all IN pins
together for proper performance. The LT3070 requires a
bypass capacitor at IN to maintain stability and low input
impedance over frequency. A 47μF input bypass capacitor
suffices for most battery and power plane impedances.
Minimizing input trace inductance optimizes performance.
Applications that operate with low VIN-VOUT differential
voltages and that have large, fast load transients may require
much higher input capacitor requirements to prevent the
input supply from drooping and allowing the regulator to
enter dropout. See the Applications Information section
for more information on input capacitor requirements.
OUT (Pins 15, 16, 17, 18): Output. These pins supply
power to the load. Tie all OUT pins together for proper
performance. A minimum output capacitance of 15μF is
required for stability. LTC recommends low ESR, X5R or
X7R dielectric ceramic capacitors for best performance.
A parallel ceramic capacitor combination of 10μF + 4.7μF
+ 2.2μF provides excellent stability and load transient
response. Large load transient applications require larger
output capacitors to limit peak voltage transients. See the
Applications Information section for more information on
output capacitor requirements.
SENSE (Pin 19): Kelvin Sense for OUT . The SENSE pin is
the inverting input to the error amplifier. Optimum regulation
is obtained when the SENSE pin is connected to the OUT
pins of the regulator. In critical applications, the resistance
(RP) of PCB traces between the regulator and the load cause
small voltage drops, creating a load regulation error at the
point of load. Connecting the SENSE pin at the load instead
of directly to OUT eliminates this voltage error. Figure 1
illustrates this Kelvin-Sense connection method. Note that
the voltage drop across the external PCB traces adds to the
dropout voltage of the regulator. The SENSE pin input bias
current depends on the selected output voltage. SENSE
pin input current varies from 50μA typically at VOUT = 0.8V
to 300μA typically at VOUT = 1.8V.
+
VBIAS
BIAS
IN
SENSE
EN
VO2
OUT
LT3070
+
RP
PWRGD
VO1
VO0
VIN
LOAD
MARGSEL
MARGTOL
VIOC
REF/BYP
GND
RP
3070 F01
Figure 1. Kelvin Sense Connection
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LT3070
PIN FUNCTIONS
MARGSEL (Pin 21): Margining Enable and Polarity Selection. This three-state pin determines both the polarity
and the active state of the margining function. The logic
low threshold is less than 220mV referenced to GND and
enables negative voltage margining. The logic “high”
threshold is greater than VBIAS – 500mV and enables
positive voltage margining. The voltage range between
these two logic thresholds defines the logic Hi-Z state
and disables the margining function.
MARGTOL (Pin 22): Margining Tolerance. This threestate pin selects the absolute value of margining (1%,
3% or 5%) if enabled by the MARGSEL input. The logic
low threshold is less than 220mV referenced to GND and
enables either ±1% change in VOUT depending on the state
of the MARGSEL pin. The logic high threshold is greater
than VBIAS – 500mV and enables either ±5% change in
VOUT depending on the state of the MARGSEL pin. The
voltage range between these two logic thresholds defines
the logic Hi-Z state and enables either ±3% change in VOUT
depending on the state of the MARGSEL pin.
VO2, VO1 and VO0 (Pins 23, 24, 25): Output Voltage Select.
These three-state pins combine to select a nominal output
voltage from 0.8V to 1.8V in increments of 50mV. Output
voltage is limited to 1.8V maximum by an internal override
of VO1 when VO2 = “1”. The input logic “0” threshold is less
than 220mV referenced to GND and the logic “1” threshold
is greater than VBIAS – 500mV. The range between these
two thresholds defines the logic Hi-Z state. See Table 1 in
the Applications Information section that defines the VO2,
VO1 and VO0 settings versus VOUT .
BIAS (Pin 27): Bias Supply. This pin supplies current
to most of the internal control circuitry and the output
stage driving the pass transistor. The LT3070 requires a
minimum 2.2μF bypass capacitor for stability and proper
operation. To ensure proper operation, the BIAS voltage
must conform to the equation:
(1.2 • VOUT) + 935mV ≤ VBIAS ≤ 3.6V
EN (Pin 28): Enable. This pin starts the internal reference,
enables all outputs and enables all support functions.
After start-up, pulling the EN pin low keeps the reference
circuit active, but disables the output transistor and puts
the LT3070 into a lower power “nap” mode. Drive the EN
pin with either a digital logic port or an open-collector NPN
or open-drain NMOS terminated with a pull-up resistor to
VBIAS. The pull-up resistor must be no larger than 35k to
meet the VIH condition of the EN pin. If unused, connect
the EN pin to VBIAS.
Exposed Pad (Pin 29): GND. Tie the Exposed Pad to all
GND pins and directly to the PCB GND. This Exposed Pad
provides enhanced thermal performance with its connection to the PCB GND. See the Applications Information
section for thermal considerations and calculating junction
temperature.
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LT3070
BLOCK DIAGRAM
27
BIAS
UVLO AND
THERMAL
SHUTDOWN
IN
5-8
+
ISENSE
REF/BYP
–
+
EAMP
BUF
–
OUT
15-18
LDO CORE
SENSE
DETECT
VIOC
+
–
1
PWRGD
19
2
VOUT(NOM) + 300mV
VREF
GND
REF/BYP
3
4,9-14,20,26,29
PROGRAM CONTROL
EN
28
VO2 VO1 VO0 MARGSEL MARGTOL
25
24
23
21
22
3070 BD
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LT3070
APPLICATIONS INFORMATION
Introduction
Current generation FPGA and ASIC processors place
stringent demands on the power supplies that power the
core, I/O and transceiver channels. These microprocessors
may cycle load current from near zero to amps in tens of
nanoseconds. Output voltage specifications, especially in
the 1V range, require tight tolerances including transient
response as part of the requirement. Some ASIC processors
require only a single output voltage from which the core
and I/O circuitry operate. Some high performance FPGA
processors require separate power supply voltages for the
processor core, the I/O, and the transceivers. Often, these
supply voltages must be low noise and high bandwidth
to achieve the lowest bit-error rates. These requirements
mandate the need for very accurate, low noise, high current, very high speed regulator circuits that operate at low
input and output voltages.
The LT3070 is a low voltage, UltraFast transient response
linear regulator. The device supplies up to 5A of output
current with a typical dropout voltage of 85mV. A 0.01μF
reference bypass capacitor decreases output voltage noise
to 25μVRMS (BW = 10Hz to 100kHz). The LT3070’s high
bandwidth provides UltraFast transient response using low
ESR ceramic output capacitors (15μF minimum), saving
bulk capacitance, PCB area and cost.
The LT3070’s features permit state-of-the-art linear regulator performance. The LT3070 is ideal for high performance
FPGAs, microprocessors, sensitive communication supplies, and high current logic applications that also operate
over low input and output voltages.
Output voltage for the LT3070 is digitally selectable in
50mV increments over a 0.8V to 1.8V range. A margining
function allows the user to tolerance system output voltage
in increments of ±1%, ±3% or ±5%.
The IC incorporates a unique tracking function, which if
enabled by the user, controls an upsteam regulator powering the LT3070’s input (see Figure 8). This tracking function
drives the buck regulator to maintain the LT3070’s input
voltage to VOUT + 300mV. This input-to-output voltage
control allows the user to change the regulator output
voltage, and have the switching regulator powering the
LT3070’s input to track to the optimum input voltage with
no component changes.
This combines the efficiency of a switching regulator
with superior linear regulator response. It also permits
thermal management of the system even with a maximum
5A output load.
LT3070 internal protection includes input undervoltage
lockout (UVLO), reverse-current protection, precision current limiting with power foldback and thermal shutdown.
The LT3070 regulator is available in a thermally enhanced
28-lead, 4mm × 5mm QFN package.
The LT3070’s architecture drives an internal N-channel
power MOSFET as a source follower. This configuration
permits a user to realize an extremely low dropout, UltraFast transient response regulator with excellent high frequency PSRR performance. The LT3070 achieves superior
regulator bandwidth and transient load performance by
eliminating expensive bulk tantalum or electrolytic capacitors in the most modern and demanding microprocessor
applications. Users realize significant cost savings as all
additional bulk capacitance is removed. The additional
savings of insertion cost, purchasing/inventory cost and
board space are readily apparent. Precision incremental
output voltage control accommodates legacy and future
microprocessor power supply voltages.
Output capacitor networks simplify to direct parallel combinations of ceramic capacitors. Often, the high frequency
ceramic decoupling capacitors required by these various
FPGA and ASIC processors are sufficient to stabilize the
system (see Stability and Output Capacitance section). This
regulator design provides ample bandwidth and responds
to transient load changes in a few hundred nanoseconds
versus regulators that respond in many microseconds.
The LT3070 also incorporates precision current limiting,
enable/disable control of output voltage and integrated
overvoltage and thermal shutdown protection. The
LT3070’s unique design combines the benefits of low
dropout voltage, high functional integration, precision
performance and UltraFast transient response, as well as
providing significant cost savings on the output capacitance
needed in fast load transient applications.
As lower voltage applications become increasingly prevalent with higher frequency switching power supplies, the
LT3070 offers superior regulation and an appreciable
3070p
11
LT3070
APPLICATIONS INFORMATION
component cost savings. The LT3070 steps to the next
level of performance for the latest generation FPGAs, DSPs
and microprocessors. The simple versatility and benefits
derived from these circuits exceed the power supply needs
of today’s high performance microprocessors.
Programming Output Voltage
Three tri-level input pins, VO2, VO1 and VO0, select the
value of output voltage. Table 1 illustrates the 3-bit digital
word to output voltage table resulting from setting these
pins high, low or allowing them to float.
These pins may be tied high or tied low by either pin-strapping them to VBIAS or driving them with digital ports. Pins
that float may either actually float or require logic that has
Hi-Z output capability. This allows output voltage to be
dynamically changed if necessary.
Output voltage is selectable from a minimum of 0.8V to
a maximum of 1.8V in increments of 50mV. The MSB,
VO2, sets the pedestal voltage, and the LSB’s, VO1 and
VO0 increment VOUT .
Output voltage is limited to 1.8V maximum by an internal
override of VO1 (default to “0”) when VO2 = “1”.
Table 1: VO2-VO0 Settings vs Output Voltage
VO2
VO1
VO0
VOUT(NOM)
VO2
VO1
VO0
VOUT(NOM)
0
0
0
0.80V
Z
0
1
1.35V
0
0
Z
0.85V
Z
Z
0
1.40V
0
0
1
0.90V
Z
Z
Z
1.45V
0
Z
0
0.95V
Z
Z
1
1.50V
0
Z
Z
1.00V
Z
1
0
1.55V
0
Z
1
1.05V
Z
1
Z
1.60V
0
1
0
1.10V
Z
1
1
1.65V
0
1
Z
1.15V
1
X
0
1.70V
0
1
1
1.20V
1
X
Z
1.75V
Z
0
0
1.25V
1
X
1
1.80V
Z
0
Z
1.30V
X = Don’t Care, 0 = GND, Z = Float, 1 = VBIAS
The input logic “0” threshold is less than 220mV referenced
to GND and the logic “1” threshold is greater than VBIAS
– 500mV. The range between these two thresholds defines
the logic Hi-Z state.
REF/BYP—Voltage Reference
This pin is the buffered output of the internal bandgap
reference and has an output impedance of ≅19kΩ. The
design includes an internal compensation pole at fC = 4kHz.
A 10nF REF/BYP capacitor to GND creates a lowpass pole
at fLP = 840Hz. The 10nF capacitor decreases reference
voltage noise to about 10μVRMS and soft-starts the reference. The LT3070 only soft-starts the reference voltage
during an initial turn-on sequence. If the EN pin is toggled
low after initial turn-on, the reference remains powered-up.
Therefore, toggling the EN pin from low to high does not
soft-start the reference. Only by turning the BIAS supply
voltage on and off will the reference be soft-started. Output
voltage noise is the RMS sum of the reference voltage
noise in addition to the amplifier noise.
The REF/BYP pin must not be DC loaded by anything except
for applications that parallel other LT3070 regulators for
higher output currents. Consult the Applications Section
on Paralleling for further details.
Output Voltage Margining
Two tri-level input pins, MARGSEL (polarity) and MARGTOL
(scale), select the polarity and amount of output voltage
margining. Margining is programmable in increments of
±1%, ±3% and ±5%. Margining is internally implemented
as a scaling of the reference voltage.
Table 2 illustrates the 2-bit digital word to output voltage
margining resulting from setting these pins high, low or
allowing them to float.
These pins may be set high or set low by either pin-strapping them to VBIAS or driving them with digital ports. Pins
that float may either actually float or require logic that has
“Hi-Z” output capability. This allows output voltage to be
dynamically margined if necessary.
The MARGSEL pin determines both the polarity and the
active state of the margining function. The logic “low”
threshold is less than 220mV referenced to GND and
enables negative voltage margining. The logic “high”
threshold is greater than VBIAS – 500mV and enables
3070p
12
LT3070
APPLICATIONS INFORMATION
positive voltage margining. The voltage range between
these two logic thresholds defines the logic Hi-Z state
and disables the margining function.
The MARGTOL pin selects the absolute value of margining
(1%, 3% or 5%) if enabled by the MARGSEL input. The
logic “low” threshold is less than 220mV referenced to
GND and enables either ±1% change in VOUT depending on
the state of the MARGSEL pin. The logic “high” threshold
is greater than VBIAS – 500mV and enables either ±5%
change in VOUT depending on the state of the MARGSEL
pin. The voltage range between these two logic thresholds
defines the logic Hi-Z state and enables either ±3% change
in VOUT depending on the state of the MARGSEL pin.
Table 2: Programming Margining
MARGSEL
MARGTOL
% of VOUT(NOM)
0
0
–1
0
Z
–3
0
1
–5
Z
0
0
Z
Z
0
Z
1
0
1
0
1
1
Z
3
1
1
5
Enable Function—Turning On and Off
The first rising edge of the EN enable pin starts the LT3070
reference and all support functions while enabling the
output. After start-up, pulling the EN pin low places the
regulator into nap mode. In nap mode, the reference circuit
remains active, but the output is disabled and quiescent
current decreases.
Drive the EN pin with either a digital logic port or an opencollector NPN or open-drain NMOS terminated with a
pull-up resistor to VBIAS. The pull-up resistor must be no
larger than 35k to meet the VIH condition of the EN pin. If
unused, connect the EN pin to VBIAS.
Input Undervoltage Lockout on BIAS Pin
An internal undervoltage lockout (UVLO) comparator
monitors the BIAS rail. If VBIAS drops below the UVLO
threshold, all functions shut down, the pass transistor is
gated off and output current falls to zero. The typical BIAS
pin UVLO threshold is 1.55V on the rising edge of VBIAS.
The UVLO circuit incorporates about 250mV of hysteresis
on the falling edge of VBIAS.
High Efficiency Linear Regulator—Input-to-Output
Voltage Control
The VIOC (voltage input to output control) pin is a function
to control a switching regulator and facilitate a design solution that maximizes system efficiency at high load currents
and still provides low dropout voltage performance.
The VIOC pin is the output of an integrated transconductance amplifier that sources and sinks 250μA of current.
It typically regulates the output of most LTC® switching
regulators or LTM® power modules, by sinking current
from the ITH compensation node. The VIOC function
controls a buck regulator powering the LT3070’s input by
maintaining the LT3070’s input voltage to VOUT + 300mV.
This 300mV VIN-VOUT differential voltage is chosen to
provide fast transient response and good high frequency
PSRR while minimizing power dissipation and maximizing
efficiency. For example, 1.5V to 1.2V conversion and 1.3V
to 1V conversion yield 1.5W maximum power dissipation
at 5A full output current.
Figure 2 depicts that the switcher’s feedback resistor network sets the maximum switching regulator output voltage
if the linear regulator is disabled. However, once the LT3070
is enabled, the VIOC feedback loop decreases the switching
regulator output voltage back to VOUT + 300mV.
Using the VIOC function creates a feedback loop between
the LT3070 and the switching regulator. As such, the
feedback loop must be frequency compensated for stability. Fortunately, the connection of VIOC to many LTC ITH
pins represents a high impedance characteristic which is
the optimum circuit node to frequency compensate the
feedback loop. Figure 2 illustrates the typical frequency
compensation network used at the VIOC node to GND.
The VIOC amplifier characteristics are:
gm = 3.2mS, IOUT = ±250μA, BW = 10MHz.
If the VIOC is not used, terminate the VIOC pin to GND with
a small capacitor (1000pF) to prevent oscillations.
3070p
13
LT3070
APPLICATIONS INFORMATION
IN
LT3070
OUT
LOAD
SWITCHING REGULATOR
REF
+
–
PWM
FB
VOUT +
VREF 300mV
VIOC
REFERENCE
ITH
3070 F02
Figure 2. VIOC Control Block Diagram
PWRGD—Power Good
PWRGD is an open-drain digital output pin that pulls “low”
if it detects any one of several fault modes including:
• VOUT is less than 90% of VOUT(NOMINAL) on the rising
edge of VOUT
• VOUT decreases below 85% of VOUT(NOMINAL) for more
than 25μs
• VIN decreases below VOUT
• Junction temperature exceeds 145°C typically*
*The junction temperature detector is an early warning
indicator that trips approximately 20°C before thermal
shutdown engages.
Stability and Output Capacitance
The LT3070’s feedback loop requires an output capacitor
for stability. Choose COUT carefully and mount it in close
proximity to the LT3070’s OUT and GND pins. Include wide
routing planes for OUT and GND to minimize inductance.
If possible, mount the regulator immediately adjacent to
the application load to minimize distributed inductance
for optimal load transient performance. Point-of-Load
applications present the best case layout scenario for
extracting full LT3070 performance.
Low ESR, X5R or X7R ceramic chip capacitors are the
LTC recommended choice for stabilizing the LT3070. Additional bulk capacitors distributed beyond the immediate
decoupling capacitors are acceptable as their parasitic ESL
and ESR, combined with the distributed PCB inductance
isolates them from the primary compensation pole provided
by the local surface mount ceramic capacitors.
The LT3070 requires a minimum output capacitance of
15μF for stability. LTC strongly recommends that the output
capacitor network consist of several low value ceramic
capacitors in parallel.
Why Do Multiple, Small-Value Output Capacitors
Connected in Parallel Work Better?
The LT3070’s unity-gain bandwidth with COUT of 15μF is
about 1MHz at its full-load current of 5A. Surface mounted
MLCC capacitors have a self-resonance frequency of
fR = 1/(2π√LC), which must be pushed to a frequency higher
than the regulator bandwidth. Standard MLCC capacitors
are acceptable. To keep the resonant frequency greater
than 1MHz, the product 1/(2π√LC) must be greater than
1MHz. At this bandwidth, PCB vias can add significant
inductance, thus the fundamental decoupling capacitors
must be mounted on the same plane as the LT3070.
Typical 0603 or 0805 case-size capacitors have an ESL of
~800pH and PCB mounting can contribute up to ~200pH.
Thus, it becomes necessary to reduce the parasitic inductance by using a parallel capacitor combination. A suitable
methodology must control this paralleling as capacitors
with the same self-resonant frequency, fR, will form a tank
circuit that can induce ringing of their own accord. Small
amounts of ESR (5mΩ to 20mΩ) have some benefit in
dampening the resonant loop, but higher ESRs degrade
3070p
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LT3070
APPLICATIONS INFORMATION
LT3070
SENSE
IN OUT
GND
Lo-Z
INPUT
Give additional consideration to the use of ceramic
capacitors. Ceramic capacitors are manufactured with
a variety of dielectrics, each with different behavior
across temperature and applied voltage. The most common dielectrics used are specified with EIA temperature
characteristic codes of Z5U, Y5V, X5R and X7R. The Z5U
and Y5V dielectrics are good for providing high capacitances in a small package, but they tend to have strong
voltage and temperature coefficients as shown in Figures
4 and 5. When used with a 5V regulator, a 16V 10μF Y5V
capacitor can exhibit an effective value as low as 1μF to
2μF for the DC bias voltage applied and over the operating
20
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10μF
0
X5R
–20
–40
–60
Y5V
–80
LOAD PLANE
2.2μF
47μF
LT3070’s unity-gain crossover frequency. This technique
illustrates the method that extracts the full bandwidth
performance of the LT3070.
CHANGE IN VALUE (%)
the capacitor response to transient load steps with rise/
fall times less than 1μs. The most area efficient parallel
capacitor combination is a graduated 4/2/1 scale of fR of
the same case size. Under these conditions, the individual
ESLs are relatively uniform, and the resonance peaks are
deconstructively spread beyond the regulator bandwidth.
The recommended parallel combination that approximates
15μF is 10μF + 4.7μF + 2.2μF. Capacitors with case sizes
larger than 0805 have higher ESL and lower ESR (<5mΩ).
Therefore, more capacitors with smaller values (<10μF)
must be chosen. Users should consider new generation,
low inductance capacitors to push out fR and maximize
stability. Refer to the surface mount ceramic capacitor
manufacturer’s data sheets for capacitor specifications.
Figure 3 illustrates an optimum PCB layout for the parallel output capacitor combination, but also illustrates the
GND connection between the IN capacitor and the OUT
capacitors to minimize the AC GND loop for fast load
transients. This tight bypassing connection minimizes
EMI and optimizes bypassing.
–100
4.7μF
0
2
10μF
10 12
4
8
6
DC BIAS VOLTAGE (V)
14
16
3070 F04
Figure 4. Ceramic Capacitor DC Bias Characteristics
3070 F03
40
Figure 3. Example PCB Layout
Many of the applications in which the LT3070 excels,
such as FPGA, ASIC processor or DSP supplies, typically
require a high frequency decoupling capacitor network for
the device being powered. This network generally consists
of many low value ceramic capacitors in parallel. In some
applications, this total value of capacitance may be close
to the LT3070’s minimum 15μF capacitance requirement.
This may reduce the required value of capacitance directly
at the LT3070’s output. Multiple low value capacitors in
parallel present a favorable frequency characteristic that
pushes many of the parasitic poles/zeroes beyond the
CHANGE IN VALUE (%)
20
0
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10μF
X5R
–20
–40
Y5V
–60
–80
–100
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
125
3070 F05
Figure 5. Ceramic Capacitor Temperature Characteristics
3070p
15
LT3070
APPLICATIONS INFORMATION
temperature range. The X5R and X7R dielectrics result in
more stable characteristics and are more suitable for use
as the output capacitor. The X7R type has better stability
across temperature, while the X5R is less expensive and
is available in higher values. Care still must be exercised
when using X5R and X7R capacitors; the X5R and X7R
codes only specify operating temperature range and maximum capacitance change over temperature. Capacitance
change due to DC bias with X5R and X7R capacitors
is better than Y5V and Z5U capacitors, but can still be
significant enough to drop capacitor values below appropriate levels. Capacitor DC bias characteristics tend to
improve as component case size increases, but expected
capacitance at operating voltage should be verified. Voltage
and temperature coefficients are not the only sources of
problems. Some ceramic capacitors have a piezoelectric
response. A piezoelectric device generates voltage across
its terminals due to mechanical stress, similar to the way
a piezoelectric microphone works. For a ceramic capacitor the stress can be induced by vibrations in the system
or thermal transients. For this reason, an X7R capacitor
with a 16V maximum voltage rating is recommended for
the REF/BYP pin.
Stability and Input Capacitance
The LT3070 is stable with a minimum capacitance of
47μF connected to its IN pins. Use low ESR capacitors to
minimize instantaneous voltage drops under large load
transient conditions. Large VIN droops during large load
transients may cause the regulator to enter dropout with
corresponding degradation in load transient response.
Increased values of input and output capacitance may be
necessary depending on an application’s requirements.
Sufficient input capacitance is critical as the circuit is
intentionally operated close to dropout to minimize power.
Ideally, the output impedance of the supply that powers
IN should be less than 10mΩ to support a 5A load with
large transients.
In cases where wire is used to connect a power supply
to the input of the LT3070 (and also from the ground of
the LT3070 back to the power supply ground), large input
capacitors are required to avoid an unstable application.
This is due to the inductance of the wire forming an LC
tank circuit with the input capacitor and not a result of the
LT3070 being unstable. The self inductance, or isolated
inductance, of a wire is directly proportional to its length.
However, the diameter of a wire does not have a major
influence on its self inductance. For example, one inch of
18-AWG, 0.04 inch diameter wire has 28nH of self inductance. The self inductance of a 2-AWG isolated wire with
a diameter of 0.26 inch is about half the inductance of a
18-AWG wire. The overall self inductance of a wire can
be reduced in two ways. One is to divide the current flowing towards the LT3070 between two parallel conductors
which flows in the same direction in each. In this case,
the farther the wires are placed apart from each other, the
more inductance will be reduced, up to a 50% reduction
when placed a few inches apart. Splitting the wires basically connects two equal inductors in parallel. However,
when placed in close proximity from each other, mutual
inductance is added to the overall self inductance of the
wires. The most effective way to reduce overall inductance
is to place the forward and return-current conductors (the
wire for the input and the wire for the return ground) in
very close proximity. Two 18-AWG wires separated by 0.05
inch reduce the overall self inductance to about one-forth
of a single isolated wire. If the LT3070 is powered by a
battery mounted in close proximity with ground and power
planes on the same circuit board, a 47μF input capacitor
is sufficient for stability. However, if the LT3070 is powered by a distant supply, use a low ESR, large value input
capacitor on the order of 330μF. As power supply output
impedance varies, the minimum input capacitance needed
for application stability also varies.
Bias Pin Capacitance Requirements
The BIAS pin supplies current to most of the internal
control circuitry and the output stage driving the pass
transistor. The LT3070 requires a minimum 2.2μF bypass
capacitor for stability and proper operation. To ensure
proper operation, the BIAS voltage must conform to the
following equation:
(1.2 • VOUT) + 935mV ≤ VBIAS ≤ 3.6V
3070p
16
LT3070
APPLICATIONS INFORMATION
Load Regulation
The LT3070 provides a Kelvin sense pin for VOUT , allowing
the application to correct for parasitic package and PCB
I-R drops. However, LTC recommends that the SENSE pin
terminate in close proximity to the LT3070’s OUT pins;
this minimizes parasitic inductance and optimizes regulation. The LT3070 handles moderate levels of output line
impedance, but excessive impedance between VOUT and
COUT causes excessive phase shift in the feedback loop
and adversely affects stability.
Figure 1 in the Pin Functions section illustrates the KelvinSense connection method that eliminates voltage drops
due to PCB trace resistance. However, note that the voltage
drop across the external PCB traces adds to the dropout
voltage of the regulator. The SENSE pin input bias current
depends on the selected output voltage. SENSE pin input
current varies from 50μA typically at VOUT = 0.8V to 300μA
typically at VOUT = 1.8V.
Short-Circuit and Overload Recovery
Like many IC power regulators, the LT3070 has safe operating area (SOA) protection. The safe area protection
decreases current limit as input-to-output voltage increases
and keeps the power transistor inside a safe operating
region for all values of input-to-output voltage up to the
absolute maximum voltage rating. VBIAS must be above
the UVLO threshold for any function. The LT3070 has a
precision current limit specified at ±10% that is active if
VBIAS is above UVLO, regardless of the value of VIN.
Under conditions of maximum ILOAD and maximum
VIN-VOUT the device’s power dissipation peaks at about
3W. If ambient temperature is high enough, die junction
temperature will exceed the 125°C maximum operating
temperature. If this occurs, the LT3070 relies on two
additional thermal safety features. At about 145°C, the
PWRGD output pulls low providing an early warning of an
impending thermal shutdown condition. At 165°C typically,
the LT3070’s thermal shutdown engages and the output is
shut down until the IC temperature falls below the thermal
hysteresis limit. The SOA protection decreases current limit
as the IN-to-OUT voltage increases and keeps the power
dissipation at safe levels for all values of input-to-output
voltage. The LT3070 provides some output current at all
values of input-to-output voltage up to the absolute maximum voltage rating. See the Current Limit vs VIN curve in
the Typical Performance Characteristics.
During start-up, after the BIAS voltage has cleared its UVLO
threshold and VIN is increasing, output voltage increases
at the rate of current limit charging COUT .
With a high input voltage, a problem can occur where
in removal of an output short will not allow the output
voltage to recover. Other regulators also exhibit this phenomenon, so it is not unique to the LT3070. The load line
for such a load may intersect the output current curve at
two points: normal operation and the 50A restricted load
current settings. A common situation is immediately after
the removal of a short circuit, but with a static load ≥ 1A.
In this situation, removal of the load or reduction of IOUT
to <1A will clear this condition and allow VOUT to return
to normal regulation.
Reverse Voltage
The LT3070 incorporates a circuit that detects if VIN decreases below VOUT . This reverse-voltage detector has
a typical threshold of about (VIN – VOUT) = –6mV. If the
threshold is exceeded, this detector circuit turns off the
drive to the internal NMOS pass transistor, thereby turning
off the output. The output pulls low with the load current
discharging the output capacitance. This circuit’s intent
is to limit and prevent back-feed current from OUT to IN
if the input voltage collapses due to a fault or overload
condition.
Thermal Considerations
The LT3070’s maximum rated junction temperature of
125°C limits its power handling capability and is dominated by the output current multiplied by the input/output
voltage differential:
IOUT • (VIN – VOUT)
The LT3070’s internal power and thermal limiting circuitry
protect it under overload conditions. For continuous normal load conditions, do not exceed the maximum junction
temperature of 125°C. Give careful consideration to all
sources of thermal resistance from junction to ambient.
This includes junction to case, case-to-heat sink interface,
3070p
17
LT3070
APPLICATIONS INFORMATION
heat sink resistance or circuit board to ambient as the
application dictates. Also, consider additional heat sources
mounted in proximity to the LT3070. The LT3070 is a surface
mount device and as such, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Surface mount heat sinks and
plated through-holes can also be used to spread the heat
generated by power devices. Junction-to-case thermal
resistance is specified from the IC junction to the bottom
of the case directly below the die. This is the lowest resistance path for heat flow. Proper mounting is required to
ensure the best possible thermal flow from this area of the
package to the heat sinking material. Note that the Exposed
Pad is electrically connected to GND. Table 3 lists thermal
resistance for several different copper areas given a fixed
board size. All measurements were taken in still air on a
4-layer 1/16" FR-4 board with one ounce copper.
thus:
Table 3, UDF Plastic Package, 28-Lead QFN
Paralleling Devices for Higher IOUT
COPPER AREA
TOPSIDE*
BACK SIDE
BOARD AREA
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)
2500mm2
2500mm2
2500mm2
30°C/W
1000mm2
2500mm2
2500mm2
32°C/W
225mm2
2500mm2
2500mm2
33°C/W
100mm2
2500mm2
2500mm2
35°C/W
*Device is mounted on topside
Calculating Junction Temperature
Example: Given an output voltage of 0.9V, an input voltage
range of 1.2V ± 5%, a BIAS voltage of 2.5V, a maximum
output current of 4A and a maximum ambient temperature
of 50°C, what will the maximum junction temperature
be?
The power dissipated by the device equals:
IOUT(MAX) • (VIN(MAX) – VOUT) + (IBIAS – IGND) • VOUT
+ IGND • VBIAS
where:
IOUT(MAX) = 4A
VIN(MAX) = 1.26V
P = 4A(1.26V – 0.9V) + (6.91mA – 0.87mA)0.9V +
0.87mA(2.5V) = 1.448W
With the QFN package soldered to maximum copper
area, the thermal resistance is 30°C/W. So the junction
temperature rise above ambient equals:
1.448W at 30°C/W = 43.44°C
The maximum junction temperature equals the maximum
ambient temperature plus the maximum junction temperature rise above ambient or:
TJMAX = 50°C + 43.44°C = 93.44°C
Applications that cannot support extensive PCB space for
heatsinking the LT3070 will require a derating of output
current or increased airflow.
Multiple LT3070s may be paralleled to obtain higher output
current. This paralleling concept borrows from the scheme
employed by the LT3080.
To accomplish this paralleling, tie the IN pins and the OUT
pins of the multiple devices together. Also, tie the REF/BYP
pins of the multiple outputs together. This effectively gives
an averaged value of multiple 600mV reference voltage
sources. The OUT of each LT3070 is connected to the
common load using a small piece of PC trace as a ballast
resistor (≅ 2mΩ) or an actual sense resistor, beyond the
primary output capacitors of each regulator. The ballast
resistor ensures output current sharing (see Figures 8 and
9). Keep this ballast trace area free of solder to maintain
a controlled resistance.
Table 4 shows a simple guideline for PCB trace resistance
as a function of weight and trace width.
Table 4. PC Board Trace Resistance
WEIGHT (Oz)
100 MIL WIDTH
200 MIL WIDTH
1
5.43
2.71
2
2.71
1.36
*Trace resistance is measured in milliohms/in
IBIAS at (IOUT = 4A, VBIAS = 2.5V) = 6.91mA
IGND at (IOUT = 4A, VBIAS = 2.5V) = 0.87mA
3070p
18
LT3070
APPLICATIONS INFORMATION
Quieting the Noise
The LT3070 offers numerous noise performance advantages. Each LDO has several sources of noise. An LDO’s
most critical noise source is the reference, followed by
the LDO error amplifier. Traditional low noise regulators
buffer the voltage reference out to an external pin (usually
through a large value resistor) to allow for bypassing and
noise reduction of reference noise. The LT3070 deviates
from the traditional voltage reference by generating a
low voltage VREF from a reference current into an internal resistor ≅19k. This intermediate impedance node
(REF/BYP) facilitates external filtering directly. A 10nF filter
capacitor minimizes reference noise to 10μVRMS at the
600mV REF/BYP pin, equivalently a 17μV contribution to
output noise at VOUT = 1V. See the Typical Performance
Characteristics for Noise vs Output Voltage performance
as a function of CBYP/REF .
This approach also accommodates reference sharing
between LT3070 regulators that are hooked up in current sharing applications. The REF/BYP filter capacitor
delays the initial power-up time by a factor of the RC time
constant. VREF remains active in nap mode, thus start-up
time is significantly reduced and well controlled coming
out of nap mode (EN:LO↑HI).
50k
VBIAS
3.3V
PWRGD
2.2μF
BIAS
VIN
1.5V
IN
330μF
EN
VO0
PWRGD
SENSE
LT3070 OUT
VO1
2.2μF*
4.7μF*
10μF*
VOUT
1.2V
5A
VO2
NC
MARGSEL
NC
MARGTOL
VIOC
1nF
REF/BYP
GND
*X5R OR X7R
0.01μF
3070 F06
Figure 6. 1.5V to 1.2V Linear Regulator
3070p
19
LT3070
APPLICATIONS INFORMATION
VBIAS
3.3V
50k
PWRGD
47μF
6.3V
s3
2.2μF
1Ω
50k
BIAS
EN
0.1μF
CLKOUT RUN PVIN PVIN SVIN ITHM
TRACK
SGND
10pF
VO2
15k
1%
VFB
PLLLPF
100pF
47μF
NC
NC
15k
IN
ITH
PVIN
PVIN
PVIN
PVIN
SW
SW
LTC3415EUHF
SW
SW
SW
SW
SW
20k
1%
VO1
NC
VO0
NC
MARGSEL
NC
MARGTOL
TBD
VOUT = 1V/5A
2.2μF*
REF/BYP
GND
4.7μF*
LOAD
10μF*
*X5R OR X7R
0.01μF
3070 F07
TBD
NOTE: LTC3415 SWITCHER 2MHz INTERNAL OSCILLATOR
SW
MODE
NC
VIOC
TBD
PWRGD
SENSE
LT3070 OUT
PGOOD
CLKIN
BSEL
PGND
PHMODE
MGN
PGND PGND PGND PGND PGND PGND PGND
100μF
6.3V
s3
1.3V/7A
0.2μH
Figure 7. Regulator with VIOC Buck Control
3070p
20
LT3070
APPLICATIONS INFORMATION
VBIAS
3.3V
50k
PWRGD
47μF
6.3V
s3
2.2μF
1Ω
50k
CLKOUT RUN PVIN PVIN SVIN ITHM
10pF
15k
1%
VFB
PLLLPF
100pF
47μF
PVIN
PVIN
PVIN
PVIN
SW
SW
LTC3415EUHF
SW
SW
SW
SW
SW
18k
1%
VO2
VO0
NC
MARGSEL
NC
MARGTOL
VIOC
PGND
PHMODE
P.O.L 1
10μF*
RTRACE
2mΩ
CONTROLLED
*X5R OR X7R
REF/BYP
GND
0.01μF
RTRACE
2mΩ
CONTROLLED
BIAS
MGN
47μF
1.3V/7A
EN
SENSE
IN
OUT
VO2
LT3070
VOUT = 1.0V/5A
2.2μF*
4.7μF*
P.O.L 2
10μF*
PWRGD
NC
VO1
NC
VO0
NC
MARGSEL
NC
MARGTOL
VIOC
1nF
1V
10A
2.2μF
50k
PGND PGND PGND PGND PGND PGND PGND
0.2μH
4.7μF*
POWER PLANE
BSEL
100μF
6.3V
s3
2.2μF*
PWRGD
VO1
NC
1nF
PGOOD
CLKIN
LT3070
NC
SW
MODE
VOUT = 1.0V/5A
OUT
IN
ITH
TRACK
SGND
SENSE
EN
NC
NC
15k
BIAS
SGND
0.1μF
*X5R OR X7R
REF/BYP
GND
0.01μF
3070 F08
NOTE: LTC3415 SWITCHER 2MHz INTERNAL OSCILLATOR
Figure 8. 1V, 10A Point-of-Load Current Sharing Regulators
3070p
21
LT3070
TYPICAL APPLICATIONS
50k
PWRGD
2.2μF
VOUT
1V
P.O.L. 1
BIAS
47μF
IN
SENSE
EN
OUT
2.2μF*
4.7μF*
10μF*
RTRACE
2mΩ
CONTROLLED
VO2 LT3070 (1)
NC
NC
VO0
NC
MARGSEL
NC
MARGTOL
VIOC
1nF
VBIAS
3.3V
10μF
10μF
VBUCK1 = 1.3V/8A
LTM4616
VBUCK2 = 2.1V/8A
VOUT2
VIN2
MGN2
SVIN2
FB2
RUN2
ITH2
PLLLPF2
ITHM2
MODE2
BSEL2
PHMODE2
PGOOD2
TRACK2
SW2 SGND1 GND1 SGND2 GND2
RFB2
3.96k
POWER PLANE
0.01μF
47μF
IN
SENSE
VOUT
1V
10μF* P.O.L. 2
EN
OUT
2.2μF*
4.7μF*
VO2 LT3070 (2)
TBD
100μF
6.3V
s3
1V
10A
RTRACE
2mΩ
CONTROLLED
BIAS
100μF
6.3V
s3
RFB1
8.5k
REF/BYP
GND
2.2μF
50k
SW1 CLKIN1 CLKOUT1 CLKIN2 CLKOUT2
VIN1
VOUT1
SVIN1
MGN1
RUN1
FB1
PLLLPF1
ITH1
MODE1
ITHM1
PHMODE1
BSEL1
TRACK1
PGOOD1
*X5R OR X7R
PWRGD
VO1
NC
VO1
NC
VO0
NC
MARGSEL
NC
MARGTOL
VIOC
TBD
*X5R OR X7R
PWRGD
REF/BYP
GND
0.01μF
TBD
2.2μF
50k
BIAS
47μF
IN
SENSE
EN
OUT
2.2μF*
4.7μF*
VOUT
1.8V
5A
10μF*
VO2 LT3070 (3)
NOTE:
THE TWO LTM4616 MODULE CHANNELS ARE
INDEPENDENTLY CONTROLLED BY THE VIOC
CONTROLS FROM THE LINEAR REGULATORS
NC
VO1
NC
VO0
NC
MARGSEL
NC
MARGTOL
VIOC
TBD
TBD
*X5R OR X7R
PWRGD
REF/BYP
GND
0.01μF
TBD
2.2μF
BIAS
SENSE
IN
47μF
OUT
EN
NC
NC
2.2μF*
4.7μF*
VOUT
1.5V
10μF* 2.5A
VO2 LT3070 (4)
*X5R OR X7R
PWRGD
VO1
VO0
NC
MARGSEL
NC
MARGTOL
VIOC
1nF
REF/BYP
GND
0.01μF
3070 F09
Figure 9. Triple Output Supply Providing 1V, 10A and 1.8V, 5A and 1.5V, 2.5A
3070p
22
LT3070
PACKAGE DESCRIPTION
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
0.70 p0.05
4.50 p 0.05
3.10 p 0.05
2.50 REF
2.65 p 0.05
3.65 p 0.05
PACKAGE OUTLINE
0.25 p0.05
0.50 BSC
3.50 REF
4.10 p 0.05
5.50 p 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 p 0.10
(2 SIDES)
0.75 p 0.05
R = 0.05
TYP
PIN 1 NOTCH
R = 0.20 OR 0.35
s 45o CHAMFER
2.50 REF
R = 0.115
TYP
27
28
0.40 p 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 p 0.10
(2 SIDES)
3.50 REF
3.65 p 0.10
2.65 p 0.10
(UFD28) QFN 0506 REV B
0.25 p 0.05
0.200 REF
0.50 BSC
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3070p
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LT3070
RELATED PARTS
PART
DESCRIPTION
COMMENTS
LT1761
100mA, Low Noise LDO
300mV Dropout Voltage, Low Noise: 20μVRMS, VIN: 1.8V to 20V,
ThinSOT package
LT1762
150mA, Low Noise LDO
300mV Dropout Voltage, Low Noise: 20μVRMS, VIN: 1.8V to 20V,
MS8 package
LT1763
500mA, Low Noise LDO
300mV Dropout Voltage, Low Noise: 20μVRMS, VIN: 1.8V to 20V,
SO-8 Package
LT1764/A
3A, Fast Transient Response, Low Noise LDO
340mV Dropout Voltage, Low Noise: 40μVRMS, VIN: 2.7V to 20V,
TO-220 and DD Packages “A” Version Stable Also with Ceramic Caps
LTC®1844
150mA, Very Low Dropout LDO
80mV Dropout Voltage, Low Noise <30μVRMS, VIN: 1.6V to 6.5V,
Stable with 1μF Output Capacitors, ThinSOT Package
LT1962
300mA, Low Noise LDO
270mV Dropout Voltage, Low Noise: 20μVRMS, VIN: 1.8V to 20V,
MS8 Package
LT1963/A
1.5A Low Noise, Fast Transient Response LDO
340mV Dropout Voltage, Low Noise: 40μVRMS, VIN: 2.5V to 20V,
“A” Version Stable with Ceramic Caps, TO-220, DD, SOT-223 and
SO-8 Packages
LT1965
1.1A, Low Noise, Low Dropout Linear Regulator
290mV Dropout Voltage, Low Noise: 40μVRMS, VIN: 1.8V to 20V,
VOUT : 1.2V to 19.5V, Stable with Ceramic Caps, TO-220, DD-Pak,
MSOP and 3mm × 3mm DFN Packages
LT3020
100mA, Low Voltage VLDO™ Linear Regulator
VIN: 0.9V to 10V, VOUT : 0.2V to 5V (Min), VDO = 0.15V, IQ = 120μA,
Noise: <250μVRMS(P-P), Stable with 2.2μF Ceramic Capacitors,
DFN-8, MS8 Packages
LT3021
500mA, Low Voltage, Very Low Dropout VLDO
Linear Regulator
VIN: 0.9V to 10V, Dropout Voltage = 160mV (Typ), Adjustable Output
(VREF = VOUT(MIN) = 200mV), Fixed Output Voltages: 1.2V, 1.5V, 1.8V,
Stable with Low ESR, Ceramic Output Capacitors 16-Pin DFN
(5mm × 5mm) and 8-Lead SO Packages
LT3080/LT3080-1
1.1A, Parallelable, Low Noise, Low Dropout Linear Regulator 300mV Dropout Voltage (2-Supply Operation), Low Noise: 40μVRMS,
VIN: 1.2V to 36V, VOUT : 0V to 35.7V, Current-Based Reference with
1 Resistor VOUT Set; Directly Parallelable (No Op Amp Required),
Stable with Ceramic Caps, TO-220, SOT-223, MSOP-8 and 3mm
× 3mm DFN-8 Packages; LT3080-1 has Integrated Internal Ballast
Resistor
LT3085
500mA, Parallelable, Low Noise, Low Dropout
Linear Regulator
275mV Dropout Voltage (2-Supply Operation), Low Noise: 40μVRMS,
VIN: 1.2V to 36V, VOUT : 0V to 35.7V, Current-Based Reference with
1 Resistor VOUT Set; Directly Parallelable (No Op Amp Required),
Stable with Ceramic Caps, MSOP-8 and 2mm × 3mm DFN-6
Packages
LTC3025
300mA Micropower VLDO Linear Regulator
VIN: 0.9V to 5.5V, Dropout Voltage: 45mV, Low Noise: 80μVRMS, Low
IQ: 54μA, 2mm × 2mm 6-Lead DFN Package
LTC3025-1/
LTC3025-2
500mA Micropower VLDO Linear Regulator
in 2mm × 2mm DFN
VIN = 0.9V to 5.5V, Dropout Voltage: 75mV, Low Noise 80μVRMS,
Low IQ: 54μA, Fixed Output: 1.2V (LTC3025-2); Adjustable Output
Range: 0.4V to 3.6V (LTC3025-1) 2mm × 2mm 6-Lead DFN Package
LTC3026
1.5A, Low Input Voltage VLDO Regulator
VIN: 1.14V to 3.5V (Boost Enabled), 1.14V to 5.5V (with External
5V), VDO = 0.1V, IQ = 950μA, Stable with 10μF Ceramic Capacitors,
10-Lead MSOP and DFN-10 Packages
LTC3035
300mA VLDO Linear Regulator with Charge Pump
VIN: 1.7V to 5.5V, VOUT : 0.4V to 3.6V, Dropout Voltage: 45mV,
IQ = 100μA, 3mm × 2mm DFN-8 Bias Generator
VLDO is a trademark of Linear Technology Corporation.
3070p
24 Linear Technology Corporation
LT 0709 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2009
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