Intersil CDP1824 32-word x 8-bit static ram Datasheet

CDP1824,
CDP1824C
32-Word x 8-Bit Static RAM
March 1997
Features
Description
• Fast Access Time
- VDD = 5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710ns
- VDD = 10V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320ns
The CDP1824 and CDP1824C are 32-word x 8-bit fully static
CMOS random-access memories for use in CDP-1800
series microprocessor systems. These parts are compatible
with the CDP1802 microprocessor and will interface directly
without additional components.
• No Precharge or Clock Required
The CDP1824 is fully decoded and does not require a precharge or clocking signal for proper operation. It has
common input and output and is operated from a single
voltage supply. The MRD signal (output disable control)
enables the three-state output drivers, and overrides the
MWR signal. A CS input is provided for memory expansion.
The CDP1824C is functionally identical to the CDP1824.
The CDP1824 has an operating range of 4V to 10.5V, and
the CDP1824C has an operating voltage range of 4V to
6.5V. The CDP1824 and CDP1824C are supplied in 18 lead
hermetic dual-in-line ceramic packages (D suffix), and in 18
lead dual-in-line plastic packages (E suffix).
Ordering Information
5V
10V
CDP1824CE
CDP1824E
CDP1824CEX
CDP1824EX
CDP1824CD
CDP1824D
PACKAGE
TEMPERATURE RANGE
-40oC to +85oC
PDIP
PKG. NO.
E18.3
Burn-In
E18.3
-40oC to +85oC
SBDIP
D18.3
Pinout
CDP1824, CDP1824C (PDIP, SBDIP)
TOP VIEW
OPERATIONAL MODES
FUNCTION
MA4
1
18 VDD
MA3
2
17 MWR
MA2
3
16 MRD
MA1
4
15 CS
MA0
5
BUS 7
BUS 6
CS
MRD MWR
DATA PINS STATUS
READ
0
0
X
Output: High/Low Dependent
on Data
WRITE
0
1
0
Input: Output Disabled
Not
Selected
1
X
X
14 BUS 0
Output Disabled:
High-Impedance State
6
13 BUS 1
Standby
0
1
1
7
12 BUS 2
Output Disabled:
High-Impedance State
BUS 5
8
11 BUS 3
Logic 1 = High
Logic 0 = Low X = Don’t Care
VSS
9
10 BUS 4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-37
File Number
1103.2
CDP1824, CDP1824C
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage Range, (VDD)
(All Voltages Referenced to VSS Terminal)
CDP1824 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1824C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range (TA)
Package Type D . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
Thermal Resistance (Typical)
θJA (oC/W) θJC (oC/W)
SBDIP Package . . . . . . . . . . . . . . . . . .
75
20
PDIP Package . . . . . . . . . . . . . . . . . . .
75
N/A
Storage Temperature Range (TSTG). . . . . . . . . . . .-65oC to +150oC
Lead Temperature (During Soldering)
At distance 1/16 ±1/32 In. (1.59 ± 0.79mm)
from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
Recommended Operating Conditions
At TA = Full Package Temperature Range.For maximum reliability, operating conditions
should be selected so that operation is always within the following ranges:
CONDITION
LIMITS
CDP1824D
CDP1824CD
VDD (V)
MIN
MAX
MIN
MAX
UNITS
Supply Voltage Range
-
4
10.5
4
6.5
V
Recommended Input Voltage Range
-
VSS
VDD
VSS
VDD
V
Input Signal Rise or Fall Time (Note 1)
5
-
5
-
5
µs
tR, tF
10
-
2
-
-
µs
PARAMETER
NOTE:
1. Input signal rise or fall times longer than these maxima can cause loss of stored data in either the selected or deselected mode.
Static Electrical Specifications
At TA = -40oC to +85oC, Except as Noted:
CONDITIONS
LIMITS
CDP1824
CDP1824C
SYMBOL
VO
(V)
VIN
(V)
VDD
(V)
MIN
(NOTE 1)
TYP
MAX
MIN
(NOTE 1)
TYP
MAX
UNITS
Quiescent Device
Current
IDD
-
-
5
-
25
50
-
100
200
µA
-
-
10
-
250
500
-
-
-
µA
Output Low (Sink)
Current
IOL
0.4
0, 5
5
1.8
2.2
-
1.8
2.2
-
mA
0.5
0, 10
10
3.6
4.5
-
-
-
-
mA
Output High (Source)
Current
IOH
4.6
0, 5
5
-0.9
-1.1
-
-0.9
-1.1
-
mA
9.5
0, 10
10
-1.8
-2.2
-
-
-
-
mA
Output Voltage
Low-Level
VOL
-
0, 5
5
-
0
0.1
-
0
0.1
V
-
0, 10
10
-
0
0.1
-
-
-
V
Output Voltage
High-Level
VOH
-
0, 5
5
4.9
5
-
4.9
5
-
V
-
0, 10
10
9.9
10
-
-
-
-
V
Input Low Voltage
VIL
0.5, 4.5
-
5
-
-
1.5
-
-
1.5
V
1.9
-
10
-
-
3
-
-
-
V
0.5, 9.5
-
5
3.5
-
-
3.5
-
-
V
1.9
-
10
7
-
-
-
-
-
V
Any
Input
0, 5
5
-
± 0.1
±1
-
± 0.1
±1
µA
0, 10
10
-
± 0.1
±1
-
-
-
µA
-
0, 5
5
-
4
8
-
4
8
mA
-
0, 10
10
-
8
16
-
-
-
mA
PARAMETER
Input High Voltage
Input Leakage Current
Operating Current
(Note 2)
VIH
IIN
IDD1
6-38
CDP1824, CDP1824C
Static Electrical Specifications
At TA = -40oC to +85oC, Except as Noted: (Continued)
CONDITIONS
LIMITS
CDP1824
CDP1824C
SYMBOL
VO
(V)
VIN
(V)
VDD
(V)
MIN
(NOTE 1)
TYP
MAX
MIN
(NOTE 1)
TYP
MAX
UNITS
Three-State Output
Leakage Current
IOUT
0, 5
0, 5
5
-
± 0.2
±2.0
-
± 0.2
±2
µA
0, 10
0, 10
10
-
± 0.2
±2.0
-
-
-
µA
Input Capacitance
CIN
-
-
-
-
5
7.5
-
5
7.5
pF
COUT
-
-
-
-
10
15
-
10
15
pF
PARAMETER
Output Capacitance
NOTES:
1. Typical values are for TA = +25oC and nominal VDD.
2. Outputs open circuited; Cycle time = 1µs.
Dynamic Electrical Specifications
at TA = -40oC to +85oC, VDD ±5%, Input tR, tF = 10ns, CL = 50pF, RL = 200kΩ; See Figure 1
TEST
CONDITIONS
PARAMETER
LIMITS
CDP1824D, CDP1824E
(NOTE 1) (NOTE 2)
MIN
TYP
MAX
CDP1824CD, CDP1824CE
(NOTE 1) (NOTE 2)
MIN
TYP
SYMBOL
VDD (V)
MAX
UNITS
Access Time From
Address Change
tAA
5
-
400
710
-
400
710
ns
10
-
200
320
-
-
-
ns
Access Time From
Chip Select
tDOA
5
-
300
710
-
300
710
ns
10
-
150
320
-
-
-
ns
Output Active From MRD
tAM
5
-
300
710
-
300
710
ns
10
-
150
320
-
-
-
ns
READ OPERATION
NOTES:
1. Time required by a limit device to allow for the indicated function.
2. Time required by a typical device to allow for the indicated function. Typical values are for TA = +25oC and nominal VDD.
MRD
tAM
(NOTE 1)
tAA
MA
CS
(NOTE 1)
tDOA
DATA OUT
HIGH IMPEDANCE
NOTES:
1. Minimum timing for valid data output longer times will initiate an earlier, but invalid output.
FIGURE 1. READ CYCLE TIMING DIAGRAMS
6-39
CDP1824, CDP1824C
Dynamic Electrical Specifications
at TA = -40oC to +85oC, VDD ±5%, Input tR, tF = 10ns, CL = 50pF, RL = 200kΩ; See Figure 2
TEST
CONDITIONS
PARAMETER
LIMITS
CDP1824D, CDP1824E
(NOTE 1) (NOTE 2)
MIN
TYP
CDP1824CD, CDP1824CE
(NOTE 1) (NOTE 2)
MIN
TYP
SYMBOL
VDD (V)
MAX
MAX
UNITS
tWRW
5
390
200
-
390
200
-
ns
10
180
150
-
-
-
-
ns
5
390
100
-
390
100
-
ns
10
180
50
-
-
-
-
ns
5
70
40
-
70
40
-
ns
10
35
20
-
-
-
-
ns
5
425
210
-
425
210
-
ns
10
215
110
-
-
-
-
ns
5
640
500
-
640
500
-
ns
10
390
300
-
-
-
-
ns
WRITE OPERATION
Write Pulse Width
Data Setup Time
Data Hold Time
Chip Select Setup Time
Address Setup Time
tDS
tDH
tCS
tAS
NOTES:
1. Time required by a limit device to allow for the indicated function.
2. Time required by a typical device to allow for the indicated function. Typical values are for TA = +25oC and nominal VDD.
MA
tAS
CS
tCS
tWRW
MWR
tDS
tDH
BUS
FIGURE 2. WRITE CYCLE TIMING DIAGRAM
DATA RETENTION
MODE
0.95 VDD
VDD
0.95 VDD
VDR
tCDR
tF
(NOTE 1)
VIH
CS V
IL
tR
(NOTE 1)
tRC
VIH
VIL
NOTE: tR, tF > 1µs.
FIGURE 3. LOW VDD DATA RETENTION WAVEFORMS AND TIMING DIAGRAM
6-40
CDP1824, CDP1824C
Data Retention Specifications
at TA = -40oC to +85oC; See Figure 3
TEST CONDITIONS
LIMITS
CDP1824
CDP1824C
SYMBOL
VDD
(V)
MIN
MAX
MIN
MAX
UNITS
Data Retention Voltage
VDR
-
2.5
-
2.5
-
V
Data Retention Quiescent Current
IDD
VDR = 2.5V
-
-
10
-
40
µA
tCDR
VDR = 2.5V
5
600
-
600
-
ns
10
300
-
-
-
ns
5
600
-
600
-
ns
10
300
-
-
-
ns
PARAMETER
Chip Deselect to Data Retention
Time
Recovery to Normal Operation Time
tRC
VDR = 2.5V
MA4
MA3
MA2
MA1
MA0
2
3
4
5
1
32 X 8-BIT
ARRAY
ADDRESS
DECODER
SENSE
AMPL
MWR
16
17
MRD
I/O BUFFERS
CS
VDD = 18
15
6
VSS = 9
7
8
10
11
12
13
14
BUS BUS BUS BUS BUS BUS BUS BUS
7
6
5
4
3
2
1
0
FIGURE 4. FUNCTIONAL DIAGRAM
CPU/ROM SYSTEM
RAM SYSTEM
ADDRESS
MA0-MA7
MA0-MA7
MA0-MA7
TPA
MRD
TPA
MRD
MRD
MWR
ROM
CPU
CDP1802
CE0
BUS0-BUS7
BUS0-BUS7
MWR
RAM
CDP1824
CS
BUS0-BUS7
DATA
FIGURE 5. CDP1824 (128 X 8) MINIMUM SYSTEM (128 X 8)
6-41
CDP1824, CDP1824C
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
6-42
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
Similar pages