Cypress CY28409ZC Clock synthesizer with differential src and cpu output Datasheet

CY28409
Clock Synthesizer with Differential SRC and
CPU Outputs
Features
• Three differential CPU clock pairs
• One differential SRC clock
• Supports Intel® Pentium® 4-type CPUs
• I2C support with readback capabilities
• Selectable CPU frequencies
• 3.3V power supply
• Ideal Lexmark Spread Spectrum profile for maximum
EMI reduction
• Ten copies of PCI clocks
• 56-pin SSOP and TSSOP packages
• Five copies of 3V66 with one optional VCH
• Two copies 48-MHz USB clocks
CPU
SRC
3V66
PCI
REF
48M
x3
x1
x5
x 10
x2
x2
[1]
Block Diagram
CPU_STP#
PCI_STP#
FS_[A:B]
VTT_PWRGD#
XTAL
OSC
PLL1
VDD_REF
REF0:1
PLL Ref Freq
VDD_CPU
CPUT[0:2], CPUC[0:2]
Divider
Network
VDD_SRC
SRCT, SRCC
~
XIN
XOUT
Pin Configuration
IREF
VDD_3V66
3V66_[0:3]
2
PCI[0:6]
3V66_4/VCH
VDD_48MHz
DOT_48
PD#
USB_48
SDATA
SCLK
I2C
Logic
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CY28409
VDD_PCI
PCIF[0:2]
PLL2
REF_0
REF_1
VDD_REF
XIN
XOUT
VSS_REF
PCIF0
PCIF1
PCIF2
VDD_PCI
VSS_PCI
PCI0
PCI1
PCI2
PCI3
VDD_PCI
VSS_PCI
PCI4
PCI5
PCI6
PD#
3V66_0
3V66_1
VDD_3V66
VSS_3V66
3V66_2
3V66_3
SCLK
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
FS_B
VDD_A
VSS_A
VSS_IREF
IREF
FS_A
CPU_STP#
PCI_STP#
VDD_CPU
CPUT2
CPUC2
VSS_CPU
CPUT1
CPUC1
VDD_CPU
CPUT0
CPUC0
VSS_SRC
SRCT
SRCC
VDD_SRC
VTT_PWRGD#
VDD_48
VSS_48
DOT_48
USB_48
SDATA
3V66_4/VCH
56 SSOP/TSSOP
Note:
1. Signals marked with [*] and [**] have internal pull-up and pull-down resistors, respectively.
Cypress Semiconductor Corporation
Document #: 38-07445 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 2, 2006
CY28409
Pin Description
Pin No.
Name
1, 2
REF(0:1)
4
XIN
Type
Description
O, SE Reference Clock. 3.3V 14.318-MHz clock output.
I
Crystal Connection or External Reference Frequency Input. This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an external
reference frequency input.
5
XOUT
O, SE Crystal Connection. Connection for an external 14.318-MHz crystal output.
41,44,47
CPUT(0:2)
O, DIF CPU Clock Output. Differential CPU clock outputs. See Table 1 for frequency configuration.
40,43,46
CPUC(0:2)
O, DIF CPU Clock Output. Differential CPU clock outputs. See Table 1 for frequency configuration.
38, 37
SRCT, SRCC
O, DIF Differential serial reference clock.
22,23,26,27
3V66(0:3)
O, SE 66-MHz Clock Output. 3.3V 66-MHz clock from internal VCO.
29
3V66_4VCH
O, SE 48-/66-MHz Clock Output. 3.3V selectable through SMBus to be 66 or 48 MHz.
7,8,9
PCIF(0:2)
O, SE Free-running PCI Output. 33-MHz clocks divided down from 3V66.
12,13,14,
15,18,19,20
PCI(0:6)
O, SE PCI Clock Output. 33-MHz clocks divided down from 3V66.
31,
USB_48
O, SE Fixed 48-MHz clock output.
O, SE Fixed 48-MHz clock output.
32
DOT_48
51,56
FS_A, FS_B
I
3.3V LVTTL input for CPU frequency selection.
52
IREF
I
Current Reference. A precision resistor is attached to this pin which is connected to
the internal current reference.
21
PD#
I, PU
3.3V LVTTL input for Power-Down# active LOW.
50
CPU_STP#
I, PU
3.3V LVTTL input for CPU_STP# active LOW.
49
PCI_STP#
I, PU
3.3V LVTTL input for PCI_STP# active LOW.
35
VTT_PWRGD#
30
SDATA
I
I/O
3.3V LVTTL input is a level sensitive strobe used to latch the FS_A and FS_B
inputs (active LOW).
SMBus-compatible SDATA.
28
SCLK
I
SMBus-compatible SCLOCK.
53
VSS_IREF
GND
Ground for current reference.
55
VDD_A
PWR
3.3V power supply for PLL.
54
VSS_A
GND
Ground for PLL.
42,48
VDD_CPU
PWR
3.3V power supply for outputs.
45
VSS_CPU
GND
Ground for outputs.
36
VDD_SRC
PWR
3.3V power supply for outputs.
39
VSS_SRC
GND
Ground for outputs.
34
VDD_48
PWR
3.3V power supply for outputs.
33
VSS_48
GND
Ground for outputs.
10,16
VDD_PCI
PWR
3.3V power supply for outputs.
11,17
VSS_PCI
GND
Ground for outputs.
24
VDD_3V66
PWR
3.3V power supply for outputs.
25
VSS_3V66
GND
Ground for outputs.
3
VDD_REF
PWR
3.3V power supply for outputs.
6
VSS_REF
GND
Ground for outputs.
Document #: 38-07445 Rev. *D
Page 2 of 17
CY28409
Table 1. Frequency Select Table (FS_A, FS_B)
FS_A
FS_B
CPU
SRC
3V66
PCIF/PCI
REF0
REF1
USB/DOT
0
0
100 MHz
100/200 MHz
66 MHz
33 MHz
14.3 MHz
14.31 MHz
48 MHz
0
MID
REF/N
REF/N
REF/N
REF/N
REF/N
REF/N
REF/N
0
1
200 MHz
100/200 MHz
66 MHz
33 MHz
14.3 MHz
14.31 MHz
48 MHz
1
0
133 MHz
100/200 MHz
66 MHz
33 MHz
14.3 MHz
14.31 MHz
48 MHz
1
MID
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Table 2. Frequency Select Table (FS_A, FS_B) SMBus Bit 5 of Byte 6 = 1
FS_A
FS_B
CPU
SRC
3V66
PCIF/PCI
REF0
REF1
USB/DOT
0
0
200 MHz
100/200 MHz
66 MHz
33 MHz
14.3 MHz
14.31 MHz
48 MHz
0
1
400 MHz
100/200 MHz
66 MHz
33 MHz
14.3 MHz
14.31 MHz
48 MHz
1
0
266 MHz
100/200 MHz
66 MHz
33 MHz
14.3 MHz
14.31 MHz
48 MHz
Frequency Select Pins (FS_A, FS_B)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A and FS_B inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled LOW by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FS_A and FS_B input values. For all logic levels
of FS_A and FS_B except MID, VTT_PWRGD# employs a
one-shot functionality in that once a valid LOW on
VTT_PWRGD# has been sampled LOW, all further
VTT_PWRGD#, FS_A and FS_B transitions will be ignored. In
the case where FS_B is at mid level when VTT_PWRGD# is
sampled LOW, the clock chip will assume “Test Clock Mode.”
Once “Test Clock Mode” has been invoked, all further FS_B
transitions will be ignored and FS_A will asynchronously
select between the Hi-Z and REF/N mode. Exiting test mode
is accomplished by cycling power with FS_B in a HIGH or
LOW state.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 3.
The block write and block read protocol is outlined in Table 4
while Table 5 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Table 3. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Table 4. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
2:8
Description
Start
Slave address – 7 bits
9
Write = 0
10
Acknowledge from slave
11:18
19
Command Code – 8 bits
'00000000' stands for block operation
Acknowledge from slave
Document #: 38-07445 Rev. *D
Block Read Protocol
Bit
1
2:8
Description
Start
Slave address – 7 bits
9
Write = 0
10
Acknowledge from slave
11:18
19
Command Code – 8 bits
'00000000' stands for block operation
Acknowledge from slave
Page 3 of 17
CY28409
Table 4. Block Read and Block Write Protocol (continued)
Block Write Protocol
Bit
20:27
28
29:36
37
38:45
Block Read Protocol
Description
Bit
Byte Count – 8 bits
20
Acknowledge from slave
21:27
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Description
Repeat start
Slave address – 7 bits
28
Read = 1
29
Acknowledge from slave
30:37
38
Byte count from slave – 8 bits
46
Acknowledge from slave
....
......................
....
Data Byte (N–1) – 8 bits
47
....
Acknowledge from slave
48:55
....
Data Byte N – 8 bits
56
Acknowledge from master
....
Acknowledge from slave
....
Data byte N from slave – 8 bits
....
Stop
....
Acknowledge from master
....
Stop
39:46
Acknowledge from master
Data byte from slave – 8 bits
Acknowledge from master
Data byte from slave – 8 bits
Table 5. Byte Read and Byte Write protocol
Byte Write Protocol
Bit
1
2:8
Byte Read Protocol
Description
Bit
Start
1
Slave address – 7 bits
2:8
Description
Start
Slave address – 7 bits
9
Write = 0
9
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
11:18
19
20:27
Command Code – 8 bits
'100xxxxx' stands for byte operation, bits[4:0] of the
command code represents the offset of the byte to
be accessed
11:18
Command Code – 8 bits
'100xxxxx' stands for byte operation, bits[4:0] of
the command code represents the offset of the
byte to be accessed
Acknowledge from slave
19
Acknowledge from slave
Data byte from master – 8 bits
20
Repeat start
28
Acknowledge from slave
29
Stop
21:27
Slave address – 7 bits
28
Read = 1
29
Acknowledge from slave
30:37
Data byte from slave – 8 bits
38
Acknowledge from master
39
Stop
Control Registers
Byte 0:Control Register 0
Bit
@Pup
7
0
Reserved
Name
Reserved, Set = 0
6
1
PCIF
PCI
PCI Drive Strength Override
0 = Force All PCI and PCIF Outputs to Low Drive Strength
1 = Force All PCI and PCIF Outputs to High Drive Strength
5
0
Reserved
Reserved, Set = 0
4
0
Reserved
Reserved, Set = 0
Document #: 38-07445 Rev. *D
Description
Page 4 of 17
CY28409
Byte 0:Control Register 0 (continued)
Bit
@Pup
Name
Description
3
Externally
Selected
PCI_STP#
PCI_STP# reflects the current value of the external PCI_STP# pin.
0 = PCI_STP# pin is LOW.
2
Externally
Selected
CPU_STP#
CPU_STP# reflects the current value of the external CPU_STP# pin.
0 = CPU_STP# pin is LOW.
1
Externally
Selected
FS_B
FS_B reflects the value of the FS_B pin sampled on power-up.
0
Externally
Selected
FS_A
FS_A reflects the value of the FS_A pin sampled on power-up.
Byte 1: Control Register 1
Bit
@Pup
7
0
Name
SRCT, SRCC
Description
Allows control of SRCT/C with assertion of PCI_STP# or SW PCI_STP
0 = Free Running, 1 = Stopped with PCI_STP#
6
1
SRCT, SRCC
SRCT/C Output Enable; 0 = Disabled (Hi-z), 1 = Enabled
5
1
Reserved
Reserved, Set = 1
4
1
Reserved
Reserved, Set = 1
3
1
Reserved
Reserved, Set = 1
2
1
CPUT2, CPUC2
CPUT/C2 Output Enable; 0 = Disabled (Hi-z), 1 = Enabled
1
1
CPUT1, CPUC1
CPUT/C1 Output Enable; 0 = Disabled (Hi-z), 1 = Enabled
0
1
CPUT0, CPUC0
CPUT/C0 Output Enable; 0 = Disabled (Hi-z), 1 = Enabled
Byte 2: Control Register 2
Bit
@Pup
Name
Description
7
0
SRCT, SRCC
SRCT/C Pwrdwn Drive Mode
0 = Driven during power-down, 1 = Three-state during power-down
6
0
SRCT, SRCC
SRCT/C Stop Drive Mode
0 = Driven during PCI_STP, 1 = Three-state during PCI_STP
5
0
CPUT2, CPUC2
CPUT/C2 Pwrdwn Drive Mode
0 = Driven during power-down, 1 = Three-state during power-down
4
0
CPUT1, CPUC1
CPUT/C1 Pwrdwn Drive Mode
0 = Driven during power-down, 1 = Three-state during power-down
3
0
CPUT0, CPUC0
CPUT/C0 Pwrdwn Drive Mode
0 = Driven during power-down, 1 = Three-state during power-down
2
0
CPUT2, CPUC2
CPUT/C2 stop Drive Mode
0 = Driven when stopped, 1 = Three-state when stopped
1
0
CPUT1, CPUC1
CPUT/C1 stop Drive Mode
0 = Driven when stopped, 1 = Three-state when stopped
0
0
CPUT0, CPUC0
CPUT/C0 stop Drive Mode
0 = Driven when stopped, 1 = Three-state when stopped
Byte 3: Control Register 3
Bit
@Pup
Name
7
1
SW PCI STOP
SW PCI_STP Function
0= PCI_STP assert, 1= PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI,PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
6
1
PCI6
PCI6 Output Enable
0 = Disabled, 1 = Enabled
Document #: 38-07445 Rev. *D
Description
Page 5 of 17
CY28409
Byte 3: Control Register 3 (continued)
Bit
@Pup
Name
Description
5
1
PCI5
PCI5 Output Enable
0 = Disabled, 1 = Enabled
4
1
PCI4
PCI4 Output Enable
0 = Disabled, 1 = Enabled
3
1
PCI3
PCI3 Output Enable
0 = Disabled, 1 = Enabled
2
1
PCI2
PCI2 Output Enable
0 = Disabled, 1 = Enabled
1
1
PCI1
PCI1 Output Enable
0 = Disabled, 1 = Enabled
0
1
PCI0
PCI0 Output Enable
0 = Disabled, 1 = Enabled
Byte 4: Control Register 4
Bit
@Pup
Name
Description
7
0
USB_48
USB_48 Drive Strength
0 = High drive strength, 1 = Low drive strength
6
1
USB_48
USB_48 Output Enable
0 = Disabled, 1 = Enabled
5
0
PCIF2
Allow control of PCIF2 with assertion of PCI_STP# or SW PCI_STP
0 = Free Running, 1 = Stopped with PCI_STP#
4
0
PCIF1
Allow control of PCIF1 with assertion of PCI_STP# or SW PCI_STP
0 = Free Running, 1 = Stopped with PCI_STP#
3
0
PCIF0
Allow control of PCIF0 with assertion of PCI_STP# or SW PCI_STP
0 = Free Running, 1 = Stopped with PCI_STP#
2
1
PCIF2
PCIF2 Output Enable
0 = Disabled, 1 = Enabled
1
1
PCIF1
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
0
1
PCIF0
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
Byte 5: Control Register 5
Bit
@Pup
7
1
DOT_48
Name
DOT_48 Output Enable
0 = Disabled, 1 = Enabled
6
1
Reserved
Reserved, Set = 1
5
0
3V66_4/VCH
VCH Select 66-MHz/48-MHz
0 = 3V66 mode, 1 = VCH (48-MHz) mode
4
1
3V66_4/VCH
3V66_4/VCH Output Enable
0 = Disabled, 1 = Enabled
3
1
3V66_3
3V66_3 Output Enable
0 = Disabled, 1 = Enabled
2
1
3V66_2
3V66_2 Output Enable
0 = Disabled, 1 = Enabled
1
1
3V66_1
3V66_1 Output Enable
0 = Disabled, 1 = Enabled
0
1
3V66_0
3V66_0 Output Enable
0 = Disabled, 1 = Enabled
Document #: 38-07445 Rev. *D
Description
Page 6 of 17
CY28409
Byte 6: Control Register 6
Bit
@Pup
Name
Description
7
0
Reserved
Reserved, Set = 0
6
0
Reserved
Reserved, Set = 0
5
0
CPUC0, CPUT0
CPUC1, CPUT1
CPUC2, CPUT2
FS_A & FS_B Operation
0 = Normal, 1 = Test mode
4
0
SRCT, SRCC
SRC Frequency Select
0 = 100 MHz, 1 = 200 MHz
3
0
Reserved
Reserved, Set = 0
2
0
PCIF
PCI
3V66
SRCT,SRCC
CPUT_ITP,CPUC_ITP
Spread Spectrum Enable
0 = Spread Off, 1 = Spread On
1
1
REF_1
REF_1 Output Enable
0 = Disabled, 1 = Enabled
0
1
REF_0
REF_0 Output Enable
0 = Disabled, 1 = Enabled
Byte 7: Vendor ID
Bit
@Pup
Name
Description
7
0
Revision ID Bit 3
Revision ID Bit 3
6
1
Revision ID Bit 2
Revision ID Bit 2
5
0
Revision ID Bit 1
Revision ID Bit 1
4
0
Revision ID Bit 0
Revision ID Bit 0
3
1
Vendor ID Bit 3
Vendor ID Bit 3
2
0
Vendor ID Bit 2
Vendor ID Bit 2
1
0
Vendor ID Bit 1
Vendor ID Bit 1
0
0
Vendor ID Bit 0
Vendor ID Bit 0
Table 6. Crystal Recommendations
Frequency
(Fund)
Cut
Loading Load Cap
Drive
(max.)
Shunt Cap
(max.)
Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
14.31818 MHz
AT
Parallel
0.1 mW
5 pF
0.016 pF
50 ppm
50 ppm
5 ppm
20 pF
Crystal Recommendations
The CY28409 requires a Parallel Resonance Crystal.
Substituting a series resonance crystal will cause the
CY28409 to operate at the wrong frequency and violate the
ppm specification. For most applications there is a 300-ppm
frequency shift between series and parallel crystals due to
incorrect loading.
Figure 1 shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. It’s a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appropriate capacitive loading (CL).
Figure 1. Crystal Capacitive Clarification
Document #: 38-07445 Rev. *D
Page 7 of 17
CY28409
Calculating Load Capacitors
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
Load Capacitance (each side)
Ce = 2 * CL – (Cs + Ci)
Total Capacitance (as seen by the crystal)
1
CLe =
1
1
( Ce1 + Cs1
)
+ Ci1 + Ce2 + Cs2 + Ci2
CL ....................................................Crystal load capacitance
CLe ......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce ..................................................... External trim capacitors
C lo c k C h ip
(C Y 2 8 4 0 9 )
Cs ..............................................Stray capacitance (terraced)
C i2
C i1
P in
3 to 6 p
Ci .......................................................... Internal capacitance
(lead frame, bond wires etc.)
PD# (Power-down) Clarification
X2
X1
C s1
C s2
T ra c e
2 .8 p F
XTAL
Ce1
Ce2
T r im
33pF
Figure 2. Crystal Loading Example
The PD# (Power-down) pin is used to shut off ALL clocks prior
to shutting off power to the device. PD# is an asynchronous
active LOW input. This signal is synchronized internally to the
device powering down the clock synthesizer. PD# is an
asynchronous function for powering up the system. When PD#
is LOW, all clocks are driven to a LOW value and held there
and the VCO and PLLs are also powered down. All clocks are
shut down in a synchronous manner so as not to cause
glitches while changing to the low ‘stopped’ state.
PD# Assertion
When PD# is sampled LOW by two consecutive rising edges
of the CPUC clock then all clock outputs (except CPU) clocks
must be held LOW on their next HIGH-to-LOW transition. CPU
clocks must be held with CPU clock pin driven HIGH with a
value of 2 x Iref and CPUC undriven. Due to the state of
internal logic, stopping and holding the REF clock outputs in
the LOW state may require more than one clock cycle to
complete
PD#
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
3V66, 66MHz
USB, 48MHz
PCI, 33MHz
REF
Figure 3. Power-down Assertion Timing Waveform
Document #: 38-07445 Rev. *D
Page 8 of 17
CY28409
PD# Deassertion
The power-up latency between PD# rising to a valid logic ‘1’
level and the starting of all clocks is less than 1.8 ms.
CPU_STP# Assertion
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable via assertion
of CPU_STP# will be stopped after being sampled by two
rising edges of the internal CPUT clock. The final states of the
stopped CPU signals are CPUT = HIGH and CPUC = LOW.
There is no change to the output drive current values during
the stopped state. The CPUT is driven HIGH with a current
value equal to (Mult 0 ‘select’) x (Iref), and the CPUC signal
will not be driven. Due to the external pull-down circuitry,
CPUC will be LOW during this stopped state.
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal will cause all CPU
outputs that were stopped to resume normal operation in a
synchronous manner. Synchronous manner meaning that no
short or stretched clock pulses will be produce when the clock
resumes. The maximum latency from the deassertion to active
outputs is no more than two CPU clock cycles.
Tstable
<1.8 ms
PD#
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
3V66, 66MHz
USB, 48MHz
PCI, 33MHz
REF
Tdrive_PWRDN#
<300 µs, >200 mV
Figure 4. Power-down Deassertion Timing Waveform
CPU_STP#
CPUT
CPUC
Figure 5. CPU_STP# Assertion Waveform
CPU_STP#
CPUT
CPUC
CPU Internal
Tdrive_CPU_STP#, 10 ns > 200 mV
Figure 6. CPU_STP# Deassertion Waveform
Document #: 38-07445 Rev. *D
Page 9 of 17
CY28409
PCI_STP# Assertion[2]
PCI_STP# Deassertion
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (tSU). (See
Figure 7.) The PCIF clocks will not be affected by this pin if
their corresponding control bit in the SMBus register is set to
allow them to be free-running.
The deassertion of the PCI_STP# signal will cause all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods after PCI_STP# transitions to a high level.
Tsu
PCI_STP#
PCI_F
PCI
SRC 100MHz
Figure 7. PCI_STP# Assertion Waveform
Tsu
Tdrive_SRC
PCI_STP#
PCI_F
PCI
SRC 100MHz
Figure 8. PCI_STP# Deassertion Waveform
Note:
2. The PCI STOP function is controlled by two inputs. One is the device PCI_STP# pin number 34 and the other is SMBus byte 0 bit 3. These two inputs are logically
ANDed. If either the external pin or the internal SMBus register bit is set low then the stoppable PCI clocks will be stopped in a logic low state. Reading SMBus
Byte 0 Bit 3 will return a 0 value if either of these control bits are set LOW thereby indicating the device’s stoppable PCI clocks are not running.
Document #: 38-07445 Rev. *D
Page 10 of 17
CY28409
FS_A, FS_B
VTT_PWRGD#
PWRGD_VRM
0.2-0.3 ms
Delay
VDD Clock Gen
Clock State
Clock Outputs
Clock VCO
State 0
Wait for
VTT_PWRGD#
State 1
Device is not affected,
VTT_PWRGD# is ignored
Sample Sels
State 2
Off
State 3
On
On
Off
Figure 9. VTT_PWRGD# Timing Diagram
S2
S1
Delay
>0.25 ms
VTT_PWRGD# = Low
Sample
Inputs straps
VDDA = 2.0V
Wait for <1.8 ms
S0
Power Off
S3
VDDA = off
Normal
Operation
Enable Outputs
VTT_PWRGD# = toggle
Figure 10. Clock Generator Power-up/Run State Diagram
Document #: 38-07445 Rev. *D
Page 11 of 17
CY28409
Absolute Maximum Conditions
Parameter
VDD
VDD_A
VIN
TS
TA
TJ
ØJC
ØJA
ESDHBM
UL–94
MSL
Description
Core Supply Voltage
Analog Supply Voltage
Input Voltage
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Flammability Rating
Moisture Sensitivity Level
Condition
Relative to VSS
Non-functional
Functional
Functional
Mil-Spec 883E Method 1012.1
JEDEC (JESD 51)
MIL-STD-883, Method 3015
@ 1/8 in.
Min.
–0.5
–0.5
–0.5
–65
0
–
–
–
2000
Max.
4.6
4.6
VDD + 0.5
150
70
150
15
45
–
V–0
1
Unit
V
V
VDC
°C
°C
°C
°C/W
°C/W
V
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter
VDD_A,
VDD_REF,
VDD_PCI,
VDD_3V66,
VDD_48,
VDD_CPU
VILI2C
VIHI2C
VIL
VIH
IIL
IIH
VOL
VOH
IOZ
IDD
CIN
COUT
LIN
VXIH
VXIL
IPD3.3V
Description
3.3V Operating Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Leakage Current
Input High Leakage Current
Output Low Voltage
Output High Voltage
High-impedance Output Current
Dynamic Supply Current
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
Xin High Voltage
Xin Low Voltage
Power-down Supply Current
Condition
3.3 ± 5%
Min.
3.135
Max.
3.465
SDATA, SCLK
SDATA, SCLK
–
1.0
2.2
–
VSS – 0.5
0.8
2.0
VDD + 0.5
except internal pull-ups resistors, 0 < VIN < VDD
–5
except internal pull-down resistors, 0 < VIN < VDD
5
IOL = 1 mA
–
0.4
IOH = –1 mA
2.4
–
–10
10
All outputs loaded per Table 9 and Figure 11
–
350
2
5
3
6
–
7
0.7VDD
VDD
0
0.3VDD
PD# Asserted
–
1
Unit
V
V
V
V
V
µA
µA
V
V
µA
mA
pF
pF
nH
V
V
mA
AC Electrical Specifications
Parameter
Description
Crystal
TDC
XIN Duty Cycle
TPERIOD
XIN Period
TR / TF
TCCJ
LACC
XIN Rise and Fall Times
XIN Cycle to Cycle Jitter
Long-term Accuracy
Document #: 38-07445 Rev. *D
Condition
Min.
Max.
Unit
The device will operate reliably with input duty
cycles up to 30/70 but the REF clock duty cycle
will not be within specification
When XIN is driven from an external clock
source
Measured between 0.3VDD and 0.7VDD
As an average over 1-µs duration
Over 150 ms
47.5
52.5
%
69.841
71.0
ns
–
–
10.0
500
300
ns
ps
ppm
Page 12 of 17
CY28409
AC Electrical Specifications (continued)
Parameter
Description
CPU at 0.7V
TDC
CPUT and CPUC Duty Cycle
TPERIOD
100-MHz CPUT and CPUC Period
133-MHz CPUT and CPUC Period
TPERIOD
200-MHz CPUT and CPUC Period
TPERIOD
Any CPUT/C to CPUT/C Clock Skew
TSKEW
TCCJ
CPUT/C Cycle to Cycle Jitter
CPUT and CPUC Rise and Fall Times
TR / TF
Rise/Fall Matching
TRFM
∆TR
Rise Time Variation
Fall Time Variation
∆TF
Voltage High
VHIGH
Voltage Low
VLOW
Crossing Point Voltage at 0.7V Swing
VOX
Maximum Overshoot Voltage
VOVS
VUDS
Minimum Undershoot Voltage
Ring Back Voltage
VRB
SRC
TDC
SRCT and SRCC Duty Cycle
TPERIOD
100 MHz SRCT and SRCC Period
200 MHz SRCT and SRCC Period
TPERIOD
SRCT/C Cycle to Cycle Jitter
TCCJ
LACC
SRCT/C Long Term Accuracy
SRCT and SRCC Rise and Fall Times
TR / TF
Rise/Fall Matching
TRFM
∆TR
Rise Time Variation
Fall Time Variation
∆TF
Voltage High
VHIGH
VLOW
Voltage Low
Crossing Point Voltage at 0.7V Swing
VOX
Maximum Overshoot Voltage
VOVS
Minimum Undershoot Voltage
VUDS
Ring Back Voltage
VRB
3V66
TDC
3V66 Duty Cycle
Spread Disabled 3V66 Period
TPERIOD
Spread Enabled 3V66 Period
TPERIOD
3V66 High Time
THIGH
3V66 Low Time
TLOW
3V66 Rise and Fall Times
TR / TF
Any 3V66 to Any 3V66 Clock Skew
TSKEW
3V66 Cycle to Cycle Jitter
TCCJ
PCI/PCIF
TDC
PCI Duty Cycle
Spread Disabled PCIF/PCI Period
TPERIOD
Spread Enabled PCIF/PCI Period
TPERIOD
THIGH
PCIF and PCI high time
PCIF and PCI low time
TLOW
Document #: 38-07445 Rev. *D
Condition
Min.
Max.
Unit
Measured at crossing point VOX
45
55
%
Measured at crossing point VOX
9.9970
10.003
ns
Measured at crossing point VOX
7.4978
7.5023
ns
Measured at crossing point VOX
4.9985
5.0015
ns
Measured at crossing point VOX
–
100
ps
Measured at crossing point VOX
–
125
ps
Measured from VOL = 0.175 to VOH = 0.525V
175
700
ps
Determined as a fraction of 2*(TR – TF)/(TR + TF)
–
20
%
–
125
ps
–
125
ps
Math averages Figure 11
660
850
mV
Math averages Figure 11
–150
–
mV
250
550
mV
–
VHIGH + 0.3 V
–0.3
–
V
See Figure 11. Measure SE
–
0.2
V
Measured at crossing point VOX
45
55
Measured at crossing point VOX
9.9970
10.003
Measured at crossing point VOX
4.9985
5.0015
Measured at crossing point VOX
–
125
Measured at crossing point VOX
–
300
Measured from VOL = 0.175 to VOH = 0.525V
175
700
Determined as a fraction of 2*(TR – TF)/(TR + TF)
–
20
–
125
–
125
Math averages Figure 11
660
850
Math averages Figure 11
–150
–
250
550
–
VHIGH + 0.3
–0.3
–
See Figure 11. Measure SE
–
0.2
%
ns
ns
ps
ppm
ps
%
ps
ps
mV
mV
mV
V
V
V
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
Measurement at 2.0V
Measurement at 0.8V
Measured between 0.8V and 2.0V
Measurement at 1.5V
Measurement at 1.5V
45
14.9955
14.9955
4.9500
4.5500
0.5
–
–
55
15.0045
15.0799
–
–
2.0
250
250
%
ns
ns
ns
ns
ns
ps
ps
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
Measurement at 2.0V
Measurement at 0.8V
45
29.9910
29.9910
12.0
12.0
55
30.0009
30.1598
–
–
%
ns
ns
ns
ns
Page 13 of 17
CY28409
AC Electrical Specifications (continued)
Parameter
Description
TR / TF
PCIF and PCI rise and fall times
TSKEW
Any PCI clock to Any PCI clock Skew
PCIF and PCI Cycle to Cycle Jitter
TCCJ
DOT
TDC
Duty Cycle
Period
TPERIOD
TSKEW
Any 48-MHz to 48-MHz Clock Skew
USB high time
THIGH
USB low time
TLOW
TR / TF
Rise and Fall Times
Cycle to Cycle Jitter
TCCJ
USB
TDC
Duty Cycle
TPERIOD
Period
Any 48-MHz to 48-MHz Clock Skew
TSKEW
USB high time
THIGH
TLOW
USB low time
Rise and Fall Times
TR / TF
Cycle to Cycle Jitter
TCCJ
REF
TDC
REF Duty Cycle
REF Period
TPERIOD
Any REF to REF Clock Skew
TSKEW
TR / TF
REF Rise and Fall Times
REF Cycle to Cycle Jitter
TCCJ
ENABLE/DISABLE and SET-UP
TSTABLE
Clock Stabilization from Power-up
TSS
Stopclock Set-up Time
Stopclock Hold Time
TSH
Condition
Measured between 0.8V and 2.0V
Measurement at 1.5V
Measurement at 1.5V
Min.
0.5
–
–
Max.
2.0
500
250
Unit
ns
ps
ps
Measurement at 1.5V
Measurement at 1.5V
Measured at crossing point VOX
Measurement at 2.0V
Measurement at 0.8V
Measured between 0.8V and 2.0V
Measurement at 1.5V
45
20.8271
–
8.994
8.794
0.5
–
55
20.8396
500
10.486
10.386
1.0
350
%
ns
ps
ns
ns
ns
ps
Measurement at 1.5V
Measurement at 1.5V
Measured at crossing point VOX
Measurement at 2.0V
Measurement at 0.8V
Measured between 0.8V and 2.0V
Measurement at 1.5V
45
20.8271
–
8.094
7.694
1.0
–
55
20.8396
500
10.036
9.836
2.0
350
%
ns
ps
ns
ns
ns
ps
Measurement at 1.5V
Measurement at 1.5V
Measured at crossing point VOX
Measured between 0.8V and 2.0V
Measurement at 1.5V
45
69.827
–
0.5
–
55
69.855
500
2.0
1000
%
ns
ps
ns
ps
–
10.0
0
1.8
–
–
ms
ns
ns
Table 7. Group Timing Relationship and Tolerances
Offset
Group
Conditions
Min.
Max.
3V66 to PCI
3V66 Leads PCI
1.5 ns
3.5 ns
Table 8. USB to DOT Phase Offset
Parameter
Typical
Value
Tolerance
DOT Skew
0°
0.0 ns
1000 ps
USB Skew
180°
0.0 ns
1000 ps
VCH SKew
0°
0.0 ns
1000 ps
Table 9. Maximum Lumped Capacitive Output Loads
Clock
PCI Clocks
3V66 Clocks
USB Clock
DOT Clock
REF Clock
Max Load
30
30
20
10
30
Document #: 38-07445 Rev. *D
Unit
pF
pF
pF
pF
pF
Page 14 of 17
CY28409
Test and Measurement Set-up
For Differential CPU and SRC Output Signals
The following diagram shows lumped test load configurations
for the differential Host Clock Outputs.
CPUT
CPUC
M e a s u re m e n t
P o in t
T PCB
33Ω
4 9 .9 Ω
33Ω
2 pF
M e a s u re m e n t
P o in t
T PCB
4 9 .9 Ω
IR E F
2 pF
475Ω
Figure 11. 0.7V Load Configuration
O u tp u t u n d e r T e s t
P ro b e
Load Cap
3 .3 V s ig n a l s
tD C
-
-
3 .3 V
2 .0 V
1 .5 V
0 .8 V
0V
Tf
Tr
Figure 12. Lumped Load For Single-ended Output Signals (for AC Parameters Measurement)
Table 10.CPU Clock Current Select Function
Board Target Trace/Term Z
Reference R, IREF – VDD (3*RREF)
Output Current
Voh @ Z
50 Ohms
RREF = 475 1%, IREF = 2.32 mA
IOH = 6*IREF
0.7V @ 50
Ordering Information
Part Number
Package Type
Product Flow
CY28409OC
56-pin SSOP
Commercial, 0° to 70°C
CY28409OCT
56-pin SSOP – Tape and Reel
Commercial, 0° to 70°C
CY28409ZC
56-pin TSSOP
Commercial, 0° to 70°C
CY28409ZCT
56-pin TSSOP – Tape and Reel
Commercial, 0° to 70°C
CY28409OXC
56-pin SSOP
Commercial, 0° to 70°C
CY28409OCXT
56-pin SSOP – Tape and Reel
Commercial, 0° to 70°C
CY28409ZXC
56-pin TSSOP
Commercial, 0° to 70°C
CY28409ZXCT
56-pin TSSOP – Tape and Reel
Commercial, 0° to 70°C
PB-Free
Document #: 38-07445 Rev. *D
Page 15 of 17
CY28409
Package Drawings and Dimensions
56-lead Shrunk Small Outline Package O56
51-85062-*C
56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56
0.249[0.009]
28
1
DIMENSIONS IN MM[INCHES] MIN.
MAX.
REFERENCE JEDEC MO-153
7.950[0.313]
8.255[0.325]
PACKAGE WEIGHT 0.42gms
5.994[0.236]
6.198[0.244]
PART #
Z5624 STANDARD PKG.
ZZ5624 LEAD FREE PKG.
29
56
13.894[0.547]
14.097[0.555]
1.100[0.043]
MAX.
GAUGE PLANE
0.25[0.010]
0.20[0.008]
0.851[0.033]
0.950[0.037]
0.500[0.020]
BSC
0.170[0.006]
0.279[0.011]
0.051[0.002]
0.152[0.006]
0°-8°
0.508[0.020]
0.762[0.030]
0.100[0.003]
0.200[0.008]
SEATING
PLANE
51-85060-*C
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips
I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification
as defined by Philips. Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned
in this document are the trademarks of their respective holders.
Document #: 38-07445 Rev. *D
Page 16 of 17
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY28409
Document History Page
Document Title: CY28409 Clock Synthesizer with Differential SRC and CPU Outputs
Document Number: 38-07445
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
121414
12/04/02
RGL
New Data Sheet
*A
124795
07/07/03
RGL
Changed revision code to 4
Corrected rise/fall time value on DOT from 1.0/2.0 to 0.5/1.0 ns, respectively
Changed USB and DOT from long-term jitter to cycle-to-cycle jitter
Changed USB and DOT period value from 28.8257/28.8340 to
20.8271/20.8396 ns, respectively
*B
128864
08/29/03
RGL
Fixed the I2C registers to match the actual device
Removed all items referencing to 166 MHz
*C
340360
See ECN
RGL
Changed Byte 6 Bit 3 to Reserve
*D
417655
See ECN
RGL
Added Lead-free devices
Document #: 38-07445 Rev. *D
Page 17 of 17
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