Fairchild FIN424C 20-bit ultra-low-power serializer / deserializer for î¼controller and rgb display Datasheet

FIN424C / FIN425C
20-Bit Ultra-Low-Power Serializer / Deserializer for µController and
RGB Displays
Features
Description
Data & Control Bits
Frequency
Capability
Interface
µController Usage
Selectable Edge Rates
Dynamic Current
Standby Current
Core Voltage (VDDA/S)
I/O Voltage (VDDP)
ESD
Package
Ordering Information
20
10MHz
QVGA
Microcontroller / RGB
I86 & m68
Yes
9mA / Pair
10µA
2.5 to 3.0V
1.6V to VDDA/S
15KV (IEC)
MLP-32 (5 x 5mm)
FIN424CMLX
FIN425CMLX
Applications
The FIN424C and FIN425C μSerDes™ are a low-power
serializer/ deserializer pair that can help minimize the cost
and power of an LCD interface. They are designed to
operate transparently between the baseband processor and
LCD. /WE and chip-select timing is maintained from the
serializer to the deserializer. Through the use of
serialization, the number of signals transferred from one
point to another can be significantly reduced. Typical
reduction is 5:1. Through the use of differential signaling,
shielding, and EMI filters can also be minimized, further
reducing the cost of serialization. Differential signaling is
important for providing a noise-insensitive signal that can
withstand radio and electrical noise sources. Major reduction
in power consumption allows minimal impact on battery life
in mobile applications.
Related Resources
ƒ Slider, Folder, and Clamshell Mobile Handsets
ƒ GSM and CDMA Phones
For more information, please visit:
http://www.fairchildsemi.com/products/interface/userdes.html
Typical Application
Simple Interface
Serializer
+
-
70-130
Ohms
Deserializer
+
2
-
2
+
-
20-Bit Deserializer
20-Bit Serializer
Baseband
+
Built-in voltage
translation
Main
Display
Internal
Termination
Figure 1.
© 2009 Fairchild Semiconductor Corporation
FIN424C / FIN425C • Rev. 1.0.0
Mobile Phone Example
www.fairchildsemi.com
µSerDes™ FIN424C / FIN425C — 20-Bit Ultra-Low-Power Serializer / Deserializer for µController and RGB Displays
November 2009
Pin Name
Description
STRB
LVCMOS Strobe Signal for Latching Data into the Serializer (On Rising Edge)
DP[19:0]
LVCMOS Data Input
/RES
Low-Power Mode
/STBY
SerDes Standby
Test
DS+, DSCKS+, CKSVDDP
VDDS
VDDA
GND
Internal Use (Should be GND)
Serial Data Output
Serial Clock Output
Power Supply for Parallel I/O and Internal Circuitry
Power Supply for Serial I/O
Power Supply for Core
Ground Pins
0
1
0
1
Serializer Low Power
Serializer Enabled
Serializer and Deserializer in Low Power
Serializer and Deserializer Enabled
25 DP[13]
26 DP[14]
27 STRB
28 DP[15]
29 DP[16]
30 DP[17]
31 DP[18]
32 DP[19]
Notes:
1. 0 = VIL; 1 = VIH.
2. All GND and VDDP pins must be connected to ground and VDDP, respectively.
CKS+ 1
24 DP[12]
CKS- 2
23 DP[11]
VDDS 3
22 DP[10]
VDDA 4
21 VDDP
GND PAD
Must be Grounded
DS- 5
20 DP[9]
Figure 2.
© 2009 Fairchild Semiconductor Corporation
FIN424C / FIN425C • Rev. 1.0.0
DP[5] 16
DP[4] 15
DP[3] 14
17 DP[6]
DP[2] 13
VDDP 8
DP[1] 12
18 DP[7]
DP[0] 11
/RES 7
Test 10
19 DP[8]
/STBY 9
DS+ 6
FIN424CMLX MLP-32 Pinout (Top Through View)
www.fairchildsemi.com
2
µSerDes™ FIN424C / FIN425C — 20-Bit Ultra-Low-Power Serializer / Deserializer for µController and RGB Displays
FIN424C Serializer Pin Descriptions
µSerDes™ FIN424C / FIN425C — 20-Bit Ultra-Low-Power Serializer / Deserializer for µController and RGB Displays
FIN425C Deserializer Pin Descriptions
Pin Name
Description
WCLK
DP[19:0]
LVCMOS STRB Output
LVCMOS Data Output
/RES
Low-Power Mode
SLEW
Parallel Output Edge Rate Control
Test
DS+, DSCKS+, CKSVDDP
VDDS
VDDA
GND
Internal Use (Should be GND)
Serial Data Input
Serial Clock Input
Power Supply for Parallel I/O and internal circuitry
Power Supply for Serial I/O
Power Supply for Core
Ground Pins
0
1
0
1
Deserializer Low Power
Deserializer Enabled
Slow Output Edge Rates
Fast Output Edge Rates
2 5 D P [1 3]
2 6 D P [1 4]
27 W CLK
2 8 D P [1 5]
29 D P [16]
3 0 D P [17]
31 D P [18]
3 2 D P [19]
Notes:
3. 0 = VIL; 1 = VIH.
4. All GND and VDDP pins must be connected to ground and VDDP, respectively.
1
2 4 D P [1 2]
CKS- 2
2 3 D P [1 1]
CKS+
VDDS
3
VDDA
4
2 2 D P [1 0]
21 VDD P
GND PAD
M u st b e G rou nd ed
DS- 5
2 0 D P [9 ]
1 7 D P [6 ]
SLEW
Figure 3.
© 2009 Fairchild Semiconductor Corporation
FIN424C / FIN425C • Rev. 1.0.0
D P [5] 1 6
8
D P [4] 1 5
VDDP
D P [3] 1 4
1 8 D P [7 ]
D P [2] 1 3
7
D P [1] 1 2
/R E S
D P [0] 1 1
1 9 D P [8 ]
Test 1 0
6
9
DS+
FIN425CMLX MLP-32 Pinout (Top Through View)
www.fairchildsemi.com
3
/RES
FIN424C
FIN425C
/STBY
FIN424C
Mode
0
X
Reset Mode
1
0
Standby Mode
1
1
Operating Mode
FIN424C Parallel
Input State
Pins
DP[19:0]
STRB / WCLK
DP[19:0]
STRB / WCLK
DP[19:0]
STRB / WCLK
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
FIN425C Parallel
Output State
LOW
HIGH
LAST STATE
HIGH
ENABLED
ENABLED
Application Diagram
FIN424C
Baseband
Processor
/WE
DP[15:0]
A0
CS1
CS2
Reset
/STBY
1.8V
FIN425C
2.8V
2.8V
VDDP VDDS/A
VDDP VDDS/A
STRB
DP[15:0]
DP[16]
DP[17]
DP[18]
DP[19]
WCLK
CKS+
CKS-DS+
DS--
CKS+
CKS-DS+
DS--
/RES
/STBY
Test
DP[15:0]
DP[16]
DP[17]
DP[18]
DP[19]
Slew
Test
/RES
GND
Figure 4.
© 2009 Fairchild Semiconductor Corporation
FIN424C / FIN425C • Rev. 1.0.0
2.8V
Main Display
16-Bit
- µController
/WE
A0
DATA[15:0]
RESET
/CS
Sub-Display
8-Bit
µController
8
/WE
A0
DATA[7:0]
RESET
/CS
GND
Dual-Display, 16-Bit, µController Interface
www.fairchildsemi.com
4
µSerDes™ FIN424C / FIN425C — 20-Bit Ultra-Low-Power Serializer / Deserializer for µController and RGB Displays
Table 1. Reset and Standby Modes / States
Baseband
Processor
/WE
DP[17:0]
A0
CS
FIN425C
2.8V
2.8V
VDDP VDDS/A
VDDP VDDS/A
STRB
WCLK
DP[17:0]
DP[18]
DP[19]
CKS+
CKS--
DS+
DS--
/RES
/STBY
Test
Figure 5.
DP[17:0]
HSYNC
VSYNC
/CS
Reset
/STBY
/WE
DATA[17:0]
/A0
CS
RESET
GND
Single–Display, 18-Bit, µController Interface
FIN424C
1.8V
Baseband
Processor
Main Display
18-Bit
- µController
Slew
Test
/RES
GND
PCLK
DP[17:0]
DP[18]
DP[19]
CKS+
CKS--
DS+
DS-Reset
/STBY
2.8V
FIN425C
2.8V
2.8V
VDDP VDDS/A
2.8V
VDDP VDDS/A
STRB
WCLK
DP[17:0]
DP[18]
DP[19]
CKS+
CKS--
CKS+
CKS--
DS+
DS--
DP[17:0]
DP[18]
DP[19]
DS+
DS--
/RES
/STBY
Test
Main Display
18-Bit
- RGB
PCLK
DATA[17:0]
HSYNC
VSYNC
/CS
RESET
Slew
Test
/RES
GND
GND
Figure 6.
Single-Display, 18-Bit, RGB Interface
Additional Application Information
Flex Cabling: The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this serial I/O
flex cable. The following best practices should be used when developing the flex cabling or Flex PCB.
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
Keep all four differential serial wires the same length.
Do not allow noisy signals over or near differential serial wires. Example: No CMOS traces over differential serial wires.
Use a design goal of 70 to 130Ω differential characteristic impedance.
Do not place test points on differential serial wires.
Design differential serial wires a minimum of 2cm away from the antenna.
Visit Fairchild’s website at http://www.fairchildsemi.com/products/interface/userdes.html, contact your sales
representative, or contact Fairchild directly at [email protected] for applications notes or flex guidelines.
© 2009 Fairchild Semiconductor Corporation
FIN424C / FIN425C • Rev. 1.0.0
www.fairchildsemi.com
5
µSerDes™ FIN424C / FIN425C — 20-Bit Ultra-Low-Power Serializer / Deserializer for µController and RGB Displays
FIN424C
1.8V
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable
above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition,
extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute
maximum ratings are stress ratings only.
Symbol
VDD
VIO
TSTG
Parameter
Min.
Max.
Unit
Supply Voltage
-0.5
+3.6
V
All Input / Output Voltage
-0.5
VDDP+0.5
V
Storage Temperature Range
-65
+150
°C
TJ
Maximum Junction Temperature
+150
°C
TL
Lead Temperature (Soldering, Four Seconds)
+260
°C
IEC 61000 Board Level
15.0
ESD
Human Body Model, JESD22-A114
All Pins
7.5
Serial I/O, /RES, PAR/SPI to GND
14.0
kV
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating
conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend
exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Min.
Max.
Unit
2.5
3.0
V
Supply Voltage
1.6
VDDA/S
V
Operating Temperature
-30
+85
°C
VDDA, VDDS(5)
Supply Voltage
VDDP
TA
Notes:
5. VDDA and VDDS supplies must be hardwired together to the same power supply. VDDP must be less than or equal to
VDDA/VDDS.
6. Typical values are tested at TA=25°C and 2.75V.
© 2009 Fairchild Semiconductor Corporation
FIN424C / FIN425C • Rev. 1.0.0
www.fairchildsemi.com
6
µSerDes™ FIN424C / FIN425C — 20-Bit Ultra-Low-Power Serializer / Deserializer for µController and RGB Displays
Absolute Maximum Ratings
Values valid for over-supply voltage and operating temperature ranges unless otherwise specified.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
0.7 x VDDP
VDDP
V
GND
0.3 x VDDP
V
DC Parallel I/O and Serial Characteristics
VIH
Input High Voltage
VIL
Input Low Voltage
VOH
Output High Voltage
VOL
Output Low Voltage
IIN
VGO
Z
SLEW=0 IOH=-250µA
SLEW=0 IOL=250µA
SLEW=1 IOL=1mA
Input Current
Serial Input Voltage Ground
Offset
V
0.8 x VDDP
SLEW=1 IOH=-1mA
-5
FIN425C to FIN424C
0.2 x VDDP
V
5
µA
0
Serial Transmission Line Impedance
70
100
V
130
Ω
Power Characteristics
IDYN_FIN424C
Dynamic Current FIN424C
VDDA/S=2.75V, VDDP=1.8V,
/STBY=1, /RES=1
5.44MHz
4
mA
IDYN_FIN425C
Dynamic Current FIN425C
VDDA/S=2.75V VDDP=1.8V,
/STBY=1, /RES=1, CL=0pF
5.44MHz
5
mA
IBRST_FIN424C Burst Standby Current FIN424C
VDDA/S=2.75V, VDDP=1.8V, /STBY=1,
/RST=1, No STROBE Signal,
1.3
mA
IBRST_FIN425C Burst Standby Current FIN425C
VDDA/S=2.75V, VDDP=1.8V, /STBY=1,
/RST=1, No STROBE Signal, CL=0pF
1.8
mA
ISTBY
Standby Current
FIN424C / FIN425C VDDS/A=VDDP=3.0V,
/STBY=0, /RST=1
10
µA
IRES
Reset Current
FIN424C / FIN425C VDDS/A=VDDP=3.0V,
/RST=0
10
µA
10
MHz
40
ns
AC FIN424C Specifications
fWSTRB0
Strobe Frequency
tR, tF
Input Edge Rates
0
(7)
tS1
DP Setup Time
DP Before STRBn ↑
tH1
DP Hold Time
DP After STRBn ↑(7)
5
ns
15
ns
AC FIN425C Specifications
tR0, tF0
Output Edge Rates of WCLK
tR1, tF1
Output Edge Rates of DP[19:0]
tcs
DP[19:0] to Falling edge of WCLK
CL=5pF 20% to 80%
tPWL
WCLK Output Pulse Width Low,
Measured 30% to 30%(7)
SLEW=0, CL=5pF 20% to 80%(7)
SLEW=1, CL=5pF 20% to 80%
SLEW=0, CL=5pF 20% to 80%(7)
SLEW=1, CL=5pF 20% to 80%
DP
tPWL
WCLK
8
17
(7)
10
8
22
(7)
17
ns
ns
0
4
50
56
240
275
310
MHz
15
30
µs
ns
tCS
AC Oscillator Specifications
fOSC
tOSC-STBY
Serial Operating Frequency
Oscillator Stabilization Time After
Standby
© 2009 Fairchild Semiconductor Corporation
FIN424C / FIN425C • Rev. 1.0.0
VDDA=VDDS=2.75V
/RES=1, /STBY ↑ Transition
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7
µSerDes™ FIN424C / FIN425C — 20-Bit Ultra-Low-Power Serializer / Deserializer for µController and RGB Displays
Electrical Specifications
Parameter
tOSC-RES
Oscillator Stabilization Time After
Reset
Test Conditions
Min.
VDDA=VDDS=2.75V
/STBY=1, /RES ↑ Transition
Typ.
Max.
Unit
30
50
µs
AC Reset and Standby Timing
tSTRB-RES
/RES after last STRBn ↑
tSTRB-RES
0
ns
200
ns
/RES
/STBY
tSTRB-STBY
Standby Time After Last Strobe
STRB
tSTRB- STBY
tVDD-SKEW
tVDD-RES
Allowed Power up Skew between
VDDP and VDDA/S
Minimum Reset Low Time After
VDD Stable
tVDD-SKEW
tVDD-RES
tRES-STBY
tOSC-STBY
-∞
+∞
ms
VDDA/S
VDDP
20
µs
20
µs
/RES
tRES-STBY
/STBY Wait Time After
/RES ↑
/STBY
STRB
Note:
7. Characterized, but not production tested.
© 2009 Fairchild Semiconductor Corporation
FIN424C / FIN425C • Rev. 1.0.0
www.fairchildsemi.com
8
µSerDes™ FIN424C / FIN425C — 20-Bit Ultra-Low-Power Serializer / Deserializer for µController and RGB Displays
Symbol
0.15 C
5.00
B
A
5.00
(0.76)
(0.25 )
PIN #1 IDENT
5.38 MIN
0.15 C
3.37 MAX
3.86 MIN
0.80 MAX
0.10 C
0.08 C
0.20MIN
X4
(0.20)
0.05
0.00
0.28 MAX
C
X40
SEATING
PLANE
0.50TYP
E
3.70
3.50
0.45
0.35
PIN #1 IDENT
PIN #1 ID
0.50
3.70
3.50
(DATUM B)
PIN #1 ID
(DATUM A)
0.18-0.30
0.10
0.05
0.50
C A B
C
NOTES:
A. CONFORMS TO JEDEC REGISTRATION MO-220, VARIATION
WHHD-4. THIS PACKAGE IS ALSO FOOTPRINT COMPATIBLE WITH
WHHD-5.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994.
D. LAND PATTERN PER IPC SM-782.
E. WIDTH REDUCED TO AVOID SOLDER BRIDGING.
F. DIMENSIONS ARE NOT INCLUSIVE OF BURRS, MOLD FLASH, OR
TIE BAR PROTRUSIONS.
G. DRAWING FILENAME: MKT-MLP32Arev3.
Figure 7.
32-Lead, Molded Leadless Package (MLP), QUAD, JEDEC MO-220, Variation WHHD-4, 5mm Square
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without
notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the
most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein,
which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Ordering Information
Part Number
Operating
Temperature Range
FIN424CMLX
-30 to +85°C
FIN425CMLX
-30 to +85°C
Package
Packing Method
Green
32-Lead, Molded Leadless Package (MLP), QUAD,
JEDEC MO-220, Variation WHHD-4, 5mm Square
Tape and Reel
Green
32-Lead, Molded Leadless Package (MLP), QUAD,
JEDEC MO-220, Variation WHHD-4, 5mm Square
Tape and Reel
Eco Status
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2009 Fairchild Semiconductor Corporation
FIN424C / FIN425C • Rev. 1.0.0
www.fairchildsemi.com
9
µSerDes™ FIN424C / FIN425C — 20-Bit Ultra-Low-Power Serializer / Deserializer for µController and RGB Displays
Physical Dimensions
µSerDes™ FIN424C / FIN425C — 20-Bit Ultra-Low-Power Serializer / Deserializer for µController and RGB Displays
10
www.fairchildsemi.com
© 2009 Fairchild Semiconductor Corporation
FIN424C / FIN425C • Rev. 1.0.0
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