Cypress CY7C107-20VC 1m x 1 static ram Datasheet

CY7C107
CY7C1007
1M x 1 Static RAM
Features
memory expansion is provided by an active LOW Chip Enable
(CE) and three-state drivers. These devices have an automatic
power-down feature that reduces power consumption by more
than 65% when deselected.
• High speed
— tAA = 12 ns
• CMOS for optimum speed/power
• Low active power
— 825 mW
• Low standby power
— 275 mW
• 2.0V data retention (optional)
— 100 µW
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
Writing to the devices is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the input pin
(DIN) is written into the memory location specified on the address pins (A0 through A19).
Reading from the devices is accomplished by taking Chip Enable (CE) LOW while Write Enable (WE) remains HIGH. Under
these conditions, the contents of the memory location specified by the address pins will appear on the data output (DOUT)
pin.
Functional Description
The output pin (D OUT) is placed in a high-impedance state
when the device is deselected (CE HIGH) or during a write
operation (CE and WE LOW).
The CY7C107 and CY7C1007 are high-performance CMOS
static RAMs organized as 1,048,576 words by 1 bit. Easy
The CY7C107 is available in a standard 400-mil-wide SOJ; the
CY7C1007 is available in a standard 300-mil-wide SOJ.
Logic Block Diagram
Pin Configuration
SOJ
Top View
DIN
A10
A11
A12
A13
A14
A15
NC
A16
A17
A18
A19
512x2048
ARRAY
DOUT
DOUT
WE
GND
VCC
A9
A8
A7
A6
A5
A4
NC
A3
A2
A1
A0
DIN
CE
107-2
POWER
DOWN
CE
A9
A 10
A 11
A12
A 13
A14
A15
A16
A 17
A 18
A 19
COLUMN
DECODER
SENSE AMPS
ROW DECODER
INPUT BUFFER
A0
A1
A2
A3
A4
A5
A6
A7
A8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
WE
107-1
Selection Guide
7C107-12
7C1007-12
7C107-15
7C1007-15
7C107-20
7C1007-20
7C107-25
7C1007-25
7C107-35
12
150
15
135
20
125
25
120
35
110
50
40
30
30
25
Maximum Access Time (ns)
Maximum Operating
Current (mA)
Maximum Standby
Current (mA)
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134 •
408-943-2600
December 1992 – Revised September 3, 1999
CY7C107
CY7C1007
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ..................................... −65°C to +150°C
Latch-Up Current ..................................................... >200 mA
Ambient Temperature with
Power Applied .................................................. −55°C to +125°C
Operating Range
Supply Voltage on VCC Relative to GND
[1]
.....−0.5V to +7.0V
Ambient
Temperature[2]
0°C to +70°C
−40°C to +85°C
Range
Commercial
Industrial
DC Voltage Applied to Outputs
in High Z State[1] ....................................... −0.5V to VCC + 0.5V
DC Input Voltage[1] .................................... −0.5V to VCC + 0.5V
VCC
5V ± 10%
5V ± 10%
Electrical Characteristics Over the Operating Range
7C107-12
7C1007-12
Parameter
Description
Test Conditions
Min.
2.4
Max.
7C107-15
7C1007-15
Min.
Max.
7C107-20
7C1007-20
Min.
Max.
Unit
VOH
Output HIGH
Voltage
VCC = Min., IOH = −4.0 mA
VOL
Output LOW
Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input HIGH
Voltage
2.2
VCC+
0.3
2.2
VCC+
0.3
VIL
Input LOW
Voltage[1]
−0.3
0.8
−0.3
0.8
IIX
Input Load Current
GND < VI < VCC
−1
+1
−1
+1
−1
+1
µA
IOZ
Output Leakage
Current
GND < VI < VCC,
Output Disabled
–5
+5
–5
+5
–5
+5
µA
IOS
Output Short
Circuit Current[3]
VCC = Max., VOUT = GND
−300
−300
−300
mA
ICC
VCC Operating
Supply Current
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
150
135
125
mA
ISB1
Automatic CE
Power-Down
Current— TTL Inputs
Max. VCC, CE > VIH,
VIN >VIH or VIN < VIL,
f = f MAX
50
40
30
mA
ISB2
Automatic CE
Power-Down
Current—
CMOS Inputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or
VIN < 0.3V, f = 0
2
2
2
mA
2.4
0.4
0.4
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the “instant on” case temperature.
3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
2
2.4
V
0.4
V
2.2
VCC+
0.3
V
−0.3
0.8
V
CY7C107
CY7C1007
Electrical Characteristics Over the Operating Range (continued)
7C107-25
7C1007-25
Parameter
Description
Test Conditions
Min.
VOH
Output HIGH
Voltage
VCC = Min., IOH = −4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input HIGH Voltage
[1]
Max.
2.4
7C107-35
Min.
Max.
Unit
2.4
0.4
V
0.4
V
2.2
VCC + 0.3
2.2
VCC + 0.3
V
−0.3
0.8
−0.3
0.8
V
VIL
Input LOW Voltage
IIX
Input Load Current
GND < VI < VCC
−1
+1
−1
+1
µA
IOZ
Output Leakage
Current
GND < VI < VCC,
Output Disabled
−5
+5
−5
+5
µA
IOS
Output Short
Circuit Current[3]
VCC = Max., VOUT = GND
−300
−300
mA
ICC
VCC Operating
Supply Current
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
120
110
mA
ISB1
Automatic CE
Power-Down
Current—TTL Inputs
Max. V CC, CE > VIH,
VIN >VIH or VIN < VIL,
f = f MAX
30
25
mA
ISB2
Automatic CE
Power-Down
Current—CMOS Inputs
Max. V CC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or
VIN < 0.3V, f = 0
2
2
mA
Capacitance[4]
Parameter
CIN: Addresses
Description
Input Capacitance
CIN: Controls
COUT
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Output Capacitance
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
3
Max.
Unit
7
pF
10
pF
10
pF
CY7C107
CY7C1007
AC Test Loads and Waveforms
R1 480Ω
5V
R1 480Ω
5V
OUTPUT
R2
255Ω
30 pF
Equivalent to:
INCLUDING
JIG AND
SCOPE (b)
90%
90%
10%
GND
R2
255Ω
5 pF
INCLUDING
JIG AND
SCOPE
(a)
ALL INPUT PULSES
3.0V
OUTPUT
10%
≤ 3 ns
≤ 3 ns
107-4
107-3
THÉVENIN EQUIVALENT
167Ω
OUTPUT
1.73V
Switching Characteristics[5] Over the Operating Range
Parameter
Description
7C107-12
7C1007-12
7C107-15
7C1007-15
7C107-20
7C1007-20
7C107-25
7C1007-25
Min.
Min.
Min.
Min.
Max.
Max.
Max.
Max.
7C107-35
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
12
tAA
Address to Data Valid
tOHA
Data Hold from Address
Change
tACE
CE LOW to Data Valid
tLZCE
CE LOW to Low Z[6]
tHZCE
CE HIGH to High Z [6, 7]
tPU
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
15
20
12
3
15
3
15
3
0
15
35
25
8
0
35
ns
ns
10
0
25
ns
ns
3
10
20
ns
3
3
0
12
25
20
7
35
3
3
6
0
20
3
12
3
25
ns
ns
35
ns
WRITE CYCLE[8]
tWC
Write Cycle Time
12
15
20
25
35
ns
tSCE
CE LOW to Write End
10
12
15
20
25
ns
tAW
Address Set-Up to Write
End
10
12
15
20
25
ns
tHA
Address Hold from Write
End
0
0
0
0
0
ns
tSA
Address Set-Up to Write
Start
0
0
0
0
0
ns
tPWE
WE Pulse Width
10
12
15
20
25
ns
tSD
Data Set-Up to Write End
7
8
10
15
20
ns
tHD
Data Hold from Write End
0
0
0
0
0
ns
[6]
tLZWE
WE HIGH to Low Z
tHZWE
WE LOW to High Z[6, 7]
3
3
3
6
7
3
8
3
10
ns
10
ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device.
7. tHZCE and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
4
CY7C107
CY7C1007
Data Retention Characteristics Over the Operating Range (L Version Only)
Parameter
Conditions[9]
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR[4]
Chip Deselect to Data Retention Time
tR[4]
Operation Recovery Time
Min.
Max.
Unit
50
µA
2.0
VCC = VDR = 2.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3 or
VIN < 0.3V
V
0
ns
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
VCC
4.5V
VDR > 2V
tCDR
4.5V
tR
CE
107-5
Switching Waveforms
Read Cycle No. 1[10, 11]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
107-6
Read Cycle No. 2[11, 12]
ADDRESS
tRC
CE
tACE
tHZCE
tLZCE
DATA OUT
VCC
SUPPLY
CURRENT
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tPD
tPU
ICC
50%
50%
ISB
107-7
Notes:
9. No input may exceed VCC + 0.5V.
10. Device is continuously selected, CE = VIL.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
5
CY7C107
CY7C1007
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[13]
tWC
ADDRESS
tSA
tSCE
CE
tHA
tAW
tPWE
WE
tHD
tSD
DATA IN
DATA OUT
DATA VALID
HIGH IMPEDANCE
107-8
Write Cycle No. 2 (WE Controlled)[13]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tSD
DATA IN
DATA VALID
tHZWE
DATA OUT
tHD
tLZWE
HIGH IMPEDANCE
DATA UNDEFINED
107-9
Note:
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
6
CY7C107
CY7C1007
Truth Table
CE
WE
DOUT
Mode
Power
H
X
High Z
Power-Down
Standby (ISB)
L
H
Data Out
Read
Active (ICC)
L
L
High Z
Write
Active (ICC)
Ordering Information
Speed
(ns)
12
15
15
20
25
Ordering Code
CY7C107-12VC
CY7C1007-12VC
CY7C107-15VC
CY7C1007-15VC
CY7C107-15VI
CY7C1007-15VI
CY7C107-20VC
CY7C1007-20VC
CY7C107-25VC
CY7C1007-25VC
Package
Name
V28
V21
V28
V21
V28
V21
V28
V21
V28
V21
Package Type
28-Lead (400-Mil) Molded SOJ
28-Lead (300-Mil) Molded SOJ
28-Lead (400-Mil) Molded SOJ
28-Lead (300-Mil) Molded SOJ
28-Lead (400-Mil) Molded SOJ
28-Lead (300-Mil) Molded SOJ
28-Lead (400-Mil) Molded SOJ
28-Lead (300-Mil) Molded SOJ
28-Lead (400-Mil) Molded SOJ
28-Lead (300-Mil) Molded SOJ
Operating
Range
Commercial
Commercial
Industrial
Commercial
Commercial
Contact factory for “L” version availability.
Document #: 38-00232-C
Package Diagrams
28-Lead (300-Mil) Molded SOJ V21
51-85031-B
7
CY7C107
CY7C1007
Package Diagrams (continued)
28-Lead (400-Mil) Molded SOJ V28
51-85032-A
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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