OKI MSM511000CL-60ZS 1,048,576-word x 1-bit dynamic ram : fast page mode type Datasheet

E2G0009-17-41
¡ Semiconductor
MSM511000C/CL
¡ Semiconductor
This version:
Jan. 1998
MSM511000C/CL
Previous version: May 1997
1,048,576-Word ¥ 1-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
DESCRIPTION
The MSM511000C/CL is a 1,048,576-word ¥ 1-bit dynamic RAM fabricated in Oki's silicon-gate
CMOS technology. The MSM511000C/CL achieves high integration, high-speed operation, and
low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/
single-layer metal CMOS process. The MSM511000C/CL is available in a 26/20-pin plastic SOJ or
20-pin plastic ZIP. The MSM511000CL (the low-power version) is specially designed for lowerpower applications.
FEATURES
• 1,048,576-word ¥ 1-bit configuration
• Single 5 V power supply, ±10% tolerance
• Input
: TTL compatible, low input capacitance
• Output : TTL compatible, 3-state
• Refresh : 512 cycles/8 ms, 512 cycles/64 ms (L-version)
• Fast page mode, read modify write capability
• CAS before RAS refresh, hidden refresh, RAS-only refresh capability
• Package options:
26/20-pin 300 mil plastic SOJ (SOJ26/20-P-300-1.27) (Product : MSM511000C/CL-xxJS)
20-pin 400 mil plastic ZIP
(ZIP20-P-400-1.27)
(Product : MSM511000C/CL-xxZS)
xx indicates speed rank.
PRODUCT FAMILY
Family
MSM511000C/CL-45
Access Time (Max.)
Cycle Time
Power Dissipation
(Min.)
Operating (Max.) Standby (Max.)
tRAC
tAA
tCAC
45 ns
24 ns
14 ns
90 ns
468 mW
MSM511000C/CL-50
50 ns
26 ns
14 ns
100 ns
440 mW
5.5 mW/
MSM511000C/CL-60
60 ns
30 ns
15 ns
120 ns
385 mW
1.1 mW (L-version)
MSM511000C/CL-70
70 ns
35 ns
20 ns
130 ns
330 mW
1/15
¡ Semiconductor
,
MSM511000C/CL
PIN CONFIGURATION (TOP VIEW)
DIN 1
26 VSS
WE 2
RAS 3
NC 4
NC 5
A0 9
A1 10
A2 11
A3 12
VCC 13
A9 1
25 DOUT
DOUT 3
24 CAS
DIN 5
23 NC
RAS 7
22 A9
NC 9
A0 11
18 A8
A2 13
17 A7
VCC 15
16 A6
A5 17
15 A5
A7 19
14 A4
26/20-Pin Plastic SOJ
Pin Name
A0 - A9
RAS
2 CAS
4 VSS
6 WE
8 NC
NO LEAD
12 A1
14 A3
16 A4
18 A6
20 A8
20-Pin Plastic ZIP
Function
Address Input
Row Address Strobe
CAS
Column Address Strobe
DIN
Data Input
DOUT
Data Output
WE
Write Enable
VCC
Power Supply (5 V)
VSS
Ground (0 V)
NC
No Connection
2/15
¡ Semiconductor
MSM511000C/CL
BLOCK DIAGRAM
Timing
Generator
RAS
Timing
Generator
CAS
10
Column
Address
Buffers
10
Internal
Address
Counter
A0 - A9
10
Row
Address
Buffers
Refresh
Control Clock
10
Row
Decoders
Word
Drivers
Column
Decoders
Write
Clock
Generator
Sense
Amplifiers
I/O
Selector
Memory
Cells
Input
Buffer
WE
Output
Buffer
DOUT
DIN
VCC
On Chip
VBB Generator
VSS
3/15
¡ Semiconductor
MSM511000C/CL
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
VT
–1.0 to 7.0
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD*
1
W
Operating Temperature
Topr
0 to 70
°C
Storage Temperature
Tstg
–55 to 150
°C
Voltage on Any Pin Relative to VSS
*: Ta = 25°C
Recommended Operating Conditions
Parameter
Power Supply Voltage
(Ta = 0°C to 70°C)
Symbol
Min.
Typ.
Max.
Unit
VCC
4.5
5.0
5.5
V
VSS
0
0
0
V
Input High Voltage
VIH
2.4
—
6.5
V
Input Low Voltage
VIL
–1.0
—
0.8
V
Capacitance
(VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz)
Symbol
Typ.
Max.
Unit
CIN1
—
5
pF
Input Capacitance (RAS, CAS, WE)
CIN2
—
5
pF
Output Capacitance (DOUT)
COUT
—
6
pF
Parameter
Input Capacitance (A0 - A9, DIN)
4/15
¡ Semiconductor
MSM511000C/CL
DC Characteristics
Parameter
(VCC = 5 V ±10%, Ta = 0°C to 70°C)
Symbol
Condition
MSM511000 MSM511000 MSM511000 MSM511000
C/CL-45
C/CL-50
C/CL-60
C/CL-70 Unit Note
Min. Max. Min. Max. Min. Max. Min. Max.
Output High Voltage
VOH
IOH = –5.0 mA
2.4
VCC
2.4
VCC
2.4
VCC
2.4
VCC
V
Output Low Voltage
VOL
IOL = 4.2 mA
0
0.4
0
0.4
0
0.4
0
0.4
V
Input Leakage Current
ILI
All other pins not
–10
10
–10
10
–10
10
–10
10
mA
–10
10
–10
10
–10
10
–10
10
mA
—
85
—
80
—
70
—
60
mA
1, 2
RAS, CAS = VIH
—
2
—
2
—
2
—
2
RAS, CAS
—
1
—
1
—
1
—
1
mA
1
≥ VCC –0.2 V
—
200
—
200
—
200
—
200
mA
1, 5
—
85
—
80
—
70
—
60
mA
1, 2
—
5
—
5
—
5
—
5
mA
1
—
85
—
80
—
70
—
60
mA
1, 2
—
80
—
75
—
65
—
55
mA
1, 3
—
300
—
300
—
300
—
300
mA
1, 4,
5
0 V £ VI £ 6.5 V;
under test = 0 V
Output Leakage Current
ILO
Average Power
Supply Current
ICC1
(Operating)
Power Supply
Current (Standby)
ICC2
0 V £ VO £ 5.5 V
RAS, CAS cycling,
tRC = Min.
RAS cycling,
Average Power
Supply Current
DOUT disable
ICC3
(RAS-only Refresh)
CAS = VIH,
tRC = Min.
RAS = VIH,
Power Supply
Current (Standby)
ICC5
Average Power
Supply Current
ICC6
(CAS before RAS Refresh)
RAS cycling,
CAS before RAS
RAS = VIL,
Average Power
Supply Current
CAS = VIL,
DOUT = enable
ICC7
CAS cycling,
(Fast Page Mode)
tPC = Min.
Average Power
tRC = 125 ms,
Supply Current
(Battery Backup)
Notes : 1.
2.
3.
4.
5.
ICC10 CAS before RAS,
tRAS £ 1 ms
ICC Max. is specified as ICC for output open condition.
The address can be changed once or less while RAS = VIL.
The address can be changed once or less while CAS = VIH.
VCC – 0.2 V £ VIH £ 6.5 V, –1.0 V £ VIL £ 0.2 V.
L-version.
5/15
¡ Semiconductor
MSM511000C/CL
AC Characteristics (1/2)
(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3
Parameter
Symbol
MSM511000 MSM511000 MSM511000 MSM511000
C/CL-45
C/CL-50
C/CL-60
C/CL-70 Unit Note
Min. Max. Min. Max. Min. Max. Min. Max.
tRC
90
—
100
—
120
—
130
—
ns
tRWC
110
—
120
—
140
—
155
—
ns
tPC
34
—
36
—
40
—
45
—
ns
tPRWC
54
—
56
—
60
—
70
—
ns
Access Time from RAS
tRAC
—
45
—
50
—
60
—
70
ns
4, 5, 6
Access Time from CAS
tCAC
—
14
—
14
—
15
—
20
ns
4, 5
Access Time from Column Address
tAA
—
24
—
26
—
30
—
35
ns
4, 6
Access Time from CAS Precharge
tCPA
—
28
—
30
—
35
—
40
ns
4
Output Low Impedance Time from CAS
tCLZ
0
—
0
—
0
—
0
—
ns
4
CAS to Data Output Buffer Turn-off Delay Time tOFF
Random Read or Write Cycle Time
Read Modify Write Cycle Time
Fast Page Mode Cycle Time
Fast Page Mode Read Modify Write
Cycle Time
0
14
0
14
0
15
0
20
ns
7
Transition Time
tT
3
50
3
50
3
50
3
50
ns
3
Refresh Period
tREF
—
8
—
8
—
8
—
8
ms
Refresh Period (L-version)
tREF
—
64
—
64
—
64
—
64
ms
RAS Precharge Time
tRP
35
—
40
—
50
—
50
—
ns
RAS Pulse Width
tRAS
45 10,000 50 10,000 60 10,000 70 10,000 ns
RAS Pulse Width (Fast Page Mode)
tRASP
45 100,000 50 100,000 60 100,000 70 100,000 ns
RAS Hold Time
tRSH
14
—
14
—
15
—
20
—
ns
CAS Precharge Time (Fast Page Mode)
tCP
10
—
10
—
10
—
10
—
ns
CAS Pulse Width
tCAS
14 10,000 14 10,000 15 10,000 20 10,000 ns
CAS Hold Time
tCSH
45
—
50
—
60
—
70
—
ns
CAS to RAS Precharge Time
tCRP
5
—
5
—
5
—
5
—
ns
RAS Hold Time from CAS Precharge
tRHCP
28
—
30
—
35
—
40
—
ns
RAS to CAS Delay Time
tRCD
17
31
18
36
20
45
20
50
ns
5
RAS to Column Address Delay Time
tRAD
12
21
13
24
15
30
15
35
ns
6
Row Address Set-up Time
tASR
0
—
0
—
0
—
0
—
ns
Row Address Hold Time
tRAH
7
—
8
—
10
—
10
—
ns
Column Address Set-up Time
tASC
0
—
0
—
0
—
0
—
ns
Column Address Hold Time
tCAH
12
—
13
—
15
—
15
—
ns
Column Address Hold Time from RAS
tAR
35
—
40
—
50
—
55
—
ns
Column Address to RAS Lead Time
tRAL
24
—
26
—
30
—
35
—
ns
6/15
¡ Semiconductor
MSM511000C/CL
AC Characteristics (2/2)
(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3
Parameter
Symbol
MSM511000 MSM511000 MSM511000 MSM511000
C/CL-45
C/CL-50
C/CL-60
C/CL-70 Unit Note
Min. Max. Min. Max. Min. Max. Min. Max.
Read Command Set-up Time
tRCS
0
—
0
—
0
—
0
—
ns
Read Command Hold Time
tRCH
0
—
0
—
0
—
0
—
ns
8
Read Command Hold Time referenced to RAS tRRH
0
—
0
—
0
—
0
—
ns
8
9
Write Command Set-up Time
tWCS
0
—
0
—
0
—
0
—
ns
Write Command Hold Time
tWCH
10
—
10
—
10
—
15
—
ns
Write Command Hold Time from RAS
tWCR
35
—
40
—
50
—
55
—
ns
Write Command Pulse Width
tWP
10
—
10
—
10
—
15
—
ns
Write Command to RAS Lead Time
tRWL
14
—
14
—
15
—
20
—
ns
Write Command to CAS Lead Time
tCWL
14
—
14
—
15
—
20
—
ns
Data-in Set-up Time
tDS
0
—
0
—
0
—
0
—
ns
10
Data-in Hold Time
tDH
12
—
13
—
15
—
15
—
ns
10
Data-in Hold Time from RAS
tDHR
35
—
40
—
50
—
55
—
ns
CAS to WE Delay Time
tCWD
14
—
14
—
15
—
20
—
ns
9
Column Address to WE Delay Time
tAWD
24
—
26
—
30
—
35
—
ns
9
RAS to WE Delay Time
tRWD
45
—
50
—
60
—
70
—
ns
9
CAS Precharge WE Delay Time
tCPWD
33
—
35
—
40
—
45
—
ns
9
CAS Active Delay Time from RAS Precharge tRPC
0
—
0
—
0
—
0
—
ns
RAS to CAS Set-up Time (CAS before RAS) tCSR
10
—
10
—
10
—
10
—
ns
RAS to CAS Hold Time (CAS before RAS)
25
—
25
—
30
—
30
—
ns
tCHR
7/15
¡ Semiconductor
Notes:
MSM511000C/CL
1. A start-up delay of 100 µs is required after power-up, followed by a minimum of
eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before
proper device operation is achieved.
2. The AC characteristics assume tT = 5 ns.
3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals.
Transition times (tT) are measured between VIH and VIL.
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.
tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified
tRCD (Max.) limit, then the access time is controlled by tCAC.
6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.
tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified
tRAD (Max.) limit, then the access time is controlled by tAA.
7. tOFF (Max.) defines the time at which the output achieves the open circuit condition and
is not referenced to output voltage levels.
8. tRCH or tRRH must be satisfied for a read cycle.
9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are
included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then
the cycle is an early write cycle and the data out will remain open circuit (high
impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.),
tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write
cycle and data out will contain data read from the selected cell; if neither of the above
sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.
10. These parameters are referenced to the CAS leading edge in an early write cycle, and
to the WE leading edge in a read modify write cycle.
8/15
E2G0088-17-41A
¡ Semiconductor
MSM511000C/CL
TIMING WAVEFORM
Read Cycle
tRC
tCSH
tCRP
CAS
tRP
tRAS
VIH –
RAS V
IL –
tRCD
VIH –
VIL –
tCRP
tRSH
tCAS
,
,
,
,,
,
tRAD
tASR
Address
VIH –
VIL –
tRAH
tRAL
tCAH
tASC
Row
Column
tAR
tRRH
tRCS
WE
VIH –
VIL –
tRCH
tCAC
tAA
DOUT
VOH –
VOL –
tOFF
tCLZ
tRAC
Open
Valid Data
"H" or "L"
Write Cycle (Early Write)
tRC
tRCD
tCRP
CAS
tRSH
tCSH
VIH –
VIL –
tAR
tASR
tRAH
tRAL
tCAH
tASC
Row
Column
tCWL
tWCR
tWCS
tWCH
VIH –
WE
VIL –
tWP
tRWL
tDHR
tDS
DIN
VIH –
VIL –
DOUT
VOH –
VOL –
tCRP
tCAS
tRAD
Address VIH –
VIL –
tRP
tRAS
VIH –
RAS V –
IL
tDH
Valid Data
Open
"H" or "L"
9/15
¡ Semiconductor
MSM511000C/CL
Read Modify Write Cycle
tRWC
tCRP
CAS
tRP
tRAS
VIH –
RAS
VIL –
tRSH
tRCD
tCRP
tRWL
tCAS
VIH –
VIL –
,,
,
,
,
tASR
Address
VIH –
VIL –
tCSH
tAR
tRAD
tCWL
tRAL
tCAH
tASC
tRAH
Row
Column
tAWD
tRWD
tWP
tCWD
VIH –
WE
VIL –
tRCS
tDS
DIN
VIH –
VIL –
tDH
Valid Data
tCAC
tAA
tOFF
tRAC
DOUT
VOH –
VOL –
Open
Valid Data
tCLZ
"H" or "L"
Fast Page Mode Read Cycle
tRASP
VIH –
RAS
VIL –
tCSH
tRCD
tCRP
CAS
tCAS
VIH –
VIL –
tRAH
tAR
tASC
Row
tASC
tCAH
Column
tRAD
tRCH
VIH –
VIL –
tCAH
tRCS
tCAC
tCRP
tRAC
VOH –
VOL –
Valid
Data
tCLZ
tRAL
tCAH
tASC
Column
tRRH
tRCH
tRCS
tCAC
tAA
DOUT
tRSH
tCAS
tCP
Column
tRCS
WE
tPC
tCAS
tCP
VIH –
VIL –
tASR
Address
tRP
tRHCP
tCAC
tAA
tAA
tCPA
tCPA
tOFF
tCLZ
tRCH
Valid
Data
tOFF
tCLZ
Valid
Data
tOFF
"H" or "L"
10/15
¡ Semiconductor
MSM511000C/CL
Fast Page Mode Write Cycle (Early Write)
tRP
tRASP
RAS
VIH –
VIL –
tRHCP
tCRP
CAS
tCAS
tRCD
VIH –
VIL –
tAR
tASC
tPC
tCAS
tCP
tRSH
tCAS
tCP
tCRP
tRAL
tCAH
,
,
,
,,
tASR
Address VIH –
VIL –
tRAH
Row
tCAH
Column
tRAD
tWCS
tCWL
Column
tWCH
tWCS
tDH
tDS
tWP
tDS
DIN
VIH –
VIL –
tASC
Column
tRWL
tWCR
VIH –
WE
VIL –
tCAH
tASC
Valid Data
tCWL
tWCH
tWP
tCWL
tWCH
tWP
tWCS
tDS
tDH
Valid Data
tDH
Valid Data
tDHR
DOUT
VOH –
VOL –
Open
"H" or "L"
Fast Page Mode Read Modify Write Cycle
tRASP
RAS
VIH –
VIL –
tRHCP
tCSH
tRCD
V
CAS IH –
VIL –
tASR
Address VIH –
VIL –
tAR
tRAH
tASC
Row
WE
tCAH
tAWD
tAA
tRAD
DOUT
DIN
VOH –
VOL –
VIH –
VIL –
tWP
tCAC
tRAC
tCLZ
tOFF
tDH
tDS
Valid
Data
tCAH
tCWL tRCS
tAWD
tCPA
tAA
tCAC
Valid Data
tCRP
tRAL
Column
tCPWD
tCWD
tCWL tRCS
tRP
tCAS
tASC
Column
tRWD
tCWD
VIH –
VIL –
tCP
tCAH
tASC
Column
tRCS
tPRWC
tCAS
tCP
tCAS
tRSH
tWP
tOFF
Valid Data
tCLZ
tDH
tDS
Valid
Data
tCLZ
tCPWD
tCWD
tAWD
tCPA
tAA
tCAC
tCWL
tWP
tOFF
Valid Data
tRWL
tDH
tDS
Valid
Data
"H" or "L"
11/15
,
¡ Semiconductor
MSM511000C/CL
RAS-Only Refresh Cycle
tRC
tRP
tRAS
VIH –
RAS
VIL –
tCRP
CAS
Address
VIH –
VIL –
VIH –
VIL –
tRPC
tRAH
tASR
Row
tOFF
DOUT
VOH –
VOL –
Open
Note: WE = "H" or "L"
"H" or "L"
CAS before RAS Refresh Cycle
tRC
tRAS
RAS
VIH –
VIL –
tRP
tRPC
tCP
tCSR
tCHR
V
CAS IH –
VIL –
tOFF
DOUT
VOH –
VOL –
Open
Note: WE, Address = "H" or "L"
12/15
¡ Semiconductor
MSM511000C/CL
Hidden Refresh Read Cycle
tRC
tRAS
tRP
tRAS
VIH –
RAS
VIL –
tCRP
CAS
tRSH
tRCD
tCHR
VIH –
VIL –
,
,
,,
tRAD
tASR
Address
VIH –
VIL –
tRAL
tRAH
tCAH
tASC
Row
Column
tAR
tRCS
WE
tRRH
VIH –
VIL –
tCAC
tAA
tOFF
tRAC
DOUT
VOH –
VOL –
Valid Data
tCLZ
"H" or "L"
Hidden Refresh Write Cycle
tRC
tRP
tRAS
tRAS
VIH –
RAS
VIL –
tCRP
CAS
tRSH
tRCD
VIH –
VIL –
tAR
tRAD
tASR
Address
VIH –
VIL –
tRAH
tRAL
tCAH
tASC
Row
Column
tRAD
tWCR
tRWL
tWCH
tWCS
WE
VIH –
VIL –
tWP
tDS
DIN
VIH –
VIL –
tCHR
tDH
Valid Data
tDHR
DOUT
VOH –
VOL –
Open
"H" or "L"
13/15
¡ Semiconductor
MSM511000C/CL
PACKAGE DIMENSIONS
(Unit : mm)
SOJ26/20-P-300-1.27
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.80 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
14/15
¡ Semiconductor
MSM511000C/CL
(Unit : mm)
ZIP20-P-400-1.27
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.50 TYP.
15/15
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