Etron EM6A9160TS-3.6G 8m x 16 ddr synchronous dram (sdram) Datasheet

EtronTech
EM6A9160
8M x 16 DDR Synchronous DRAM (SDRAM)
(Rev. 1.4 May/2006)
Pin Assignment (Top View)
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Fast clock rate: 300/275/250/200MHz
Differential Clock CK & /CK
Bi-directional DQS
DLL enable/disable by EMRS
Fully synchronous operation
Internal pipeline architecture
Four internal banks, 1M x 16-bit for each bank
Programmable Mode and Extended Mode registers
- /CAS Latency: 3, 4
- Burst length: 2, 4, 8
- Burst Type: Sequential & Interleaved
Individual byte write mask control
DM Write Latency = 0
Auto Refresh and Self Refresh
4096 refresh cycles / 32ms
Precharge & active power down
Power supplies: VDD & VDDQ = 2.5V ± 5%
Interface: SSTL_2 I/O Interface
Package: 66 Pin TSOP II, 0.65mm pin pitch
Lead-free Package is available.
VDD
1
66
VSS
DQ0
2
3
65
DQ15
VSSQ
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
4
5
6
7
8
9
10
64
63
62
61
60
59
58
57
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
11
12
56
DQ7
NC
13
54
53
DQ8
VDDQ
15
16
52
VSSQ
UDQS
DQ6
VSSQ
LDQS
NC
VDD
NC
LDM
/WE
/CAS
/RAS
/CS
NC
BS0
14
17
18
19
20
21
22
23
24
25
26
55
51
50
49
48
47
46
45
44
43
42
41
DQ9
VDDQ
NC
NC
VREF
VSS
UDM
/CK
CK
CKE
NC
NC
A11
27
28
40
A0
A1
29
38
37
A7
A2
31
32
36
A5
A4
BS1
A10/AP
A3
VDD
30
33
39
35
34
A9
A8
A6
VSS
Ordering Information
Clock Frequency
Data Rate
Package
EM6A9160TS-3.3/3.3G*
Part Number
300MHz
600Mbps/pin
TSOP II
EM6A9160TS-3.6/3.6G
275MHz
550Mbps/pin
TSOP II
EM6A9160TS-4/4G
250MHz
500Mbps/pin
TSOP II
EM6A9160TS-5/5G
200MHz
400Mbps/pin
TSOP II
Note : “G” indicates Pb-free package
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C.
TEL: (886)-3-5782345
FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
EtronTech
EM6A9160
Overview
The EM6A9160 SDRAM is a high-speed CMOS double data rate synchronous DRAM containing 128 Mbits. It is
internally configured as a quad 2M x 16 DRAM with a synchronous interface (all signals are registered on the positive
edge of the clock signal, CK). Data outputs occur at both rising edges of CK and /CK. Read and write accesses to the
SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in
a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a
Read or Write command. The EM6A9160 provides programmable Read or Write burst lengths of 2, 4, or 8. An auto
precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst
sequence. The refresh functions, either Auto or Self Refresh are easy to use. In addition, EM6A9160 features
programmable DLL option. By having a programmable mode register and extended mode register, the system can
choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring
high memory bandwidth, result in a device particularly well suited to high performance main memory and graphics
applications.
2
Rev. 1.4
May 2006
EtronTech
EM6A9160
8Mx16 DDR SDRAM
Block Diagram
CK
/CK
DLL
CLOCK
BUFFER
CONTROL
SIGNAL
GENERATOR
Row Decoder
Column Decoder
2Mx16
CELL ARRAY
(BANK #0)
Sense Amplifier
CK
/CS
/RA
/CA
/WE
COMMAND
DECODER
A10
or
AP
COLUMN
COUNTER
Sense Amplifier
A0
to
A11
BS0
BS1
ADDRESS
BUFFER
Column Decoder
MODE
REGISTER
Row Decoder
Row Decoder
REFRESH
COUNTER
DATA
STROBE
BUFFER
2Mx16
CELL ARRAY
(BANK #1)
2Mx16
CELL ARRAY
(BANK #2)
Sense Amplifier
DQ
BUFFER
DQ0
to
DQ15
Column Decoder
Row Decoder
LDQS
UDQS
Column Decoder
2Mx16
CELL ARRAY
(BANK #3)
Sense Amplifier
LDM
UDM
3
Rev. 1.4
May 2006
EtronTech
8Mx16 DDR SDRAM
EM6A9160
Pin Descriptions
Table 1. Pin Details of EM6A9160
Symbol
Type
Description
CK, /CK
Input
Differential Clock: CK, /CK are driven by the system clock. All SDRAM input signals
are sampled on the positive edge of CK. Both CK and /CK increment the internal
burst counter and controls the output registers.
CKE
Input
Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CK signal. If CKE
goes low synchronously with clock, the internal clock is suspended from the next
clock cycle and the state of output and burst address is frozen as long as the CKE
remains low. When all banks are in the idle state, deactivating the clock controls the
entry to the Power Down and Self Refresh modes.
BS0, BS1
Input
Bank Select: BS0 and BS1 defines to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied.
A0-A11
Input
Address Inputs: A0-A11 are sampled during the BankActivate command (row
address A0-A11) and Read/Write command (column address A0-A8 with A10
defining Auto Precharge).
/CS
Input
Chip Select: /CS enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when /CS is sampled HIGH. /CS
provides for external bank selection on systems with multiple banks. It is considered
part of the command code.
/RAS
Input
Row Address Strobe: The /RAS signal defines the operation commands in
conjunction with the /CAS and /WE signals and is latched at the positive edges of
CK. When /RAS and /CS are asserted "LOW" and /CAS is asserted "HIGH," either
the BankActivate command or the Precharge command is selected by the /WE
signal. When the /WE is asserted "HIGH," the BankActivate command is selected
and the bank designated by BS is turned on to the active state. When the /WE is
asserted "LOW," the Precharge command is selected and the bank designated by BS
is switched to the idle state after the precharge operation.
/CAS
Input
Column Address Strobe: The /CAS signal defines the operation commands in
conjunction with the /RAS and /WE signals and is latched at the positive edges of
CK. When /RAS is held "HIGH" and /CS is asserted "LOW," the column access is
started by asserting /CAS "LOW." Then, the Read or Write command is selected by
asserting /WE "HIGH " or LOW"."
/WE
Input
Write Enable: The /WE signal defines the operation commands in conjunction with
the /RAS and /CAS signals and is latched at the positive edges of CK. The /WE input
is used to select the BankActivate or Precharge command and Read or Write
command.
LDQS,
Input /
UDQS
Output
Bidirectional Data Strobe: Specifies timing for Input and Output data. Read Data
Strobe is edge triggered. Write Data Strobe provides a setup and hold time for data
and DQM. LDQS is for DQ0~7, UDQS is for DQ8~15.
LDM,
Input
Data Input Mask: Input data is masked when DM is sampled HIGH during a write
cycle. LDM masks DQ0-DQ7, UDM masks DQ8-DQ15.
Input /
Output
Data I/O: The DQ0-DQ15 input and output data are synchronized with the positive
edges of CK and /CK. The I/Os are byte-maskable during Writes.
UDM
DQ0 - DQ15
4
Rev. 1.4
May 2006
EtronTech
8Mx16 DDR SDRAM
EM6A9160
VDD
Supply
Power Supply: +2.5V ±5%
VSS
Supply
Ground
VDDQ
Supply
DQ Power: +2.5V ±5%. Provide isolated power to DQs for improved noise immunity.
VSSQ
Supply
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
VREF
Supply
Reference Voltage for Inputs: +0.5*VDDQ
NC
-
No Connect: These pins should be left unconnected.
5
Rev. 1.4
May 2006
EtronTech
EM6A9160
8Mx16 DDR SDRAM
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CK. Table 2
shows the truth table for the operation commands.
Table 2. Truth Table (Note (1), (2) )
Command
State
CKEn-1 CKEn UDM UDM BS0,1 A10 A0-9,11 /CS /RAS /CAS /WE
Idle(3)
H
X
X
X
V
BankPrecharge
L
L
H
H
Any
H
X
X
X
V
L
X
L
L
H
L
PrechargeAll
Any
H
X
X
X
X
Write
Active(3)
H
X
L
L
H
L
H
X
X
X
V
L
L
H
L
L
X
V
H
Column
address
(A0 ~ A8)
Write and AutoPrecharge
Active(3)
H
X
X
L
H
L
L
Read
Active(3)
H
X
X
X
V
L
L
H
L
H
Read and Autoprecharge
Active(3)
H
Mode Register Set
X
X
X
V
H
L
H
L
H
Idle
Extended MRS
H
X
X
X
OP code
L
L
L
L
Idle
H
X
X
X
OP code
L
L
L
L
No-Operation
Any
H
X
X
X
X
X
X
L
H
H
H
Active(4)
H
X
X
X
X
X
X
L
H
H
L
Device Deselect
Any
H
X
X
X
X
X
X
H
X
X
X
AutoRefresh
Idle
H
H
X
X
X
X
X
L
L
L
H
SelfRefresh Entry
Idle
H
L
X
X
X
X
X
L
L
L
H
Idle
L
H
X
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
H
X
X
X
L
H
H
H
X
X
X
X
Active
H
X
H
H
X
X
X
X
Note: 1. V=Valid data, X=Don't Care, L=Low level, H=High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. LDM and UDM can be enable respectively.
X
X
X
BankActivate
Burst Stop
SelfRefresh Exit
Row address
Column
address
(A0 ~ A8)
(SelfRefresh)
Precharge Power Down Mode
Entry
Precharge Power Down Mode
Exit
Active Power Down Mode
Entry
Active Power Down Mode Exit
Idle
Any
H
L
L
X
H
X
X
X
X
X
X
X
X
X
(PowerDown)
Active
Any
H
L
L
X
H
X
X
X
X
X
X
X
X
X
(PowerDown)
Data Input Mask Disable
Active
H
X
L
L
X
X
X
Data Input Mask Enable(5)
6
Rev. 1.4
May 2006
EtronTech
EM6A9160
8Mx16 DDR SDRAM
Mode Register Set (MRS)
The mode register is divided into various fields depending on functionality.
Burst Length Field (A2~A0)
•
This field specifies the data length of column access using the A2~A0 pins and selects the
Burst Length to be 2, 4, 8.
•
A2
A1
A0
Burst Length
0
0
0
Reserved
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
Addressing Mode Select Field (A3)
The Addressing Mode can be one of two modes, both Interleave Mode or Sequential Mode.
Both Sequential Mode and Interleave Mode support burst length of 2,4 and 8.
A3
Addressing Mode
0
Sequential
1
Interleave
--- Addressing Sequence of Sequential Mode
An internal column address is performed by increasing the address from the column
address which is input to the device. The internal column address is varied by the Burst
Length as shown in the following table.
Data n
0
1
2
3
4
5
6
7
Column Address
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
2 words
Burst Length
4 words
8 words
Full Page (Even starting address)
--- Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the
address bits in the sequence shown in the following table.
Data n
Column Address
Burst Length
Data 0
A7
A6
A5
A4
A3
A2
A1
A0
Data 1
A7
A6
A5
A4
A3
A2
A1
A0#
Data 2
A7
A6
A5
A4
A3
A2
A1# A0
Data 3
A7
A6
A5
A4
A3
A2
A1# A0#
Data 4
A7
A6
A5
A4
A3
A2# A1
A0
Data 5
A7
A6
A5
A4
A3
A2# A1
A0#
Data 6
A7
A6
A5
A4
A3
A2# A1# A0
Data 7
A7
A6
A5
A4
A3
A2# A1# A0#
7
4 words
8 words
Rev. 1.4
May 2006
EtronTech
•
•
•
8Mx16 DDR SDRAM
EM6A9160
CAS Latency Field (A6~A4)
This field specifies the number of clock cycles from the assertion of the Read command to
the first read data. The minimum whole value of CAS Latency depends on the frequency of
CK. The minimum whole value satisfying the following formula must be programmed into this
field. tCAC(min) ≤ CAS Latency X tCK
A6
A5
A4
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
Reserved
0
1
1
3 clocks
1
0
0
4 clocks
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
Test Mode field (A8~A7)
These two bits are used to enter the test mode and must be programmed to "00" in normal
operation.
A8
A7
Test Mode
0
0
Normal mode
1
0
DLL Reset
X
1
Test mode
( BS0, BS1)
BS1
BS0
An ~ A0
RFU
0
MRS Cycle
RFU
1
Extended Functions (EMRS)
8
Rev. 1.4
May 2006
EtronTech
EM6A9160
8Mx16 DDR SDRAM
Extended Mode Register Set (EMRS)
The Extended Mode Register Set stores the data for enabling or disabling DLL and selecting output driver
strength. The default value of the extended mode register is not defined, therefore must be written after power
up for proper operation. The extended mode register is written by asserting low on CS#, RAS#, CAS#, and
WE#. The state of A0, A2 ~ A5, A7 ~ A11and BS1 is written in the mode register in the same cycle as CS#,
RAS#, CAS#, and WE# going low. The DDR SDRAM should be in all bank precharge with CKE already high
prior to writing into the extended mode register. A1 and A6 are used for setting driver strength to normal, weak
or matched impedance. Two clock cycles are required to complete the write operation in the extended mode
register. The mode register contents can be changed using the same command and clock cycle requirements
during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BS0
is used for EMRS. Refer to the table for specific codes.
Extended Mode Resistor Bitmap
BS1
0
BS0
1
BS0 Mode
0
MRS
1 EMRS
A11
A6
0
0
1
1
A10
A9
A8
RFU must be set to “0”
A7
A6
DS1
A5
A4
A3
A2
RFU must be set to “0”
A1
Drive Strength
Strength
Comment
0
Full
100%
1
SSTL-2 weak
60%
0
RFU
RFU Reserved For Future
1 Matched impedance 30% Output driver matches impedance
9
Rev. 1.4
A1
DS0
A0
DLL
A0
DLL
0
Enable
1 Disable
May 2006
EtronTech
EM6A9160
8Mx16 DDR SDRAM
Absolute Maximum Rating
Symbol
Item
Rating
-3.3/3.6/4/5
Unit
Note
-3.3G/3.6G/4G/5G
VIN, VOUT
Input, Output Voltage
- 0.3~ VDD + 0.3
V
1
VDD, VDDQ
Power Supply Voltage
- 0.3~3.6
V
1
TOPR
Operating Temperature
0~70
°C
1
TSTG
Storage Temperature
- 55~150
°C
1
TSOLDER
Soldering Temperature
°C
1
245
260
PD
Power Dissipation
1
W
1
IOUT
Short Circuit Output Current
50
mA
1
Recommended D.C. Operating Conditions (Ta = 0 ~ 70 °C)
Parameter
Symbol
Min.
Max.
Unit
Power Supply Voltage
VDD
2.375
2.625
V
Power Supply Voltage (for I/O Buffer)
VDDQ
2.375
2.625
V
Input Reference Voltage
VREF
0.49* VDDQ
0.51* VDDQ
V
Termination Voltage
Note
VTT
VREF - 0.04
VREF + 0.04
V
Input High Voltage (DC)
VIH (DC)
VREF + 0.15
VDDQ + 0.3
V
Input Low Voltage (DC)
VIL (DC)
-0.3
VREF – 0.15
V
Input Voltage Level, CLK and CLK#
inputs
VIN (DC)
-0.3
VDDQ + 0.3
V
II
-5
5
µA
Output leakage current
IOZ
-5
5
µA
Output High Voltage
VOH
VTT + 0.76
-
V
IOH = -15.2 mA
Output Low Voltage
VOL
VTT – 0.76
V
IOL = +15.2 mA
Input leakage current
10
Rev. 1.4
May 2006
EtronTech
EM6A9160
8Mx16 DDR SDRAM
Capacitance (VDD = 2.5V, f = 1MHz, Ta = 25 °C)
Symbol
CIN
CI/O
Parameter
Min.
Max.
Unit
Input Capacitance (except for CK pin)
2.5
4
pF
Input Capacitance (CK pin)
2.5
4
pF
DQ, DQS, DM Capacitance
4
6.5
pF
Note: These parameters are periodically sampled and are not 100% tested.
11
Rev. 1.4
May 2006
EtronTech
EM6A9160
8Mx16 DDR SDRAM
Recommended D.C. Operating Conditions (VDD = 2.5V ± 5%, Ta = 0~70 °C)
Parameter & Test Condition
Symbol
OPERATING CURRENT : One bank; Active-Precharge;
tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs
changing once per clock cycle; Address and control
inputs changing once every two clock cycles.
OPERATING CURRENT : One bank; Active-ReadPrecharge; BL=4; CL=4; tRCDRD=4*tCK; tRC=tRC(min);
tCK=tCK(min); lout=0mA; Address and control inputs
changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT:
All banks idle; power-down mode; tCK=tCK(min);
CKE=LOW
IDLE STANDLY CURRENT : CKE = HIGH;
CS#=HIGH(DESELECT); All banks idle; tCK=tCK(min);
Address and control inputs changing once per clock
cycle; VIN=VREF for DQ, DQS and DM
ACTIVE POWER-DOWN STANDBY CURRENT : one
bank active; power-down mode; CKE=LOW;
tCK=tCK(min)
ACTIVE STANDBY CURRENT :
CS#=HIGH;CKE=HIGH; one bank active ;
tRC=tRC(max);tCK=tCK(min);Address and control inputs
changing once per clock cycle; DQ,DQS,and DM inputs
changing twice per clock cycle
OPERATING CURRENT BURST READ : BL=2; READS;
Continuous burst; one bank active; Address and control
inputs changing once per clock cycle; tCK=tCK(min);
lout=0mA;50% of data changing on every transfer
OPERATING CURRENT BURST Write : BL=2;
WRITES; Continuous Burst ;one bank active; address
and control inputs changing once per clock cycle;
tCK=tCK(min); DQ,DQS,and DM changing twice per clock
cycle; 50% of data changing on every transfer
AUTO REFRESH CURRENT : tRC=tRFC(min);
tCK=tCK(min)
SELF REFRESH CURRENT: Sell Refresh Mode ;
CKE<=0.2V;tCK=tCK(min)
BURST OPERATING CURRENT 4 bank operation:
Four bank interleaving READs; BL=4;with Auto
Precharge; tRC=tRC(min); tCK=tCK(min); Address and
control inputschang only during Active, READ , or WRITE
command
12
3.3 3.6 4
Max
5
Unit Notes
IDD0
200 180 160 140 mA
IDD1
220 200 180 160 mA
IDD2P
50
45
40
35 mA
IDD2N 110 100
90
80 mA
IDD3P
40
35 mA
IDD3N 120 110 100
90 mA
50
45
IDD4R 340 310 280 250 mA
IDD4W 280 260 240 220 mA
IDD5
IDD6
IDD7
270 250 230 210 mA
2
2
2
2
mA
440 400 360 330 mA
Rev. 1.4
May 2006
EtronTech
EM6A9160
8Mx16 DDR SDRAM
Electrical AC Characteristics (VDD = 2.5 ± 5%, Ta = 0~70 °C)
Symbol
3.3
Parameter
CL = 3
CL = 4
3.6
4.0
5.0
Min
Max
Min
Max
Min
Max
Min
Max
3.3
10
3.6
-
10
-
4
-
10
-
5
-
10
-
tCK
Clock cycle time
tCH
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tWPST
tDQSH
tDQSL
tIS
tIH
tDS
tDH
Clock high level width
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
Clock low level width
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
DQS-out access time from CK,CK#
-0.6
0.6
-0.6
0.6
-0.6
0.6
-0.7
0.7
Output access time from CK,CK#
-
0.4
-
0.4
-
0.45
-
tCLMIN
or
tCHMIN
-
tCLMIN
or
tCHMIN
-
tCLMIN
or
tCHMIN
-
tCLMIN
or
tCHMIN
-
ns
tHP 0.35
-
tHP 0.4
-
tHP 0.4
-
tHP 0.45
-
ns
-
15
-
13
-
12
-
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
us
-0.6
0.6
-0.6
0.6
-0.6
0.6
-0.7
0.7
-
0.35
-
0.4
-
0.4
-
0.45
Read preamble
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
Read postamble
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
CK to valid DQS-in
0.85
1.15
0.85
1.15
0.85
1.15
0.85
1.15
DQS-in setup time
0
-
0
-
0
-
0
-
DQS-in hold time
0.35
-
0.35
-
0.35
-
0.3
-
DQS write postamble
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
DQS in high level pulse width
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
DQS in low level pulse width
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
Address and Control input setup time
0.9
-
0.9
-
0.9
-
1.0
-
Address and Control input hold time
0.9
-
0.9
-
0.9
-
1.0
-
DQ & DM setup time to DQS
0.35
-
0.4
-
0.4
-
0.45
-
0.35
tHP
Clock half period
tQH
Output DQS valid window
tRC
tRFC
tRAS
tRCDRD
tRCDWR
tRP
tRRD
twR
tCDLR
tCCD
tMRD
tDAL
tXSA
tPDEX
tREF
Row cycle time
15
Refresh row cycle time
17
-
17
-
15
-
14
-
Row active time
10
100K
10
100K
9
100K
8
100K
RAS# to CAS# Delay in Read
5
-
5
-
4
-
4
-
RAS# to CAS# Delay in Write
3
-
3
-
2
-
2
-
Row precharge time
5
-
5
-
4
-
4
-
Row active to Row active delay
3
-
3
-
3
-
3
-
Write recovery time
3
-
3
-
3
-
3
-
Last data in to Read command
3
-
2
-
2
-
2
-
Col. Address to Col. Address delay
1
-
1
-
1
-
1
-
Mode register set cycle time
2
-
2
-
2
-
2
-
Auto precharge write recovery + Precharge
Self refresh exit to read command delay
ns
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
ns
ns
ns
ns
DQS-DQ Skew
DQ & DM hold time to DQS
Unit
8
-
8
-
7
-
7
-
200
-
200
-
200
-
200
-
tCK + tIS
-
tCK + tIS
-
7.8
-
7.8
Power down exit time
tCK + tIS
-
tCK + tIS
-
Refresh interval time
-
7.8
-
7.8
13
Rev. 1.4
May 2006
EtronTech
EM6A9160
8Mx16 DDR SDRAM
Recommended A.C. Operating Conditions (VDD = 2.5 ± 5%, Ta = 0~70 °C)
Parameter
Symbol
Min.
Max.
Unit
Input High Voltage (DC)
VIH (AC)
VREF + 0.35
Input Low Voltage (DC)
VIL (AC)
VREF – 0.35
V
Input Different Voltage, CLK and CLK#
inputs
VID (AC)
0.7
VDDQ + 0.6
V
Input Crossing Point Voltage, CLK and
CLK# inputs
VIX (AC)
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
Note
V
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device.
2. All voltages are referenced to VSS.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during tCK.
4. Power-up sequence is described in Note 6.
5. A.C. Test Conditions
SSTL_2 Interface
Reference Level of Output Signals (VRFE)
0.5 * VDDQ
Output Load
Reference to the Under Output Load (A)
Input Signal Levels
VREF+0.35 V / VREF-0.35 V
Input Signals Slew Rate
1 V/ns
Reference Level of Input Signals
0.5 * VDDQ
0.5*VDDQ
25 Ω
25Ω
Output
30pF
SSTL_2 A.C. Test Load
6.
Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to VDD and VDDQ(simultaneously) when all input signals are held "NOP" state
and maintain CKE “LOW”. Power applied to VDDQ the same time as VTT and VREF.
14
Rev. 1.4
May 2006
EtronTech
8Mx16 DDR SDRAM
EM6A9160
2) After power-up, No-Operation of 200 µ−seconds minimum is required.
3) Start clock and keep CKE “HIGH” to maintain either No-Operation or Device Deselect at the input.
4) Issue EMRS – enable DLL.
5) Issue MRS – reset DLL and set device to idle with bit A8 (An additional 200 cycles min of clock are
needed for DLL lock)
6) Precharge all banks of the device.
7) Two or more Auto Refresh commands.
8) Issue MRS – Initialize device operation.
15
Rev. 1.4
May 2006
EtronTech
8Mx16 DDR SDRAM
EM6A9160
Timing Waveforms
Figure 1. AC Parameters for Write Timing (Burst Length=4)
CK
/CK
CMD
Write
ADDR
/CS
DQ
D0
D1
D2
D3
tDH
tWPRES
tDS
tDQSS
tDSL
tDSH
t WPST
DQS
Preamble
Postamble
16
Rev. 1.4
May 2006
EtronTech
EM6A9160
8Mx16 DDR SDRAM
Figure 2. Read Command to Output Data Latency (Burst Length=2)
CK
/CK
CMD
Read
CL=2
DQ
DA0
DA1
Postamble
DQS
Preamble
CL=2.5
DQ
DA0
DA1
Postamble
DQS
Preamble
CL=3
DQ
DA0
DA1
Postamble
DQS
Preamble
17
Rev. 1.4
May 2006
EtronTech
8Mx16 DDR SDRAM
EM6A9160
Figure 3. Read Followed by Write (Burst Lenth=4, CAS Latency=3)
CK
/CK
tRRD
tRCDR
Activate
CMD
Read
Write
ACT
ADDR
Row/Bank0
Col/Bank0 Rol/Bank1
Col/Bank0
/CS
DQ
DQS
D0
D1
D2
D3
Preamble
Postamble
18
Rev. 1.4
May 2006
EtronTech
8Mx16 DDR SDRAM
EM6A9160
Figure 4. Write followed by Read (Burst Lenth=4, CAS Latency=3)
CK
/CK
t WTR
CMD
Write
Read
ADDR
Col
Col
/CS
DQ
D0
D1
D2
D0
D3
D1
D2 D3
DQS
19
Rev. 1.4
May 2006
EtronTech
EM6A9160
8Mx16 DDR SDRAM
Figure 5. Precharge Termination of a Burst Read (Burst Length=4, CAS Latency=3)
CK
/CK
Precharge
CMD
ADDR
ACT
Read
Col
Bank
Bank
/CS
tRP
DQ
DQS
D0
D1
Preamble
Postamble
20
Rev. 1.4
May 2006
EtronTech
EM6A9160
8Mx16 DDR SDRAM
Figure 6. Precharge Termination of a Burst Write (Burst Length=4)
CK
/CK
tRC
Activate
Write
Precharge
Activate
CMD
ADDR
Row/Bank
Col/Bank
Row/Bank
Row/Bank
/CS
tRCD
tWR
DQM
tRP
tDS
tQDH
tRAS
DQ
D0
D1
masked by DQM
DQS
Preamble
Postamble
21
Rev. 1.4
May 2006
EtronTech
8Mx16 DDR SDRAM
EM6A9160
Figure 7. Auto Precharge after Read Burst (CAS Latency=3)
CK
/CK
tRP
BL=2
CMD
Auto Precharge
ReadA
DQ
ACT
D0
D1
tRP
Auto Precharge
BL=4
CMD
ACT
ReadA
DQ
D0
D1
D2
D3
tRP
BL=8
CMD
DQ
Auto Precharge
ACT
ReadA
D0
D1
D2
D3 D4 D5
D6
D7
22
Rev. 1.4
May 2006
EtronTech
8Mx16 DDR SDRAM
EM6A9160
Figure 8. Auto Precharge after Write Burst
CK
/CK
BL=2
WriteA
Auto Precharge
ACT
CMD
t WR
tRP
D0 D1
DQ
Preamble
DQS
BL=4
Postamble
WriteA
Auto Precharge
ACT
CMD
t WR
D0 D1 D2
DQ
tRP
D3
Preamble
DQS
BL=8
Postamble
Auto Precharge
WriteA
ACT
CMD
tWR
DQ
D0 D1
D2 D3
D4 D5
tRP
D6 D7
Preamble
DQS
Postamble
23
Rev. 1.4
May 2006
EtronTech
8Mx16 DDR SDRAM
EM6A9160
Figure 9. Read Terminated By Burst Stop (Burst Length=8)
CK
/CK
CMD
ADDR
Read
BST
Col
/CS
CL=3
DQ
D0
D1
D2
D3
DQS
24
Rev. 1.4
May 2006
EtronTech
EM6A9160
8Mx16 DDR SDRAM
Figure 10. Read Terminated by Read (Burst Length=4, CAS Latency=3)
CK
/CK
tCCD
CMD
Read
Read
ADDR
Col A
Col B
/CS
DA0
DQ
DA1
DB0
DB1
DB2
DB3
DQS
25
Rev. 1.4
May 2006
EtronTech
8Mx16 DDR SDRAM
EM6A9160
Figure 11. Mode Register Set Command
CK
/CK
tRP
1 clk
MRS
CMD
ACT
Precharge
Row
ADDR
MRS Data
/CS
26
Rev. 1.4
May 2006
EtronTech
EM6A9160
8Mx16 DDR SDRAM
Figure 12. Active / Precharge Power Down Mode
CK
/CK
tPDEX
t IS
CKE
Any
Command
CMD
Activate /
Precharge
Note 1,2
Note:
1. All banks should be in idle state prior to entering precharge power down mode.
2. One of the banks should be in active state prior to entering active power down mode.
27
Rev. 1.4
May 2006
EtronTech
8Mx16 DDR SDRAM
EM6A9160
Figure 13. Self Refresh Entry and Exit Cycle
CK
/CK
Self Refresh Enter
CMD
Auto
Refresh
NOP
tRC
CKE
t IS
Self Refresh Exit
tRC is required before any command can be applied,
and 200 cycles of clk are required before a READ
command can be applied.
28
Rev. 1.4
May 2006
EtronTech
EM6A9160
8Mx16 DDR SDRAM
66 Pin TSOP II Package Outline Drawing Information
Units: mm
22.22 0.13
66
0.085
0.125 +- 0.005
0.5 0.1
10.16 0.13
11.76 0.20
0.8 TYP
34
1.00 0.10
1.20 MAX
33
1
0~8
0.65 TYP
0.10 MAX
0.30 0.08
0.05 MIN
0.71 TYP
29
0.25 TYP
Rev. 1.4
May 2006
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