Mitsubishi M66244FP High speed monolithic pulse width modulator Datasheet

PRELIMINARY DATA SHEET
MITSUBISHI <DIGITAL ASSP>
M66244FP
June 1998
Ver.8.0.0
High Speed Monolithic Pulse Width Modulator
NOTE:This is not final specification. Some parametric limits are subject to change
DESCRIPTION
The M66244FP is a high-speed digitally programmable pulse width modulator (PWM) which
uses high-performance silicon gate CMOS process technology.Output pulse width is
proportional to a 6-bit DATA input value. Two additional CONTROL inputs determine if the
pulse is placed at the beginning , middle ,or end of the clock period. Pulse width and
placement can be changed every clock cycle up to 72MHz.
FEATURES
• Frequency
45MHz to 72MHz
• 6 bit Resolution
• Center, Leading, Trailing Edge Modulation
• Single 3.3V Operation
• JTAG (IEEE Standard 1149.1Test Port)
APPLICATIONS
• Laser Printers
Gray Scale Capability
Resolution Enhancement
• Copiers
• Optical Disk Drives
• Precision Pulse Placement
PIN CONFIGURATION (TOP VIEW)
TEST PIN
(JTAG)
TEST CLOCK INPUT
TCK
1
36
TDI
TEST DATA INPUT
TEST MODE INPUT
TMS
2
35
TDO
TEST DATA OUTPUT
TEST RESET INPUT
TRST
3
34
GND
GND
4
33
CLK
VDD
5
32
VDD
GND
6
31
RESET
RESET INPUT
VDD
7
30
SET
SET INPUT
GND
8
29
VDD
VDD
9
28
GND
GND
10
27
PWMOUT
VDD
11
26
VDD
GND
12
25
GND
VDD
13
24
D0(LSB)
FRANGE1
14
23
D1
FRANGE2
15
22
D2
16
21
D3
SEM/DEM
17
20
D4
LEM/TEM
18
19
D5(MSB)
FREQUENCY
RANGE SET INPUT
LINE SIGNAL INPUT
PULSE MODE
CONTROL
INPUT
LS
Outline
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36P2R
CLOCK INPUT
DATA BUS
INPUT
TEST PIN
(JTAG)
MITSUBISHI <DIGITAL ASSP>
M66244FP
June 1998
Ver.8.0.0
High Speed Monolithic Pulse Width Modulator
BLOCK DIAGRAM
RESET
31
BSR
SET
30
BSR
D0(LSB)
24
BSR
D1
23
BSR
D2
22
BSR
D3
21
BSR
D4
20
BSR
D5(MSB)
19
BSR
LEM/TEM
18
BSR
SEM/DEM
17
BSR
16
BSR
FRANGE2
15
BSR
FRANGE1
14
BSR
LS
27
PWM OUT
PULSE WIDTH
and MODE
CONTROL
CIRCUIT
PULSE
GENERATE
CIRCUIT
33
CLK
JTAG Block
TDI
36
TRST
3
ID register
Bypass register
35
TDO
Instruction register
TMS
2
TCK
1
TAP Contoroller
PIN DESCRIPTION
PIN NAME
NAME
D0-D5
CLK
Digital Data Bit
Clock input
normal Input
normal Input
DESCRIPTION
6 bit Digital Data from MPU
Dot Clock input
PWM OUT
PWM output
normal output
PWM output
SEM/DEM
LEM/TEM
Control output
pulse mode
normal Input
Control pin of output pulse mode (refer to page 3)
normal Input
When SET is "H", PWM output is "H" (direct set )
When SET is "L", PWM output depend on D<5:0>
When RESET is "L", M66244FP is reset to initial state.
SET
RESET
LS
Set input
Reset input
Line Signal input
FRANGE1 Operation Frequency
FRANGE2 range set up
IN/OUT buffer type
schmitt Input (Pull-up 50kΩ)
normal Input
refer to page 10
normal Input
FRANGE1 and FRANGE2 are set up correspond to
operation frequency range (refer to page 8)
TRST
Test Reset input
TMS
Test Mode Select input normal Input (Pull-up 50kΩ)
TCK
Test Clock input
schmitt Input(Pull-down 50kΩ) Test Clock input of JTAG test circuit
TDI
Test Data In input
normal Input (Pull-up 50kΩ)
TDO
Test Data Out output
schmitt Input (Pull-up 50kΩ)
3-sate output
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Test Reset input of JTAG test circuit
Test Mode Select input of JTAG test circuit
Test Data input of JTAG test circuit
Test Data output of JTAG test circuit
MITSUBISHI <DIGITAL ASSP>
M66244FP
June 1998
Ver.8.0.0
High Speed Monolithic Pulse Width Modulator
FUNCTION
M66244 can control "H" width and positioning of PWM output by DATA pins (D<5:0> ) and
CONTROL pins (SEM/DEM,LEM/TEM) in each CLK period.
These inputs can be updated on the rising edge of the CLK.
Positioning the width-controlled pulse are begging , middle ,or end of the clock period.
This is accomplished through CONTROL pins (SEM/DEM,LEM/TEM)
Pulse positioning within the clock period is defined by the following CONTROL truth table.
SEM/DEM
1
1
0
LEM/TEM
1
0
X
Alignment
Right hand justify
Left hand justify
Center justify
SEM/DEM : single edge modulation / dual edge modulation
LEM/TEM : leading edge modulation / trailing edge modulation
The diagram of page4 illustrates the output of the M66244FP with various DATA(D<5:0>) ,
CONTROL(SEM/DEM, LEM/TEM) inputs and PWM output.
This does not take into account any delays,which will explain later.
The rising edge is delayed from the leading edge of the clock, and the falling edge is delayed
from the center of the clock period.
Top line shows the clock; the second shows DATA inputs ; third shows CONTROL inputs
being updated on the rising edge of clock. The forth line shows the resulting PWM pulse with an
explanation of the second and third lines.
In the first cycle (Ncycle) , DATA is 3F . So the CONTROL value is shown as "X". This
means the value is not important because a 100% pulse will be output for any CONTROL value.
In the second cycle (N+1cycle) , DATA is 1F , SEM/DEM is "H" and LEM/TEM is "H". This
means PWMoutput width is 50% and positioning is right hand justify.
In the third cycle (N+2cycle) , DATA is 0F , SEM/DEM is "L" and LEM/TEM is "X". This means
PWMoutput width is 25% and positioning is center justify.
In the fourth cycle (N+3cycle) , DATA is 2F , SEM/DEM is "H" and LEM/TEM is "L". This
means PWMoutput width is 75% and positioning is left hand justify.
In the fifth cycle (N+4cycle) , DATA is 00 . So the CONTROL value is shown "X" . This means
the value is not important because a 0% pulse will be output for any CONTROL value.
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MITSUBISHI <DIGITAL ASSP>
M66244FP
June 1998
Ver.8.0.0
High Speed Monolithic Pulse Width Modulator
PWM OUTPUT EXAMPLE
N
N+2
N+1
N+4
N+3
CLK
D<0:5>
3F
1F
0F
2F
00
3F
SEMDEM
LEM/TEM
N+1
N
N+3
N+2
PWMOUT
100%
50%
Right hand justify
25%
75%
0%
Left hand justify
Center hand justify
PWM Pulse linearity (image figure)
(1) In case of next pulse is "H"
(2) In case of next pulse is "L"
100
100
Minimum
"L" Pulse
Width
Liner region
Liner region
Minimum
"H" Pulse
Width
Minimum
"H" Pulse
Width
Change of linearity
0
Change of linearity
0
0
Code (Dec)
63
0
Code (Dec)
63
CLK
Next Pulse
PWMOUT
"L"
Minimum
"H" Pulse
Width
Next Pulse
"L"
"H"
Minimum
"H" Pulse
Width
Minimum
"L" Pulse
Width
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"L"
MITSUBISHI <DIGITAL ASSP>
M66244FP
June 1998
Ver.8.0.0
High Speed Monolithic Pulse Width Modulator
OPERATING TIMING BETWEEN POWER ON TO NORMAL OPERATION
After Power on, it needs following oerations before start normal operation.
(1) Set the value of FRANGE1 and FRANGE2 depends on operation ferequency. (Refer to page 9)
(2) Input CLK same as normal operarion frequency.
(3) Reset operarion using RESET (31pin) and TRST (3pin) .
(reset to initial state of internal logic and BSR)
(4) CLK continue to input during 100msec.
set up period
of internal circuit
Power ON
normal operation
period
reset cycle
100msec
RESET
tsu(RESET)
th(RESET)
TRST
CLK
FRANGE1
Fixed value determined page9
FRANGE2
Fixed value determined page9
n
n+1
n+2
SEM/DEM
n
n+1
n+2
LEM/TEM
n
n+1
n+2
D<5:0>
td(PWM)
n
PWMOUT
Note:
The reset cycle requires a minimum of two cycles.
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N cycle
output
MITSUBISHI <DIGITAL ASSP>
June 1998
M66244FP
Ver.8.0.0
OPERATING TIMING
High Speed Monolithic Pulse Width Modulator
EXAMPLE
DATA(D<0:5>) and CONTROL(SEM/DEM,LEM/TEM) are written to the latching circuit at the
first rise edge of CLK. PWMOUT is outputted at the next edge of CLK. A propagation delay
exists between the CLK and PWMOUT pulse. The minimum propagation delay can be observed
when alternating between codes 00(H) and 3F(H).
In the following diagram, when SET is "H" , PWM output is "H" , when SET is "L" , PWMOUT is
determined correspond to D<5:0>. The function of SET is direct set, so when the rise edge of
CLK and SET are entered at the same time PWMOUT will be "H" .
tw(SET)
SET
tw(CLK)
CLK
N cycle
tsu(D)
n
tsu(LT)
LEM/TEM
N+3 cycle
N+4 cycle
n+1
n+2
n+3
n+3
n+1
n+2
n+3
n+3
n+1
n+2
n+3
n+3
th(SD)
tsu(SD)
SEM/DEM
N+2 cycle
th(D)
n
D<5:0>
N+1 cycle
th(LT)
n
td(PWM)
td(PWM)
td(SET)
td(SET)
n
PWMOUT
N
cycle output
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"H"
n+3
N+3
cycle output
MITSUBISHI <DIGITAL ASSP>
M66244FP
June 1998
Ver.8.0.0
High Speed Monolithic Pulse Width Modulator
TIMING CONDITIONS (Ta=0~ 70˚C,Vcc=3.3V±5%, GND=0V)
Symbol
Parameter
tw(CLK)
Clock cycle
duty(CLK)
Clock duty
Min.
Typ.
14
tsu(RESET)
RESET setup time to CLK
6
th(RESET)
RESET hold time to CLK
6
tw(SET)
SET pulse width
Max.
Unit
22
ns
±7
%
ns
ns
ns
14
6
6
6
tsu(D)
th(D)
tsu(SD)
th(SD)
Input data setup time to CLK
Input data hold time to CLK
SEM/DEM setup time to CLK
SEM/DEM hold time to CLK
tsu(LT)
th(LT)
LEM/TEM setup time to CLK
LEM/TEM hold time to CLK
tr / tf
Input pulse rise / fall time
tw(TCK)
TCK cycle
50
ns
tsu(TDI)
TDI setup time to CLK
TDI hold time to CLK
10
ns
10
ns
10
ns
th(TMS)
TMS setup time to CLK
TMS hold time to CLK
10
ns
tw(TRST)
TRST pulse width
20
ns
th(TDI)
tsu(TMS)
ns
ns
ns
ns
6
6
ns
ns
6
2
ns
SWITCHING CHARACTERISTICS (Ta=0~ 70˚C,Vcc=3.3V±5%, GND=0V)
Symbol
Parameter
Min.
Typ.
Max.
Unit
td (PWM)
PWM output access time
40
ns
td (SET)
"H" output access time
20
ns
td (TDO)
TDO access time
40
ns
OUTPUT PULSE LINEARITY (Ta=0~ 70˚C,Vcc=3.3V±5%, GND=0V)
Symbol
Parameter
Min.
Typ.
Max.
Unit
DLV
Differential linearity by voltage change
4
%
DLT
Differential linearity by temperature change
4
%
DLW
Differential linearity by wafer lot change
4
%
Pw+(min)
Minimum "H" pulse width
(@CL=10pF)
4
ns
Pw
Minimum "L" pulse width
(@CL=10pF)
4
ns
(max)
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MITSUBISHI <DIGITAL ASSP>
M66244FP
June 1998
Ver.8.0.0
High Speed Monolithic Pulse Width Modulator
ABSOLUTE MAXIMUM RATINGS (Ta=0~70˚C unless otherwise noted)
Symbol
Conditions
Parameter
Ratings
Unit
V
V
Vcc
Supply voltage
-0.3~+4.6
VI
Input voltage
Output voltage
A value based GND pin
-0.3~VCC+0.3
Ta = 70 ˚C
-0.3~VCC+0.3
414
Vo
Pd
Tstg
Maximum power dissipation
Storage temperature
V
mW
˚C
-55~150
RECOMMENDED OPERATING CONDITIONS
Symbol
Limits
Parameter
Vcc
GND
Supply voltage
Supply voltage
Topr
Operating ambient temperature
Min.
Typ.
Max.
3.15
3.3
0
3.45
Unit
V
V
0~70
˚C
ELECTRICAL CHARACTERISTICS (Ta=0~70˚C, Vcc=3.3V±5%,GND=0V unless otherwise noted)
Symbol
VIH
VIL
VTVT+
VH
Parameter
"H" Input voltage
for normal type input
"L" Input voltage
for normal type input
Negative going threshold voltage
for schmitt type input
positive going threshold voltage
for schmitt type input
Hysteresis
for schmitt type input
Limits
Conditions
Min.
D0~D5, LEM/TEM ,LS
SEM//DEM, CLK, SET,
FRANGE1, FRANGE2
Typ.
Max.
Unit
V
Vcc x 0.8
0.8
V
0.5
1.65
V
1.4
2.4
V
TCK, TRST, RESET
Vcc=3.3V
V
0.75
VOH
"H" Output voltage
IOH=-2mA
VOL
"L" Output voltage
IOL=2mA
0.55
V
10
µA
-10
µA
IIH
"H" Input current
VI=Vcc
IIL
"L" Input current
VI=GND
V
2.0
IOZH
Off state "H" output current
Vo=Vcc
TDO
10
µA
IOZL
Off state "L" output current
Vo=GND
TDO
-10
µA
f=72MHz , CL=10pF
120
mA
f=1MHz
10
pF
f=1MHz
15
pF
Icc
CI
CO
Operating mean
current dissipation
Input capacitance
Off state output capacitance
Note 1 : under consideration
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M66244FP
June 1998
Ver.8.0.0
High Speed Monolithic Pulse Width Modulator
SETTING OF OPERATING FREQUENCY RANGE
M66244FP can operate between 45MHz to 72MHz of clock frequency, it needs to set the value
of the FRANGE1 and FRANGE2 correspond to operating frequency.
Frequency range
FRANGE1
FRANGE2
45MHz~50MHz
L
H
50MHz~60MHz
H
L
60MHz~72MHz
H
H
TIMING of PROPAGATION DELAY and THRESHOLD VOLTAGE of PULSE WIDTH
CLK
3.0V
1.3V
0V
td(PWM)
VOH
1.3V
PWMOUT
VOL
tw(PWM)
3.0V
SET
1.3V
0V
td(SET)
VOH
PWMOUT
1.3V
"H"
NOTE : OUTPUT LOAD 10pF
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VOL
MITSUBISHI <DIGITAL ASSP>
M66244FP
June 1998
Ver.8.0.0
High Speed Monolithic Pulse Width Modulator
Solution for clock period is shifted
In the printer or copier system, there are some possibility that clock period is shifted because
beam detect signal generates at the beginning of each pass across the paper.
If clock period is shifted one time, PWMOUT will be invalid. It needs long time to recover valid
PWMOUT after previous clock period inputted.
To settle above problem, beam detect signal take in to LS (16 pin) of M66244FP.
For this, It can recover valid PWMOUT within 4usec after previous clock period inputted.
1 line sequence
Beam-detect
PWM clock
Phase shifted clock
Phase shifted clock
4 usec
4 usec
PWMOUT
valid
invalid
valid
invalid
Example of operating timing using LS function
clock stopped time (ns)
recovery time(ns)
20
40
60
80
100
200
400
600
800
1000
2000
4000
1000
1000
2000
4000
7000
10000
14000
17000
20000
23000
30000
40000
recovery time that not using LS function
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valid
MITSUBISHI <DIGITAL ASSP>
June 1998
M66244FP
Ver.8.0.0
High Speed Monolithic Pulse Width Modulator
TEST CIRCUIT DESCRIPTION (JTAG)
GENERAL DESCRIPTION
The Test Access Port conforms with the IEEE standard 1149.1.
This standard defines a test access port and boundary-scan architecture for digital integrated
circuits.
The facilities defined by the standard seek to provide a solution to the problem of testing
assembled printed circuit boards and other products based on highly complex digital
integrated circuits and high-density surface-mounting assembly techniques. They also
provide a means of accessing and controlling design-for-test features build into digital
integrated circuits themselves.
PIN DESCRIPTION
TCK,TMS,TDI,TRST,TDO are used in this test operation.
•Test Clock Input (TCK)
TCK provides the clock for the test logic defined by this standard. Stored-state devices
contained in the test logic retain their state indefinitely when the signal applied to TCK is
stopped at 0.
•Test Mode Select Input (TMS)
The signal received at TMS is decoded by the TAP controlled to control test operation.
The signal presented at TMS is sampled by the test logic on the rising edge of TCK.
•Test Data Input (TDI)
Serial test instructions and data are received by the test logic at TDI.
The signal presented at TDI is sampled by the test logic on the rising edge of TCK.
•Test Reset Input (TRST)
The TRST input provides for asynchronous initialization of the TAP controller.
If TRST is included in the TAP, then the TAPcontroller is asynchronously reset to the TestLogic-Reset controller state when a logic 0 is applied to TRST.
•Test Data Input (TDO)
TDO is a serial output for test instructions and data from the test logic defined in this
standard.
Changes in the state of the signal driven through TDO occur only on the falling edge of
TCK. The TDO driver is set to its inactive drive state except when the scanning of data is in
progress.
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M66244FP
June 1998
Ver.8.0.0
High Speed Monolithic Pulse Width Modulator
BLOCK DIAGRAM OF TEST CIRCUIT
5
GND
VDD
3
4
2
1
36
35
33
34
32
6
7
BSR
31
BSR
30
SET
29
VDD
GND
RESET
GND
8
VDD
9
28
GND
10
27
PWMOUT
26
VDD
VDD
11
25
GND
GND
12
24
VDD
13
14
15
16
17
18
19
20
21
22
23
NOTE1 : BSR routing order = FRANGE1→FRANGE2→LS →SEMDEM→
LEMTEM→D5→D4→D3→D2→D1→D0 →SET →RESET
NOTE2 : CLK(33pin) and PWMOUT(27pin) do not have BSR.
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M66244FP
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Ver.8.0.0
High Speed Monolithic Pulse Width Modulator
TAP CONTROLLER DESCRIPTION
The TAP controller is a synchronous finite state machine that responds to change at the
TMS and TCK signals of the TAP and controls the sequence of operations of the circuitry
defined by this standard.
The state diagram for the TAP controller is shown in following figure.
All state transitions of the TAP controller occur on the value of TMS at the time of a rising
edge of TCK.
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M66244FP
June 1998
High Speed Monolithic Pulse Width Modulator
Ver.8.0.0
INSTRUCTION DESCRIPTION
INSTRUCTION SET
Instruction
Code (Binary)
Selected TDR
EXTEST
000
BSR (Boundary Scan Register)
IDCODE
001
DIR (Device Identification Register)
010
BSR
111
BPR (Bypass Register)
SAMPLE/PRELAOD
BYPASS
EXTEST INSTRUCTION
EXTEST instruction allows testing of off-cihp circuitry and board level interconnections. Data
would typically be loaded onto the latched parallel outputs of boundary-scan shift-register
stages using the SAMPLE/PRELOAD instruction prior to selection of the EXTEST instruction.
The EXTEST instruction select only the BSR(Boundary-scan register) to be connected for
serial access between TDI and TDO in the Shift-DR controller state.
When the EXTEST instruction is selected, the state of all signals received at system input
pins are loaded into the boundary-scan register on the rising edge of TCK in the Capture-DR
controller state.
PWMOUT pin does not have BSR, so PWMOUT pin can not test interconnection to board
using the EXTEST instruction.
BYPASS INSTRUCTION
The bypass register contains a single shift-register stage and is used to provided a minimumlength serial path between the TDI and the TDO pins of a M66244FP when no test operation of
M66244FP is required.
This allows more rapid movement of test data to and from other components on a board that
are required to perform test operations.
The BYPASS instruction select the bypass register to be connected for serial access between
TDI and TDO in the Shift-DR controller state.
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June 1998
Ver.8.0.0
High Speed Monolithic Pulse Width Modulator
SAMPLE/PRELOAD INSTRUCTION
The SAMPLE/PRELOAD instruction allows a snapshot of normal operation of the component
to the taken and examined. It also allows data values to be loaded onto the latched parallel
outputs of the boundary-scan shift register prior to selection of the other boundary-scan test
instruction.
The SAMPLE/PRELOAD instruction select only the boundary-scan register to be connected
for serial access between TDI and TDO in the Shift-DR controller state.
When SAMPLE/PRELOAD instruction is selected, the state of all signals flowing through
system pins are loaded into the register on the rising edge of TCK in the Capture-DR controller
state.
When SAMPLE/PRELOAD instruction is selected, parallel output registers/latches included in
boundary-scan register cells load the data held associated shift-register stage on the falling
edge of TCK in the Update-DR controller state.
IDCOAD INSTRUCTION
Use of the device identification register allows a code to be serially read from the component
that shows:
(1)The version number for the part
(2)The part number
(3)The manufacturer's identity
The IDCODE instruction select only the device identification register to be connected for serial
access between TDI and TDO in the Shift-DR controller state.
When the IDCODE instruction is selected, the vendor identification code is loaded into the
device identification register on the rising edge of TCK following entry into Capture-DR
controller state.
ID code of M66244FP is as follow;
Version
(4bit)
Part num.
(16bit)
bit num.
code
0
0 0 0
bit num. 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
code
Manufacture num. bit num.
(11bit)
code
LSB
(4bit)
31 30 29 28
bit num.
code
0 0 0 1 1 0 0 0 0 1 1 0 0 1 0 0
11 10 9 8 7 6 5 4 3 2 1
0 0 0 0 0 0 1 1 1 0 0
0
JEDEC code
of MITSUBISHI
fixed value
1
C 1998 MITSUBISHI ELECTRIC CORPORATION
binary code
of "6244"
(15/15)
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