Intersil ICM7211AMLM44 4-digit, lcd display driver Datasheet

ICM7211A
4-Digit, LCD Display Driver
August 2001
Features
Description
• Four Digit Non-Multiplexed 7 Segment LCD Display
Outputs with Backplane Driver
The ICM7211A (LCD) device constitutes a family of non-multiplexed four-digit seven-segment CMOS display decoderdrivers.
• Complete Onboard RC Oscillator to Generate Backplane
Frequency
The ICM7211A devices are configured to drive conventional
LCD displays by providing a complete RC oscillator, divider
chain, backplane driver, and 28 segment outputs.
• Backplane Input/Output Allows Simple Synchronization
of Slave-Devices to a Master
This device is available with multiplexed or microprocessor
input configurations. The multiplexed versions provide four
data inputs and four Digit Select inputs. This configuration is
suitable for interfacing with multiplexed BCD or binary output
devices, such as the ICL7135. The microprocessor versions
provide data input latches and Digit Address latches under
control of high-speed Chip Select inputs. These devices simplify the task of implementing a cost-effective alphanumeric
seven-segment display for microprocessor systems, without
requiring extensive ROM or CPU time for decoding and display updating.
• ICM7211A Devices Provide Separate Digit Select Inputs
to Accept Multiplexed BCD Input (Pinout and
Functionally Compatible with Siliconix DF411)
• ICM7211AM Devices Provide Data and Digit Address
Latches Controlled by Chip Select Inputs to Provide a
Direct High Speed Processor Interface
• Decodes Binary to Code B (0-9, Dash, E, H, L, P, Blank)
• Available in Surface Mount Package
The ICM7211A provides the “Code B” output code, i.e., 0-9,
dash, E, H, L, P, blank, but will correctly decode true BCD to
seven-segment decimal outputs.
Ordering Information
PART NUMBER
DISPLAY
TYPE
DISPLAY
DECODING
INPUT
INTERFACING
DISPLAY DRIVE
TYPE
TEMP.
RANGE (oC)
PACKAGE
PKG. NO.
ICM7211AlPL
LCD
Code B
Multiplexed
Direct Drive
-40× to 85×
40 Ld PDIP
E40.6
ICM7211AMlPL
LCD
Code B
Microprocessor
Direct Drive
-40× to 85×
40 Ld PDIP
E40.6
ICM7211AMlM44
LCD
Code B
Microprocessor
Direct Drive
-40× to 85×
44 Ld MQFP
Q44.10x10
1-888-INTERSIL or 321-724-7143
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
| Intersil and Design is a trademark of Intersil Americas Inc. | Copyright © Intersil Americas Inc. 2001
1
File Number
3158.4
ICM7211A
Pinouts
ICM7211AM
(PDIP)
TOP VIEW
ICM7211A
(PDIP)
TOP VIEW
VDD 1
40 d1
VDD 1
40 d1
e1 2
39 c1
e1 2
39 c1
g1 3
38 b1
g1 3
38 b1
f1 4
37 a1
f1 4
37 a1
BP 5
36 OSC
BP 5
36 OSC
a2 6
35 VSS
a2 6
35 VSS
b2 7
34 D4
b2 7
34 CHIP SELECT 2
c2 8
33 D3
c2 8
33 CHIP SELECT 1
d2 9
32 D2
d2 9
32 DIGIT ADRESS BIT 2
DIGIT
SELECT
INPUTS
e2 10
31 D1
e2 10
31 DIGIT ADRESS BIT 1
g2 11
30 B3
g2 11
30 B3
f2 12
29 B2
f2 12
29 B2
a3 13
28 B1
a3 13
28 B1
b3 14
27 B0
b3 14
27 B0
c3 15
26 f4
c3 15
26 f4
d3 16
25 g4
d3 16
25 g4
e3 17
24 e4
e3 17
24 e4
g3 18
23 d4
g3 18
23 d4
f3 19
22 c4
f3 19
22 c4
a4 20
21 b4
a4 20
21 b4
DATA
INPUTS
a1
OSC
b1
c1
d1
NC
VDD
e1
g1
BP
f1
ICM7211AM
(MQFP)
TOP VIEW
b2
44 43 42 41 40 39 38 37 36 35 34
33
2
32
CHIP SELECT 2
c2
3
31
CHIP SELECT 1
d2
4
30
DIGITAL ADRESS BIT 2
e2
5
29
DIGITAL ADRESS BIT 1
NC
6
28
NC
g2
7
27
B3
a2
1
VSS
2
g4
e4
B0
c4
d4
24
11
23
12 13 14 15 16 17 18 19 20 21 22
b4
10
c3
NC
b3
a4
B1
f3
B2
25
g3
26
9
e3
8
d3
f2
a3
f4
DATA
INPUTS
DATA
INPUTS
ICM7211A
Functional Block Diagrams
ICM7211A
D4
SEGMENT OUTPUTS
D3
SEGMENT OUTPUTS
D2
SEGMENT OUTPUTS
D1
SEGMENT OUTPUTS
7 WIDE DRIVER
7 WIDE DRIVER
7 WIDE DRIVER
7 WIDE DRIVER
7 WIDE LATCH EN
7 WIDE LATCH EN
7 WIDE LATCH EN
7 WIDE LATCH EN
PROGRAMMABLE
4 TO 7 DECODER
PROGRAMMABLE
4 TO 7 DECODER
PROGRAMMABLE
4 TO 7 DECODER
PROGRAMMABLE
4 TO 7 DECODER
DATA
INPUTS
DIGIT
SELECT
INPUTS
OSCILLATOR
19kHz
FREE-RUNNING
OSCILLATOR
INPUT
÷128
BLACKPLANE
DRIVER
ENABLE
BP INPUT/OUTPUT
ENABLE
DIRECTOR
ICM7211AM
DATA
INPUTS
2-BIT
DIGIT
ADRESS
INPUT
CHIP
SELECT 1
CHIP
SELECT 2
D4
SEGMENT OUTPUTS
D3
SEGMENT OUTPUTS
D2
SEGMENT OUTPUTS
D1
SEGMENT OUTPUTS
7 WIDE DRIVER
7 WIDE DRIVER
7 WIDE DRIVER
7 WIDE DRIVER
7 WIDE LATCH EN
7 WIDE LATCH EN
7 WIDE LATCH EN
7 WIDE LATCH EN
PROGRAMMABLE
4 TO 7 DECODER
PROGRAMMABLE
4 TO 7 DECODER
PROGRAMMABLE
4 TO 7 DECODER
PROGRAMMABLE
4 TO 7 DECODER
4-BIT
LATCH
ENABLE
2-BIT
LATCH
2 TO 4
DECODER
ENABLE
ONE
SHOT
OSCILLATOR
19kHz
FREE-RUNNING
OSCILLATOR
INPUT
ENABLE
DIRECTOR
3
÷128
BLACKPLANE
DRIVER
ENABLE
BP INPUT/OUTPUT
ICM7211A
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VDD - VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V
Input Voltage (Any Terminal) (Note 1) . . VSS - 0.3V to VDD , + 0.3V
Thermal Resistance (Typical, Note 2)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . .-65×oC to 150oC
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC
(MQFP - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40×oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Due to the SCR structure inherent in the CMOS process, connecting any terminal to voltages greater than VDD or less than VSS may
cause destructive device latchup. For this reason, it is recommended that no inputs from external sources not operating on the same
power supply be applied to the device before its supply is established, and that in multiple supply systems, the supply to the ICM7211A
be turned on first.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
3
5
6
V
10
50
µA
CHARACTERISTICS (LCD) VDD = 5V ±10%, TA = 25oC, VSS = 0V Unless Otherwise Specified
Operating Supply Voltage Range (VDD - VSS), VSUPPLY
Operating Current, IDD
Test circuit, Display blank
-
Oscillator Input Current, IOSCI
Pin 36
-
±2
±10
µA
Segment Rise/Fall Time, tr , tf
CL = 200pF
-
0.5
-
µs
Backplane Rise/Fall Time, tr , tf
CL = 5000pF
-
1.5
-
µs
Oscillator Frequency, fOSC
Pin 36 Floating
-
19
-
kHz
Backplane Frequency, fBP
Pin 36 Floating
-
150
-
Hz
Logical “1” Input Voltage, VIH
4
-
-
V
Logical “0” Input Voltage, VIL
-
-
1
V
-
±0.01
±1
µA
INPUT CHARACTERISTICS
Input Leakage Current, IILK
Pins 27-34
Input Capacitance, ClN
Pins 27-34
-
5
BP/Brightness Input Leakage, IBPLK
Measured at Pin 5 with Pin 36 at VSS
-
±0.01
±1
µA
pF
BP/Brightness Input Capacitance, CBPI
All Devices
-
200
-
pF
AC CHARACTERISTICS - MULTIPLEXED INPUT CONFIGURATION
1
-
-
µs
Data Setup Time, tDS
500
-
-
ns
Data Hold Time, tDH
200
-
-
ns
2
-
-
µs
200
-
-
ns
Digit Select Active Pulse Width, tWH
Refer to Timing Diagrams
Inter-Digit Select Time, tIDS
AC CHARACTERISTICS - MICROPROCESSOR INTERFACE
Chip Select Active Pulse Width, tWL
Other Chip Select Either Held Active,
or Both Driven Together
Data Setup Time, tDS
100
-
-
ns
Data Hold Time, tDH
10
0
-
ns
2
-
-
µs
Inter-Chip Select Time, tICS
4
ICM7211A
Input Definitions In this table, VDD and VSS are considered to be normal operating input logic levels. Actual input low and high levels are
specified under Operating Characteristics. For lowest power consumption, input signals should swing over the full supply.
INPUT
DIP TERMINAL
CONDITIONS
FUNCTION
B0
27
VDD = Logical One
VSS = Logical Zero
Ones (Least Significant)
B1
28
VDD = Logical One
VSS = Logical Zero
Twos
B2
29
VDD = Logical One
VSS = Logical Zero
Fours
B3
30
VDD = Logical One
VSS = Logical Zero
Eights (Most Significant)
OSC
36
Floating or with External
Capacitor to VDD
Oscillator Input
V SS
Disables BP output devices, allowing segments to be synchronized to
an external signal input at the BP terminal (Pin 5).
Data Input Bits
Multiplexed-Binary Input Configuration
INPUT
TERMINAL
D1
31
CONDITIONS
FUNCTION
D2
32
D3
33
D3 Digit Select
D4
34
D4 Digit Select (Most Significant)
VDD = Active
VSS = Inactive
D1 Digit Select (Least Significant)
D2 Digit Select
Microprocessor Interface Input Configuration
INPUT
DESCRIPTION
DIP TERMINAL
CONDITIONS
DA1
Digit Address
Bit 1 (LSB)
31
VDD = Logical One
VSS = Logical Zero
DA2
Digit Address
Bit 2 (MSB)
32
VDD = Logical One
VSS = Logical Zero
CS1
Chip Select 1
33
VDD = Inactive
VSS = Active
CS2
Chip Select 2
34
VDD = Inactive
VSS = Active
FUNCTION
DA1 and DA2 serve as a 2-bit Digit Address Input
DA2, DA1 = 00 selects D4
DA2, DA1 = 01 selects D3
DA2, DA1 = 10 selects D2
DA2, DA1 = 11 selects D1
When both CS1 and CS2 are taken low, the data at the Data
and Digit Select code inputs are written into the input latches.
On the rising edge of either Chip Select, the data is decoded
and written into the output latches.
Timing Diagrams
tIDS
DIGIT SELECT
DN-1
tWH
tIDS
tDH
DIGIT SELECT
DN
DATA VALID
DN-1
DATA VALID
DN
tDS
FIGURE 1. MULTIPLEXED INPUT
CS1
(CS2)
CS2
(CS1)
DATA AND
DIGIT
ADDRESS
tICS
tWI
tDH
tDS
= DON’T CARE
FIGURE 2. MICROPROCESSOR INTERFACE INPUT
5
ICM7211A
Typical Performance Curves
180
30
LCD DEVICES, TA = 25 oC
LCD DEVICES, TEST CIRCUIT
DISPLAY BLANK, PIN 36 OPEN
25
150
COSC = 0pF
(PIN 36 OPEN)
TA = -20 oC
120
TA = 25 oC
ƒBP (Hz)
IOP (µA)
20
15
10
COSC = 22pF
90
60
TA = 70oC
5
COSC = 220pF
30
0
1
2
3
4
5
6
1
7
VSUPP (V)
FIGURE 3. OPERATING SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE
2
3
4
VSUPP (V)
5
6
FIGURE 4. BACKPLANE FREQUENCY AS A FUNCTION OF
SUPPLY VOLTAGE
Description Of Operation
play temperatures, depending on the display type.
LCD Devices
The onboard oscillator is designed to free run at approximately 19kHz at microampere current levels. The oscillator
frequency is divided by 128 to provide the backplane frequency, which will be approximately 150Hz with the oscillator
free-running; the oscillator frequency may be reduced by
connecting an external capacitor between the OSCillator terminal and VDD .
The ICM7211A provides outputs suitable for driving conventional four-digit, seven-segment LCD displays. These
devices include 28 individual segment drivers, backplane
driver, and a self-contained oscillator and divider chain to
generate the backplane frequency.
The segment and backplane drivers each consist of a
CMOS inverter, with the N-Channel and P-Channel devices
ratioed to provide identical on resistances, and thus equal
rise and fall times. This eliminates any DC component, which
could arise from differing rise and fall times, and ensures
maximum display life.
The oscillator may also be overdriven if desired, although care
must be taken to ensure that the backplane driver is not disabled during the negative portion of the overdriving signal
(which could cause a DC component to the display). This can
be done by driving the OSCillator input between the positive
supply and a level out of the range where the backplane disable
is sensed (about one fifth of the supply voltage above VSS).
Another technique for overdriving the oscillator (with a signal
swinging the full supply) is to skew the duty cycle of the overdriving signal such that the negative portion has a duration
shorter than about one microsecond. The backplane disable
sensing circuit will not respond to signals of this duration.
The backplane output devices can be disabled by connecting the OSCillator input (pin 36) to VSS . This allows the 28
segment outputs to be synchronized directly to a signal input
at the BP terminal (pin 5). In this manner, several slave
devices may be cascaded to the backplane output of one
master device, or the backplane may be derived from an
external source. This allows the use of displays with characters in multiples of four and a single backplane. A slave
device represents a load of approximately 200pF (comparable to one additional segment). Thus the limitation of the
number of devices that can be slaved to one master device
backplane driver is the additional load represented by the
larger backplane of displays of more than four digits. A good
rule of thumb to observe in order to minimize power consumption is to keep the backplane rise and fall times less
than about 5µs. The backplane output driver should handle
the backplane to a display of 16 one-half inch characters. It
is recommended, if more than four devices are to be slaved
together, the backplane signal be derived externally and all
the ICM7211A devices be slaved to it. This external signal
should be capable of driving very large capacitive loads with
short (1 - 2µs) rise and fall times. The maximum frequency
for a backplane signal should be about 150Hz although this
may be too fast for optimum display response at lower dis-
OSCILLATOR
FREQUENCY
128 CYCLES
BACKPLANE
INPUT/OUTPUT
OFF
SEGMENTS
64 CYCLES
64 CYCLES
ON
SEGMENTS
FIGURE 5. DISPLAY WAVEFORMS
6
ICM7211A
Input Configurations and Output Codes
under processor control.
The ICM7211A accepts a four-bit true binary (i.e., positive
level = logical one) input at pins 27 thru 30, least significant
bit at pin 27 ascending to the most significant bit at pin 30. It
decodes the binary input into seven-segment alphanumeric
“Code B” output, i.e., 0-9, dash, E, H, L, P, blank. These
codes are shown explicitly in Table 1. It will correctly decode
true BCD to a seven-segment decimal output.
In these devices, the four data input bits and the two-bit digit
address (DA1 pin 31, DA2 pin 32) are written into input buffer
latches when both chip select inputs (CS1 pin 33, CS2 pin
34) are taken low. On the rising edge of either chip select
input, the content of the data input latches is decoded and
stored in the output latches of the digit selected by the contents of the digit address latches.
An address of 00 writes into D4, DA2 = 0, DA1 = 1 writes into
D3, DA2 = 1, DA1 = 0 writes into D2, and 11 writes into D1.
The timing relationships for inputting data are shown in
Figure 2, and the chip select pulse widths and data setup and
hold times are specified under Operating Characteristics.
TABLE 1. OUTPUT CODES
BlNARY
B3
B2
B1
BO
0
0
0
0
CODE B
ICM7211A
ICM7212AM
a
f
0
0
0
b
g
1
e
c
d
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
FIGURE 6. SEGMENT ASSIGNMENT
BLANK
The ICM7211A is designed to accept multiplexed binary or
BCD input. These devices provide four separate digit lines
(least significant digit at pin 31 ascending to most significant
digit at pin 34), each of which when taken to a positive level
decodes and stores in the output latches of its respective digit
the character corresponding to the data at the input port, pins
27 through 30.
The ICM7211AM is intended to accept data from a data bus
7
ICM7211A
Test Circuit
VDD
+
VSS
-
1 VDD
2
40
3
38
4
37
5 BP
OSC
36
6
VSS
35
7
8
9
EACH SEGMENT
OUTPUT TO
BACKPLANE
WITH A 200pF
CAPACITOR
39
ICM7211AM
10
34
DIGIT/CHIP
SELECT
INPUTS
11
33
VDD
MICROPROCESSOR
VERSION
VSS
MULTIPLEXED
VERSION
32
31
30
12
DATA
INPUTS
13
29
VDD
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
FIGURE 7.
Typical Applications
D8
D7
D6
D5
D4
D3
D2
D1
BACKPLANE
8-DIGIT
LCD DISPLAY
BACKPLANE
SLAVE
+5V
VDD
BACKPLANE
MASTER
28
+5V
SEGMENTS
HIGH ORDER
ICM7211A
VSS
OSC
B3-B0
SEGMENTS
LOW ORDER
ICM7211A
VSS
OSC
D4 D3 D2 D1 BP
4
BCD/BINARY
DATA
VDD
28
B3-B0
D4 D3 D2 D1 BP
4
4
D8
D7
D6
DIGIT
SELECTS
D5
D4
D3
D2
D1
FIGURE 8. GANGED ICM7211A’s DRIVING 8-DIGIT LCD DISPLAY
8
ICM7211A
Typical Applications
(Continued)
8 DIGIT
LCD DISPLAY
ICM7211AM
HIGH ORDER DIGITS
+5V
40 26
VCC VDD
NC
INPUT
20 P10 27
VSS
28
29
2 XTAL1
30
31
32
3 XTAL2
33
4 RESET
P17 34
P20 21
7 EA
22
23
24
35
5 SS
80C48
36
µCOMPUTER
37
P27 38
1 TO
DB0 12
13
39 T1
14
15
6 INT
16
17
18
DB7 19
ALE PSEN PROG WR
11
9
25
10
+5V
ICM7211AM
LOW ORDER DIGITS
1 VDD
2, 3, 4
SEGMENTS 6-26
35 VSS
37-40
DATA
36 OSC B0-B3
I/O
BP 5
DS1 DS2 CS1 CS2
27 28 29 30 31 32 33 34
BP 5
DATA
B0-B3
2, 3, 4
1 VDD
6-26 SEGMENTS
35 VSS
37-40
36 OSC
+5V
DS1 DS2 CS1 CS2
27 28 29 30 31 32 33 34
I/O
RD
8
FIGURE 9. 80C48 MICROPROCESSOR INTERFACE
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
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