TI1 BQ40Z50RSMT 1-series, 2-series, 3-series, and 4-series li-ion battery pack manager Datasheet

bq40z50
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SLUSBS8 – DECEMBER 2013
1-Series, 2-Series, 3-Series, and 4-Series Li-Ion Battery Pack Manager
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FEATURES
APPLICATIONS
•
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1
2
•
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Fully Integrated 1-Series, 2-Series, 3-Series,
and 4-Series Li-Ion or Li-Polymer Cell Battery
Pack Manager and Protection
Next-Generation Patented Impedance Track™
Technology Accurately Measures Available
Charge in Li-Ion and Li-Polymer Batteries
High Side N-CH Protection FET Drive
Integrated Cell Balancing While Charging or At
Rest
Full Array of Programmable Protection
Features
– Voltage
– Current
– Temperature
– Charge Timeout
– CHG/DSG FETs
– AFE
Sophisticated Charge Algorithms
– JEITA
– Enhanced Charging
– Adaptive Charging
– Cell Balancing
Diagnostic Lifetime Data Monitor
LED Display
Supports Two-Wire SMBus v1.1 Interface
SHA-1 Authentication
Compact Package: 32-Lead QFN
Notebook/Netbook PCs
Medical and Test Equipment
Portable Instrumentation
DESCRIPTION
The bq40z50 device, incorporating patented
Impedance Track™ technology, is a fully integrated,
single-chip, pack-based solution that provides a rich
array of features for gas gauging, protection, and
authentication for 1-series, 2-series, 3-series, and 4series cell Li-Ion and Li-Polymer battery packs.
Using its integrated high-performance analog
peripherals, the bq40z50 device measures and
maintains an accurate record of available capacity,
voltage, current, temperature, and other critical
parameters in Li-Ion or Li-Polymer batteries, and
reports this information to the system host controller
over an SMBus v1.1 compatible interface.
The bq40z50 provides software-based 1st- and 2ndlevel
safety
protection
against
overvoltage,
undervoltage, overcurrent, short-circuit current,
overload, and overtemperature conditions, as well as
other pack- and cell-related faults.
SHA-1 authentication, with secure memory for
authentication keys, enables identification of genuine
battery packs.
The compact 32-lead QFN package minimizes
solution cost and size for smart batteries while
providing maximum functionality and safety for
battery gauging applications.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Impedance Track is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
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SLUSBS8 – DECEMBER 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA
PART
NUMBER
PACKAGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
–40°C to
85°C
bq40z50
RSM-32
RSM
bq40z50
(1)
(2)
(3)
ORDERING INFORMATION (1)
TUBE (2)
TAPE AND
REEL (3)
bq40z50RSMT
bq40z50RSMR
For the most current package and ordering information, see the Package Option Addendum at the end of the document, or see the TI
website at www.ti.com.
A single tube quantity is 50 units.
A single reel quantity is 2000 units.
THERMAL INFORMATION
bq40z50
THERMAL METRIC (1)
RSM (QFN)
UNITS
32 Pins
θJA, High K
Junction-to-ambient thermal resistance (2)
47.4
θJC(top)
Junction-to-case(top) thermal resistance (3)
40.3
θJB
Junction-to-board thermal resistance (4)
14.7
ψJT
Junction-to-top characterization parameter (5)
0.8
ψJB
Junction-to-board characterization parameter (6)
14.4
θJC(bottom)
Junction-to-case(bottom) thermal resistance (7)
3.8
(1)
(2)
(3)
(4)
(5)
(6)
(7)
2
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
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TYPICAL IMPLEMENTATION
100 Ω
3 MΩ
PACK+
10 kΩ
DSG
5.1 kΩ
VCC
1 kΩ
5.1 kΩ
PCHG
BAT
CHG
FUSE
PTC
10 kΩ
5.1 kΩ
0.1 μF
5.1 kΩ
3 MΩ
PACK
LEDCNTLA
10 Ω
VC4
LEDCNTLB
100 Ω
LEDCNTLC
VC3
VDD
VC3
2nd level
protector
OUT
100 Ω
VC2
VC2
100 Ω
VC1
100 Ω
DISP
SMBD
VC1
SMBD
GND
SMBC
100 Ω
PRES
100 Ω
PBI
SMBC
2.2 μF
PRES
180 kΩ
VSS
SRP
SRN
TS1
TS2
10 kΩ
10 kΩ
PACK–
Figure 1. bq40z50 Implementation
BAT
CHG
PCHG
NC
DSG
PACK
VCC
FUSE
32
31
30
29
28
27
26
25
Pinout Diagram
PBI
1
24
PTCEN
VC4
2
23
PTC
VC3
3
22
LEDCNTLC
VC2
4
21
LEDCNTLB
VC1
5
20
LEDCNTLA
SRN
6
19
SMBC
NC
7
18
SMBD
SRP
8
17
DISP
16
15
BTP_I NT
PRES
¯¯¯¯ or
SHUTDN
¯¯¯¯
13
14
NC
12
TS3
TS4
11
TS2
9
10
VSS
TS1
¯¯¯¯
Figure 2. bq40z50 Pinout Diagram
PIN FUNCTIONS
(1)
PIN NAME
PIN
NUMBER
TYPE (1)
PBI
1
P
Power supply backup input pin
VC4
2
IA
Sense voltage input terminal for most positive cell, and balance current input for most
positive cell
DESCRIPTION
P = Power Connection, O = Digital Output, AI = Analog Input, I = Digital Input, I/OD = Digital Input/Output
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PIN FUNCTIONS (continued)
PIN NAME
PIN
NUMBER
TYPE (1)
VC3
3
IA
Sense voltage input terminal for second most positive cell, balance current input for
second most positive cell, and return balance current for most positive cell
VC2
4
IA
Sense voltage input terminal for third most positive cell, balance current input for third
most positive cell, and return balance current for second most positive cell
VC1
5
IA
Sense voltage input terminal for least positive cell, balance current input for least positive
cell, and return balance current for third most positive cell
SRN
6
I
NC
7
—
SRP
8
I
Analog input pin connected to the internal coulomb counter peripheral for integrating a
small voltage between SRP and SRN where SRP is the top of the sense resistor.
DESCRIPTION
Analog input pin connected to the internal coulomb counter peripheral for integrating a
small voltage between SRP and SRN where SRP is the top of the sense resistor.
Not internally connected. Connect to VSS.
VSS
9
P
Device ground
TS1
10
IA
Temperature sensor 1 thermistor input pin
TS2
11
IA
Temperature sensor 2 thermistor input pin
TS3
12
IA
Temperature sensor 3 thermistor input pin
TS4
13
IA
Temperature sensor 4 thermistor input pin
NC
14
—
Not internally connected.
BTP_INT
15
O
Battery Trip Point (BTP) interrupt output
PRES or SHUTDN
16
I
Host system present input for removable battery pack or emergency system shutdown
input for embedded pack
DISP
17
—
SMBD
18
I/OD
SMBus data pin
SMBC
19
I/OD
SMBus clock pin
LEDCNTLA
20
—
LED display segment that drives the external LEDs depending on the firmware
configuration
LEDCNTLB
21
—
LED display segment that drives the external LEDs depending on the firmware
configuration
LEDCNTLC
22
—
LED display segment that drives the external LEDs depending on the firmware
configuration
PTC
23
IA
Safety PTC thermistor input pin. To disable, connect both PTC and PTCEN to VSS.
PTCEN
24
IA
Safety PTC thermistor enable input pin. Connect to BAT. To disable, connect both PTC
and PTCEN to VSS.
FUSE
25
O
Fuse drive output pin
VCC
26
P
Secondary power supply input.
PACK
27
IA
Pack sense input pin
DSG
28
O
NMOS Discharge FET drive output pin
NC
29
—
Not internally connected.
PCHG
30
O
PMOS Precharge FET drive output pin
CHG
31
O
NMOS Charge FET drive output pin
BAT
32
P
Primary power supply input pin
4
Display control for LEDs
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SLUSBS8 – DECEMBER 2013
PIN EQUIVALENT DIAGRAMS
VC4
BAT
VCC
CDEN4
PACK
VC3
+
–
3.1 V
BATDET
ENVCC
CDEN3
PACK
Detector
VC2
PACKDET
PBI
Reference
System
Shutdown
Latch
1.8 V
Domain
SHUTDOWN
VC1
BAT
Control
Power Supply Control
ADC
CDEN2
SHOUT
ENBAT
ADC Mux
CDEN1
Cell Balancing
VCC
CHGEN
BAT
2 kΩ
CHG
Pump
CHG
8 kΩ
2 kΩ
PCHG
CHGOFF
PCHGEN
Pre-Charge Drive
PACK
BAT
DSGEN
BAT
DSG
Pump
ZVCD
2 kΩ
DSG
CHGEN
BAT
DSGOFF
CHG
Pump
VCC
ZVCHGEN
CHG, DSG Drive
Zero-Volt Charge
Figure 3. Pin Equivalent Diagram 1
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1.8 V
ADTHx
BAT
FUSEWKPUP
18 kΩ
2 kΩ
ADC Mux
TS1,2,3,4
ADC
FUSEEN
150 nA
2 kΩ
FUSE
1.8 V
1.8 V
100 kΩ
FUSEDIG
RCWKPUP
RCPUP
FUSE Drive
1 kΩ
RCIN
RCOUT
SMBCIN
100 kΩ
SMBC
Thermistor Inputs
SMBCOUT
SMBCEN
1 MΩ
PBI
100 kΩ
SMBDIN
RHOEN
SMBDOUT
10 kΩ
PRES
SMBD
SMBDEN
1 MΩ
SMBus Interface
RHOUT
100 kΩ
RHIN
High-Voltage GPIO
PTCEN
BAT
30 kΩ
PTC
RLOEN
PTC
Comparator
PTC
Counter
PTC
Latch
PTCDIG
290 nA
10 kΩ
LED1, 2, 3
22.5 mA
RLOUT
100 kΩ
RLIN
LED Drive
PTC Detection
Figure 4. Pin Equivalent Diagram 2
6
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SLUSBS8 – DECEMBER 2013
10 Ω
VC4
CHANx
Φ2
3.8 kΩ
1.9 MΩ
SRP
ADC Mux
Φ1
ADC
Comparator
Array
Φ2
3.8 kΩ
0.1 MΩ
SRN
Φ1
Φ2
10 Ω
100 Ω
PACK
Φ1
Coulomb
Counter
Φ2
CHANx
100 Ω
Φ1
1.9 MΩ
ADC Mux
ADC
0.1 MΩ
OCD, SCC, SCD Comparators and Coulomb Counter
VC4 and PACK Dividers
Figure 5. Pin Equivalent Diagram 3
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted) (1)
DESCRIPTION
Supply voltage range, VCC
Input voltage range, VIN
Output voltage range, VO
PINS
BAT, VCC, PBI
–0.3 to 30 V
PACK, SMBC, SMBD, PRES or SHUTDN, BTP_INT,
DISP
–0.3 to 30 V
TS1, TS2, TS3, TS4
–0.3 to VREG + 0.3 V
PTC, PTCEN, LEDCNTLA, LEDCNTLB, LEDCNTLC
–0.3 to VBAT + 0.3 V
SRP, SRN
–0.3 to 0.3 V
VC4
VC3 – 0.3 to VC3 + 8.5 V, or VSS + 30 V
VC3
VC2 – 0.3 to VC2 + 8.5 V, or VSS + 30 V
VC2
VC1 – 0.3 to VC1 + 8.5 V, or VSS + 30 V
VC1
VSS – 0.3 to VSS + 8.5 V, or VSS + 30 V
CHG, DSG
–0.3 to 32 V
PCHG, FUSE
–0.3 to 30 V
Maximum VSS current, ISS
ESD Rating
VALUE
50 mA
HBM
2 kV
CDM
500 V
MM
200 V
Functional Temperature, TFUNC
–40 to 110°C
Storage temperature range, TSTG
–65 to 150°C
Lead temperature (soldering, 10 s), TSOLDER
300°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
MIN
VCC
Supply voltage
BAT, VCC, PBI
2.2
VSHUTDOWN–
Shutdown voltage
VPACK < VSHUTDOWN–
1.8
TYP
2.0
MAX
UNIT
26
V
2.2
V
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RECOMMENDED OPERATING CONDITIONS (continued)
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
VSHUTDOWN+
Start-up voltage
VPACK > VSHUTDOWN– + VHYS
VHYS
Shutdown voltage
hysteresis
VSHUTDOWN+ – VSHUTDOWN–
MIN
TYP
MAX
UNIT
2.05
2.25
2.45
V
250
PACK, SMBC, SMBD , PRES, BTP_IN, DISP
26
TS1, TS2, TS3, TS4
VREG
PTC, PTCEN, LEDCNTLA, LEDCNTLB, LEDCNTLC
VIN
Input voltage range
mV
VBAT
SRP, SRN
–0.2
0.2
VC4
VVC3
VVC3 + 5
VC3
VVC2
VVC2 + 5
VC2
VVC1
VVC1 + 5
VC1
VVSS
VVSS + 5
VO
Output voltage
range
CPBI
External PBI
capacitor
2.2
TOPR
Operating
temperature
–40
CHG, DSG, PCHG, FUSE
26
V
V
µF
85
°C
SUPPLY CURRENT
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 20 V (unless otherwise noted)
PARAMETER
INORMAL
NORMAL mode
ISLEEP
SLEEP mode
ISHUTDOWN
SHUTDOWN mode
TEST CONDITION
MIN
TYP
CHG on. DSG on, no Flash write
336
CHG off, DSG on, no SBS communication
75
CHG off, DSG off, no SBS communication
52
MAX
UNIT
µA
µA
1.6
µA
POWER SUPPLY CONTROL
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
VBAT < VSWITCHOVER–
1.95
2.1
2.2
V
VBAT > VSWITCHOVER– + VHYS
2.9
3.1
3.25
V
VSWITCHOVER–
BAT to VCC
switchover
voltage
VSWITCHOVER+
VCC to BAT
switchover
voltage
VHYS
Switchover
VSWITCHOVER+ – VSWITCHOVER–
voltage hysteresis
ILKG
RPD
8
Input Leakage
current
Internal pulldown
resistance
1000
mV
BAT pin, BAT = 0 V, VCC = 25 V, PACK = 25 V
1
PACK pin, BAT = 25 V, VCC = 0 V, PACK = 0 V
1
BAT and PACK pins, BAT = 0 V, VCC = 0 V, PACK =
0 V, PBI = 25 V
1
PACK
30
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40
50
µA
kΩ
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AFE POWER-ON RESET
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITION
VREGIT–
Negative-going
voltage input
VREG
VHYS
Power-on reset
hysteresis
VREGIT+ – VREGIT–
tRST
Power-on reset
time
MIN
TYP
MAX
UNIT
1.51
1.55
1.59
V
70
100
130
mV
200
300
400
µs
AFE WATCHDOG RESET AND WAKE TIMER
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
372
500
628
tWDT = 1000
744
1000
1256
tWDT = 2000
1488
2000
2512
tWDT = 4000
2976
4000
5024
tWAKE = 250
186
250
314
tWAKE = 500
372
500
628
tWAKE = 1000
744
1000
1256
tWAKE = 512
1488
2000
2512
tFETOFF = 512
409
512
614
tWDT = 500
AFE watchdog
timeout
tWDT
tWAKE
AFE wake timer
tFETOFF
FET off delay after
reset
UNIT
ms
ms
ms
CURRENT WAKE COMPARATOR
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
VWAKE
Wake voltage
threshold
VWAKE(DRIFT)
Temperature drift
of VWAKE accuracy
tWAKE
Time from
application of
current to wake
interrupt
tWAKE(SU)
Wake comparator
startup time
MIN
TYP
MAX
VWAKE = ±0.625 mV
TEST CONDITION
±0.3
±0.625
±0.9
VWAKE = ±1.25 mV
±0.6
±1.25
±1.8
VWAKE = ±2.5 mV
±1.2
±2.5
±3.6
VWAKE = ±5 mV
±2.4
±5.0
±7.2
0.5
500
UNIT
mV
%/°C
700
µs
1000
µs
VC1, VC2, VC3, VC4, BAT, PACK
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
K
Scaling factor
TEST CONDITION
MIN
TYP
MAX
VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3
0.1980
0.2000
0.2020
BAT–VSS, PACK–VSS
0.049
0.050
0.051
VREF2
0.490
0.500
0.510
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Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3
–0.2
5
BAT–VSS, PACK–VSS
–0.2
20
VIN
Input voltage range
ILKG
Input leakage current
VC1, VC2, VC3, VC4, cell balancing off, cell detach
detection off, ADC multiplexer off
RCB
Internal cell balance
resistance
RDS(ON) for internal FET switch at 2 V < VDS < 4 V
ICD
Internal cell detach
check current
VCx > VSS + 0.8 V
30
50
UNIT
V
1
µA
200
Ω
70
µA
SMBD, SMBC
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
VIH
Input voltage high
SMBC, SMBD, VREG = 1.8 V
1.3
VIL
Input voltage low
SMBC, SMBD, VREG = 1.8 V
0.8
VOL
Output low voltage
SMBC, SMBD, VREG = 1.8 V, IOL = 1.5 mA
0.4
CIN
Input capacitance
ILKG
Input leakage current
RPD
Pulldown resistance
V
5
0.7
UNIT
1.0
V
V
pF
1
µA
1.3
MΩ
PRES, BTP_INT, DISP
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
VIH
High-level input
VIL
Low-level input
VOH
Output voltage high
VOL
Output voltage low
CIN
Input capacitance
ILKG
Input leakage current
RO
Output reverse
resistance
TEST CONDITION
MIN
TYP
MAX
1.3
V
0.55
VBAT > 5.5 V, IOH = –0 µA
3.5
VBAT > 5.5 V, IOH = –10 µA
1.8
V
V
IOL = 1.5 mA
0.4
5
V
pF
1
Between PRES or BTP_INT or DISP and PBI
UNIT
8
µA
kΩ
LEDCNTLA, LEDCNTLB, LEDCNTLC
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
VIH
High-level input
VIL
Low-level input
TEST CONDITION
TYP
MAX
1.45
Output voltage high
VBAT > 3.0 V, IOH = –22.5 mA
VOL
Output voltage low
IOL = 1.5 mA
ISC
High level output
current protection
IOL
Low level output
current
VBAT > 3.0 V, VOH = 0.4 V
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UNIT
V
0.55
VOH
10
MIN
VBAT –
1.6
V
V
0.4
V
–30
–45
–6 0
mA
15.75
22.5
29.25
mA
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Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITION
ILEDCNTLx
Current matching
between LEDCNTLx
CIN
Input capacitance
ILKG
Input leakage current
fLEDCNTLx
Frequency of LED
pattern
MIN
TYP
VBAT = VLEDCNTLx + 2.5 V
MAX
UNIT
+/–1
%
20
pF
1
µA
124
Hz
COULOMB COUNTER
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITION
Input voltage range
Full scale range
MIN
TYP
MAX
UNIT
–0.1
0.1
V
–VREF1/10
VREF1/10
V
±5.2
±22.3
LSB
Integral nonlinearity (1)
16-bit, best fit over input voltage range
Offset error
16-bit, Post-calibration
±5
±10
µV
Offset error drift
15-bit + sign, Post-calibration
0.2
0.3
µV/°C
Gain error
15-bit + sign, over input voltage range
±0.2
±0.8
%FSR
Gain error drift
15-bit + sign, over input voltage range
150
PPM /°C
Effective input resistance
(1)
2.5
N
MΩ
15
1 LSB = VREF1/(10 × 2 ) = 1.215/(10 × 2 ) = 3.71 µV
CC DIGITAL FILTER
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITION
Conversion time
Single conversion
Effective resolution
Single conversion
MIN
TYP
MAX
UNIT
250
ms
15
Bits
ADC
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
Input voltage range
Full scale range
Integral nonlinearity (1)
TEST CONDITION
MIN
TYP
MAX
Internal reference (VREF1)
–0.2
1
External reference (VREG)
–0.2
0.8 x VREG
VFS = VREF1 or VREG
–VFS
UNIT
V
VFS
16-bit, best fit, –0.1 V to 0.8 x VREF1
±6.6
16-bit, best fit, –0.2 V to –0.1 V
±13.1
V
LSB
Offset error (2)
16-bit, Post-calibration, VFS = VREF1
Offset error drift
16-bit, Post-calibration, VFS = VREF1
0.6
3
µV/°C
Gain error
16-bit, –0.1 V to 0.8 x VFS
±0.2
±0.8
%FSR
Gain error drift
16-bit, –0.1 V to 0.8 x VFS
150
PPM/°C
Effective input resistance
(1)
(2)
N
±67
±157
µV
8
MΩ
15
1 LSB = VREF1/(2 ) = 1.225/(2 ) = 37.4 µV (when tCONV = 31.25 ms)
For VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3, VC4–VSS, PACK–VSS, and VREF1/2, the offset error is multiplied by (1/ADC
multiplexer scaling factor (K)).
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ADC DIGITAL FILTER
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
Conversion time
Resolution
Effective resolution
TEST CONDITION
MIN
TYP
Single conversion
31.25
Single conversion
15.63
Single conversion
7.81
Single conversion
1.95
No missing codes
16
With sign, tCONV = 31.25 ms
14
15
With sign, tCONV = 15.63 ms
13
14
With sign, tCONV = 7.81 ms
11
12
With sign, tCONV = 1.95 ms
9
10
MAX
UNIT
ms
Bits
Bits
CHG, DSG FET DRIVE
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
Output voltage
ratio
TEST CONDITION
MIN
TYP
MAX
RatioDSG = (VDSG – VBAT)/VBAT, 2.2 V < VBAT < 4.92 V,
10 MΩ between PACK and DSG
2.133
2.333
2.433
RatioCHG = (VCHG – VBAT)/VBAT, 2.2 V < VBAT < 4.92 V,
10 MΩ between BAT and CHG
2.133
2.333
2.433
10.5
11.5
12
10.5
11.5
12
VDSG(ON) = VDSG – VBAT, VBAT ≥ 4.92 V, 10 MΩ between
PACK and DSG, VBAT = 18 V
Output voltage,
CHG and DSG on VCHG(ON) = VCHG – VBAT, VBAT ≥ 4.92 V, 10 MΩ between
BAT and CHG, VBAT = 18 V
V(FETON)
V(FETOFF)
tR
VDSG(OFF) = VDSG – VPACK, 10 MΩ between PACK and
Output voltage,
DSG
CHG and DSG off
VCHG(OFF) = VCHG – VBAT, 10 MΩ between BAT and CHG
Rise time
tF
Fall time
UNIT
—
V
–0.4
0.4
–0.4
0.4
VDSG from 0% to 35% VDSG(ON)(TYP), VBAT ≥ 2.2 V, CL =
4.7 nF between DSG and PACK, 5.1 kΩ between DSG
and CL, 10 MΩ between PACK and DSG
200
VCHG from 0% to 35% VCHG(ON)(TYP), VBAT ≥ 2.2 V, CL =
4.7 nF between CHG and BAT, 5.1 kΩ between CHG
and CL, 10 MΩ between BAT and CHG
200
500
VDSG from VDSG(ON)(TYP) to 1 V, VBAT ≥ 2.2 V, CL = 4.7 nF
between DSG and PACK, 5.1 kΩ between DSG and CL,
10 MΩ between PACK and DSG
40
300
VCHG from VCHG(ON)(TYP) to 1 V, VBAT ≥ 2.2 V, CL = 4.7
nF between CHG and BAT, 5.1 kΩ between CHG and
CL, 10 MΩ between BAT and CHG
40
V
500
µs
µs
200
PCHG FET DRIVE
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
V(FETON)
Output voltage,
PCHG on
VPCHG(ON) = VVCC – VPCHG, 10 MΩ between VCC and
PCHG
6
7
8
V
V(FETOFF)
Output voltage,
PCHG off
VPCHG(OFF) = VVCC – VPCHG, 10 MΩ between VCC and
PCHG
–0.4
0.4
V
tR
Rise time
VPCHG from 10% to 90% VPCHG(ON)(TYP), VVCC ≥ 8 V, CL =
4.7 nF between PCHG and VCC, 5.1 kΩ between PCHG
and CL, 10 MΩ between VCC and CHG
200
µs
12
TEST CONDITION
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Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
tF
TEST CONDITION
MIN
TYP
MAX
UNIT
40
200
µs
VPCHG from 90% to 10% VPCHG(ON)(TYP), VCC ≥ 8 V, CL =
4.7 nF between PCHG and VCC, 5.1 kΩ between PCHG
and CL, 10 MΩ between VCC and CHG
Fall time
FUSE DRIVE
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITION
VOH
Output voltage
high
VIH
High-level input
IAFEFUSE(PU)
Internal pullup
current
RAFEFUSE
Output
impedance
CIN
Input capacitance
tDELAY
Fuse trip
detection delay
tRISE
Fuse output rise
time
MIN
TYP
MAX
VBAT ≥ 8 V, CL = 1 nF, IAFEFUSE = 0 µA
6
7
8.65
VBAT < 8 V, CL = 1 nF, IAFEFUSE = 0 µA
VBAT – 0.1
1.5
VBAT ≥ 8 V, VAFEFUSE = VSS
2
UNIT
V
VBAT
2.0
2.5
V
150
330
nA
2.6
3.2
kΩ
5
128
VBAT ≥ 8 V, CL = 1 nF, VOH = 0 V to 5 V
5
pF
256
µs
20
µs
INTERNAL TEMPERATURE SENSOR
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
Internal
temperature
sensor voltage
drift
VTEMP
TEST CONDITION
MIN
TYP
MAX
VTEMPP
–1.9
–2.0
–2.1
VTEMPP – VTEMPN, assured by design
0.177
0.178
0.179
UNIT
mV/°C
TS1, TS2, TS3, TS4
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
TS1, TS2, TS3, TS4, VBIAS = VREF1
–0.2
0.8 x VREF1
TS1, TS2, TS3, TS4, VBIAS = VREG
–0.2
0.8 x VREG
UNIT
VIN
Input voltage
range
RNTC(PU)
Internal pullup
resistance
TS1, TS2, TS3, TS4
14.4
18
21.6
kΩ
RNTC(DRIFT)
Resistance drift
over
temperature
TS1, TS2, TS3, TS4
–360
–280
–200
PPM/°C
V
PTC, PTCEN
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
RPTC(TRIP)
TEST CONDITION
PTC trip
resistance
MIN
TYP
MAX
UNIT
1.2
2.5
3.95
MΩ
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Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
VPTC(TRIP)
PTC trip voltage
VPTC(TRIP) = VPTCEN – VPTC
200
500
890
mV
IPTC
Internal PTC
current bias
TA = –40°C to 110°C
200
290
350
nA
tPTC(DELAY)
PTC delay time
TA = –40°C to 110°C
40
80
145
ms
INTERNAL 1.8-V LDO
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
1.6
1.8
2.0
V
VREG
Regulator voltage
ΔVO(TEMP)
Regulator output
over temperature
ΔVREG/ΔTA, IREG = 10 mA
ΔVO(LINE)
Line regulation
ΔVREG/ΔVBAT, VBAT = 10 mA
–0 .6
0.5
%
ΔVO(LOAD)
Load regulation
ΔVREG/ΔIREG, IREG = 0 mA to 10 mA
–1.5
1.5
%
IREG
Regulator output
current limit
VREG = 0.9 x VREG(NOM), VIN > 2.2 V
20
ISC
Regulator shortcircuit current limit
VREG = 0 x VREG(NOM)
25
PSRRREG
Power supply
rejection ratio
ΔVBAT/ΔVREG, IREG = 10 mA ,VIN > 2.5 V, f = 10 Hz
VSLEW
Slew rate
enhancement
voltage threshold
VREG
±0.25
1.58
%
mA
40
55
mA
40
dB
1.65
V
HIGH-FREQUENCY OSCILLATOR
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
fHFO
TEST CONDITION
MIN
Operating frequency
fHFO(ERR)
Frequency error
tHFO(SU)
Start-up time
TYP
MAX
16.78
MHz
TA = –20°C to 70°C, includes frequency drift
–2.5
±0.25
2.5
TA = –40°C to 85°C, includes frequency drift
–3.5
±0.25
3.5
TA = –20°C to 85°C, oscillator frequency within
+/–3% of nominal
oscillator frequency within +/–3% of nominal
UNIT
%
4
ms
100
µs
LOW-FREQUENCY OSCILLATOR
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
fLFO
MIN
Operating frequency
fLFO(ERR)
Frequency error
fLFO(FAIL)
Failure detection
frequency
14
TEST CONDITION
TYP
MAX
262.144
kHz
TA = –20°C to 70°C, includes frequency drift
–1.5
±0.25
1.5
TA = –40°C to 85°C, includes frequency drift
–2.5
±0.25
2.5
30
80
100
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UNIT
%
kHz
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SLUSBS8 – DECEMBER 2013
VOLTAGE REFERENCE 1
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
VREF1
Internal reference
voltage
VREF1(DRIFT)
Internal reference
voltage drift
TEST CONDITION
TA = 25°C, after trim
MIN
TYP
MAX
UNIT
1.21
1.215
1.22
V
TA = 0°C to 60°C, after trim
±50
TA = –40°C to 85°C, after trim
±80
PPM/°C
VOLTAGE REFERENCE 2
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
VREF2
Internal reference
voltage
VREF2(DRIFT)
Internal reference
voltage drift
TEST CONDITION
TA = 25°C, after trim
MIN
TYP
MAX
UNIT
1.22
1.225
1.23
V
TA = 0°C to 60°C, after trim
±50
TA = –40°C to 85°C, after trim
±80
PPM/°C
INSTRUCTION FLASH
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITION
Data retention
Flash programming
write cycles
MIN
TYP
MAX
UNIT
10
Years
1000
Cycles
tPROGWORD
Word programming
time
TA = –40°C to 85°C
40
µs
tMASSERASE
Mass-erase time
TA = –40°C to 85°C
40
ms
tPAGEERASE
Page-erase time
TA = –40°C to 85°C
40
ms
IFLASHREAD
Flash-read current
TA = –40°C to 85°C
2
mA
IFLASHWRITE
Flash-write current
TA = –40°C to 85°C
5
mA
IFLASHERASE
Flash-erase current
TA = –40°C to 85°C
15
mA
DATA FLASH
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITION
Data retention
Flash programming
write cycles
MIN
TYP
MAX
UNIT
10
Years
20000
Cycles
tPROGWORD
Word programming
time
TA = –40°C to 85°C
40
µs
tMASSERASE
Mass-erase time
TA = –40°C to 85°C
40
ms
tPAGEERASE
Page-erase time
TA = –40°C to 85°C
40
ms
IFLASHREAD
Flash-read current
TA = –40°C to 85°C
1
mA
IFLASHWRITE
Flash-write current
TA = –40°C to 85°C
5
mA
IFLASHERASE
Flash-erase current
TA = –40°C to 85°C
15
mA
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OCD, SCC, SCD1, SCD2 CURRENT PROTECTION THRESHOLDS
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITION
VOCD = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 1
OCD detection
threshold voltage range VOCD = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 0
VOCD
OCD detection
threshold voltage
program step
ΔVOCD
SCC detection
threshold voltage
program step
ΔVSCC
SCD1 detection
threshold voltage
program step
ΔVSCD1
VSCD2
SCD2 detection
threshold voltage
program step
ΔVSCD2
VOFFSET
OCD, SCC, and SCDx
offset error
VSCALE
OCD, SCC, and SCDx
scale error
–100
–8.3
–50
UNIT
mV
VOCD = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 0
–2.78
mV
44.4
200
22.2
100
mV
VSCC = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 1
22.2
VSCC = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 0
11.1
mV
–44.4
–200
–22.2
–100
mV
VSCD1 = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 1
–22.2
VSCD1 = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 0
–11.1
VSCD2 = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 1
SCD2 detection
threshold voltage range VSCD2 = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 0
MAX
–16.6
–5.56
VSCD1 = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 1
SCD1 detection
threshold voltage range VSCD1 = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 0
VSCD1
TYP
VOCD = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 1
VSCC = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 1
SCC detection
threshold voltage range VSCC = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 0
VSCC
MIN
mV
–44.4
–200
–22.2
–100
mV
VSCD2 = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 1
–22.2
VSCD2 = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 0
–11.1
mV
Post-trim
–2.5
2.5
No trim
–10
10
Post-trim
–5
5
mV
%
OCD, SCC, SCD1, SCD2 CURRENT PROTECTION TIMING
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
tOCD
OCD detection
delay time
ΔtOCD
OCD detection
delay time
program step
tSCC
SCC detection
delay time
ΔtSCC
SCC detection
delay time
program step
16
TEST CONDITION
MIN
TYP
1
MAX
UNIT
31
ms
2
0
915
61
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Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
tSCD1
SCD1 detection
delay time
AFE PROTECTION CONTROL[SCDDx2] = 0
0
915
AFE PROTECTION CONTROL[SCDDx2] = 1
0
1850
SCD1 detection
delay time
program step
AFE PROTECTION CONTROL[SCDDx2] = 0
61
ΔtSCD1
AFE PROTECTION CONTROL[SCDDx2] = 1
121
tSCD2
SCD2 detection
delay time
AFE PROTECTION CONTROL[SCDDx2] = 0
0
458
AFE PROTECTION CONTROL[SCDDx2] = 1
0
915
SCD2 detection
delay time
program step
AFE PROTECTION CONTROL[SCDDx2] = 0
30.5
ΔtSCD2
AFE PROTECTION CONTROL[SCDDx2] = 1
61
tDETECT
Current fault
detect time
VSRP – VSRN = VT – 3 mV for OCD, SCD1, and SC2,
VSRP – VSRN = VT + 3 mV for SCC
tACC
Current fault
delay time
accuracy
Max delay setting
–10
UNIT
µs
µs
µs
µs
160
µs
10
%
SMBus
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
100
kHz
fSMB
SMBus operating
frequency
SLAVE mode, SMBC 50% duty cycle
fMAS
SMBus master clock
frequency
MASTER mode, no clock low slave extend
tBUF
Bus free time between start
and stop
4.7
µs
tHD(START)
Hold time after (repeated)
start
4.0
µs
tSU(START)
Repeated start setup time
4.7
µs
tSU(STOP)
Stop setup time
4.0
µs
tHD(DATA)
Data hold time
300
ns
tSU(DATA)
Data setup time
250
ns
tTIMEOUT
Error signal detect time
25
tLOW
Clock low period
4.7
tHIGH
Clock high period
4.0
tR
Clock rise time
tF
Clock fall time
10
51.2
kHz
35
ms
µs
50
µs
10% to 90%
1000
ns
90% to 10%
300
ns
tLOW(SEXT)
Cumulative clock low slave
extend time
25
ms
tLOW(MEXT)
Cumulative clock low
master extend time
10
ms
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Figure 6. SMBus Timing Diagram
SMBus XL
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITION
40
TYP
MAX
UNIT
400
kHz
SMBus XL operating
frequency
tBUF
Bus free time between start
and stop
4.7
µs
tHD(START)
Hold time after (repeated)
start
4.0
µs
tSU(START)
Repeated start setup time
4.7
µs
tSU(STOP)
Stop setup time
4.0
tTIMEOUT
Error signal detect time
tLOW
tHIGH
18
SLAVE mode
MIN
fSMBXL
5
µs
20
ms
Clock low period
20
µs
Clock high period
20
µs
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SLUSBS8 – DECEMBER 2013
FEATURE SET
Primary (1st Level) Safety Features
The bq40z50 supports a wide range of battery and system protection features that can easily be configured. The
primary safety features include:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Cell Overvoltage Protection
Cell Undervoltage Protection
Cell Undervoltage Protection Compensated
Overcurrent in Charge Protection
Overcurrent in Discharge Protection
Overload in Discharge Protection
Short Circuit in Charge Protection
Short Circuit in Discharge Protection
Overtemperature in Charge Protection
Overtemperature in Discharge Protection
Undertemperature in Charge Protection
Undertemperature in Discharge Protection
Overtemperature FET protection
Precharge Timeout Protection
Host Watchdog Timeout Protection
Fast Charge Timeout Protection
Overcharge Protection
Overcharging Voltage Protection
Overcharging Current Protection
Over Precharge Current Protection
Secondary (2nd Level) Safety Features
The secondary safety features of the bq40z50 can be used to indicate more serious faults via the FUSE pin. This
pin can be used to blow an in-line fuse to permanently disable the battery pack from charging or discharging. The
secondary safety features provide protection against:
• Safety Overvoltage Permanent Failure
• Safety Undervoltage Permanent Failure
• Safety Overtemperature Permanent Failure
• Safety FET Overtemperature Permanent Failure
• Qmax Imbalance Permanent Failure
• Impedance Imbalance Permanent Failure
• Capacity Degradation Permanent Failure
• Cell Balancing Permanent Failure
• Fuse Failure Permanent Failure
• PTC Permanent Failure
• Voltage Imbalance at Rest Permanent Failure
• Voltage Imbalance Active Permanent Failure
• Charge FET Permanent Failure
• Discharge FET Permanent Failure
• AFE Register Permanent Failure
• AFE Communication Permanent Failure
• Second Level Protector Permanent Failure
• Instruction Flash Checksum Permanent Failure
• Open Cell Connection Permanent Failure
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bq40z50
SLUSBS8 – DECEMBER 2013
•
•
www.ti.com
Data Flash Permanent Failure
Open Thermistor Permanent Failure
Charge Control Features
The bq40z50 charge control features include:
•
•
•
•
•
•
•
Supports JEITA temperature ranges. Reports charging voltage and charging current according to the active
temperature range
Handles more complex charging profiles. Allows for splitting the standard temperature range into two subranges and allows for varying the charging current according to the cell voltage
Reports the appropriate charging current needed for constant current charging and the appropriate charging
voltage needed for constant voltage charging to a smart charger using SMBus broadcasts
Reduces the charge difference of the battery cells in fully charged state of the battery pack gradually using a
voltage-based cell balancing algorithm during charging. A voltage threshold can be set up for cell balancing to
be active. This prevents fully charged cells from overcharging and causing excessive degradation and also
increases the usable pack energy by preventing premature charge termination.
Supports pre-charging/zero-volt charging
Supports charge inhibit and charge suspend if battery pack temperature is out of temperature range
Reports charging fault and also indicates charge status via charge and discharge alarms
Gas Gauging
The bq40z50 uses the Impedance Track algorithm to measure and calculate the available capacity in battery
cells. The bq40z50 accumulates a measure of charge and discharge currents and compensates the charge
current measurement for the temperature and state-of-charge of the battery. The bq40z50 estimates selfdischarge of the battery and also adjusts the self-discharge estimation based on temperature. The device also
has TURBO BOOST mode support, which enables the bq40z50 to provide the necessary data for the MCU to
determine what level of peak power consumption can be applied without causing a system reset or transient
battery voltage level spike to trigger termination flags. See the bq40z50 Technical Reference Manual (SLUUA43)
for further details.
Battery Trip Point (BTP)
Required for WIN8 OS, the battery trip point (BTP) feature indicates when the RSOC of a battery pack has
depleted to a certain value set in a DF register. This feature allows a host to program two capacity-based
thresholds that govern the triggering of a BTP interrupt on the BTP_INT pin and the setting or clearing of the
OperationStatus[BTP_INT] on the basis of RemainingCapacity().
An internal weak pull-up is applied when the BTP feature is active. Depending on the system design, an external
pull-up may required to put on the BTP_INT pin. See PRES, BTP_INT, DISP for details.
Lifetime Data Logging Features
The bq40z50 offers lifetime data logging for several critical battery parameters. The following parameters are
updated every 10 hours if a difference is detected between values in RAM and data flash:
• Maximum and Minimum Cell Voltages
• Maximum Delta Cell Voltage
• Maximum Charge Current
• Maximum Discharge Current
• Maximum Average Discharge Current
• Maximum Average Discharge Power
• Maximum and Minimum Cell Temperature
• Maximum Delta Cell Temperature
• Maximum and Minimum Internal Sensor Temperature
• Maximum FET Temperature
• Number of Safety Events Occurrences and the Last Cycle of the Occurrence
• Number of Valid Charge Termination and the Last Cycle of the Valid Charge Termination
20
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•
•
•
•
SLUSBS8 – DECEMBER 2013
Number of Qmax and Ra Updates and the Last Cycle of the Qmax and Ra Updates
Number of Shutdown Events
Cell Balancing Time for Each Cell
(This data is updated every 2 hours if a difference is detected.)
Total FW Runtime and Time Spent in Each Temperature Range
(This data is updated every 2 hours if a difference is detected.)
Authentication
The bq40z50 supports authentication by the host using SHA-1.
LED Display
The bq40z50 can drive a 3-, 4-, or 5- segment LED display for remaining capacity indication and/or a permanent
fail (PF) error code indication.
Power Modes
The bq40z50 supports three power modes to reduce power consumption:
• In NORMAL mode, the bq40z50 performs measurements, calculations, protection decisions, and data
updates in 250-ms intervals. Between these intervals, the bq40z50 is in a reduced power stage.
• In SLEEP mode, the bq40z50 performs measurements, calculations, protection decisions, and data updates
in adjustable time intervals. Between these intervals, the bq40z50 is in a reduced power stage. The bq40z50
has a wake function that enables exit from SLEEP mode when current flow or failure is detected.
• In SHUTDOWN mode, the bq40z50 is completely disabled.
Configuration
Oscillator Function
The bq40z50 fully integrates the system oscillators and does not require any external components to support this
feature.
System Present Operation
The bq40z50 checks the PRES pin periodically (1 s). If PRES input is pulled to ground by the external system,
the bq40z50 detects this as system present.
Emergency Shutdown
For battery maintenance, the emergency shutdown feature enables a push button action connecting the
SHUTDN pin to shutdown an embedded battery pack system before removing the battery. A high-to-low
transition of the SHUTDN pin signals the bq40z50 to turn off both CHG and DSG FETs, disconnecting the power
from the system to safely remove the battery pack. The CHG and DSG FETs can be turned on again by another
high-to-low transition detected by the SHUTDN pin or when a data flash configurable timeout is reached.
1-Series, 2-Series, 3-Series, or 4-Series Cell Configuration
In a 1-series cell configuration, VC4 is shorted to VC, VC2 and VC1. In a 2-series cell configuration, VC4 is
shorted to VC3 and VC2. In a 3-series cell configuration, VC4 is shorted to VC3.
Cell Balancing
The device supports cell balancing by bypassing the current of each cell during charging or at rest. If the device's
internal bypass is used, up to 10 mA can be bypassed and multiple cells can be bypassed at the same time.
Higher cell balance current can be achieved by using an external cell balancing circuit. In external cell balancing
mode, only one cell at a time can be balanced.
The cell balancing algorithm determines the amount of charge needed to be bypassed to balance the capacity of
all cells.
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bq40z50
SLUSBS8 – DECEMBER 2013
www.ti.com
BATTERY PARAMETER MEASUREMENTS
Charge and Discharge Counting
The bq40z50 uses an integrating delta-sigma analog-to-digital converter (ADC) for current measurement, and a
second delta-sigma ADC for individual cell and battery voltage and temperature measurement.
The integrating delta-sigma ADC measures the charge/discharge flow of the battery by measuring the voltage
drop across a small-value sense resistor between the SRP and SRN pins. The integrating ADC measures bipolar
signals from –0.1 V to 0.1 V. The bq40z50 detects charge activity when VSR = V(SRP) – V(SRN) is positive, and
discharge activity when VSR = V(SRP) – V(SRN) is negative. The bq40z50 continuously integrates the signal over
time, using an internal counter. The fundamental rate of the counter is 0.26 nVh.
Voltage
The bq40z50 updates the individual series cell voltages at 0.25-second intervals. The internal ADC of the
bq40z50 measures the voltage, and scales and calibrates it appropriately. This data is also used to calculate the
impedance of the cell for the Impedance Track gas gauging.
Current
The bq40z50 uses the SRP and SRN inputs to measure and calculate the battery charge and discharge current
using a 1-mΩ to 3-mΩ typ. sense resistor.
Temperature
The bq40z50 has an internal temperature sensor and inputs for four external temperature sensors. All five
temperature sensor options can be individually enabled and configured for cell or FET temperature usage. Two
configurable thermistor models are provided to allow the monitoring of cell temperature in addition to FET
temperature, which use a different thermistor profile.
Communications
The bq40z50 uses SMBus v1.1 with MASTER mode and packet error checking (PEC) options per the SBS
specification.
SMBus On and Off State
The bq40z50 detects an SMBus off state when SMBC and SMBD are low for two or more seconds. Clearing this
state requires that either SMBC or SMBD transition high. The communication bus will resume activity within
1 ms.
SBS Commands
See the bq40z50 Technical Reference Manual (SLUUA43) for further details.
22
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Product Folder Links: bq40z50
1
2
1N
AGND
3
2P
2
3P
1P J5
1
J1
4P
4P
GND
NT1
Net-Tie
1
3
100
R22
100
R23
4
3
2
1
0.1uF
C14
V2
V3
V4
GND
Place RT1 close to Q2 and Q3.
0.1uF
C15
5
6
7
8
Replace D1 and R9 with a 10 ohm resistor for single cell applications.
V1
VSS
CD
OUT
U2
BQ2947xyDSG
VDD
C7
3
GND
TP3
0.1uF
C17
R19
0.001
DNP
GND
R31
100
R30
100
C19
0.1uF
SRN
C18
GND
8
7
6
5
4
3
2
2.2uF
1
5.1K
5.1K
C13
R17
R16
C3
0.1uF
R6
5.1K
R7
3
CHG
DNP
C20
SRP
NC
SRN
VC1
VC2
VC3
VC4
PBI
1
GND
Q2
Si7116DN
SRP
BAT
1
2
3
FUSEPIN
10M
R2
51K
Q5
Si1406DH
D1
BAT54HT1
AGND
BAT
0.1uF
0.1uF
C16
0.1uF
C6
3
SFDxxxx
2
300
GND
10K
RT2
10M
R5
3
Q1
FDN358P
10M
R8
2
R9
GND
DSG
100
BQ40Z50RSM
U1
10K
RT3
GND
GND
GND
10K
RT4
4
10K
RT5
3
2
1
5.1K
R10
TP12
PTC
PTCEN
GND
0.1uF
C21
B
B'
B
B'
GND
LED DISPLAY
A
A'
S2
SHUTDOWN
17
18
19
20
21
22
23
24
10K
R12
10M
R3
A
A'
S3
DISP
SMBD
SMBC
LEDCNTLA
LEDCNTLB
LEDCNTLC
Q3
Si7116DN
200
R28
GND
200 1
2
R26
200
R24
D7
L
D5
R4
J7
D2
BAT
10K
CHGND
Q4
2N7002K
1
D8
D6
RT1
D9
2
10K
0.1uF
CHGND
D3
C12
D4
BAT
CHGND
1K
R29
100
R27
100
R25
PACK+
SMBC
L
CHGND
L
GND SIDE
J2
1
2
3
VSS
SMBC
SMBD
ED3 ED5 ED2 ED4 ED1
4
SMBD
L
C10
0.1uF
0.1uF
C8
CHGND
L
PACK+
J3
1
PACK-
PACK+
3
2
PACK-
Sys Pres
1
J4
2
PACK+
www.ti.com
2
1
100
R21
0.1uF
C11
0.1uF
C9
0.1uF
C5
0.1uF
C4
IC ground should be connected to the 1N cell tab.
100
R20
1K
R18
1K
R15
1K
R14
1K
R13
100
FUSE
3
6
4
1
1
F1
1
5
1
1
5
1
1
R11
EP
9
1
1
1
5
2
1
1
1
31
BAT
33
PWPD
32
CHG
VSS
9
4
1
1
TS2
11
27
1
1
1
TS3
12
TS1
10
30
PCHG
29
NC
28
DSG
TS4
13
PACK
NC
14
25
2
3
C2
MM3ZxxVyC
0.1uF
SMBD
0.1uF
MM3ZxxVyC
26
VCC
BTP_INT
15
FUSE
PRESorSHUTDN
16
1
1
1
1
1
2
C1
SMBD
1
2
SMBC
SMBC
Product Folder Links: bq40z50
1
Copyright © 2013, Texas Instruments Incorporated
GND SIDE2
1
1
1
2
R1
GND SIDE
4P
bq40z50
SLUSBS8 – DECEMBER 2013
APPLICATION SCHEMATIC
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23
GND SIDE
MM3ZxxVyC
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jan-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ40Z50RSMR
ACTIVE
VQFN
RSM
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ40Z50
BQ40Z50RSMT
ACTIVE
VQFN
RSM
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ40Z50
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jan-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jan-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
BQ40Z50RSMR
VQFN
RSM
32
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
BQ40Z50RSMT
VQFN
RSM
32
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jan-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ40Z50RSMR
VQFN
RSM
32
3000
367.0
367.0
35.0
BQ40Z50RSMT
VQFN
RSM
32
250
210.0
185.0
35.0
Pack Materials-Page 2
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